1 #include <linux/device.h> 2 #include <linux/cpu.h> 3 #include <linux/smp.h> 4 #include <linux/percpu.h> 5 #include <linux/init.h> 6 #include <linux/sched.h> 7 #include <linux/export.h> 8 #include <linux/nodemask.h> 9 #include <linux/cpumask.h> 10 #include <linux/notifier.h> 11 12 #include <asm/current.h> 13 #include <asm/processor.h> 14 #include <asm/cputable.h> 15 #include <asm/hvcall.h> 16 #include <asm/prom.h> 17 #include <asm/machdep.h> 18 #include <asm/smp.h> 19 #include <asm/pmc.h> 20 #include <asm/firmware.h> 21 22 #include "cacheinfo.h" 23 24 #ifdef CONFIG_PPC64 25 #include <asm/paca.h> 26 #include <asm/lppaca.h> 27 #endif 28 29 static DEFINE_PER_CPU(struct cpu, cpu_devices); 30 31 /* 32 * SMT snooze delay stuff, 64-bit only for now 33 */ 34 35 #ifdef CONFIG_PPC64 36 37 /* Time in microseconds we delay before sleeping in the idle loop */ 38 DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 }; 39 40 static ssize_t store_smt_snooze_delay(struct device *dev, 41 struct device_attribute *attr, 42 const char *buf, 43 size_t count) 44 { 45 struct cpu *cpu = container_of(dev, struct cpu, dev); 46 ssize_t ret; 47 long snooze; 48 49 ret = sscanf(buf, "%ld", &snooze); 50 if (ret != 1) 51 return -EINVAL; 52 53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze; 54 return count; 55 } 56 57 static ssize_t show_smt_snooze_delay(struct device *dev, 58 struct device_attribute *attr, 59 char *buf) 60 { 61 struct cpu *cpu = container_of(dev, struct cpu, dev); 62 63 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id)); 64 } 65 66 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay, 67 store_smt_snooze_delay); 68 69 static int __init setup_smt_snooze_delay(char *str) 70 { 71 unsigned int cpu; 72 long snooze; 73 74 if (!cpu_has_feature(CPU_FTR_SMT)) 75 return 1; 76 77 snooze = simple_strtol(str, NULL, 10); 78 for_each_possible_cpu(cpu) 79 per_cpu(smt_snooze_delay, cpu) = snooze; 80 81 return 1; 82 } 83 __setup("smt-snooze-delay=", setup_smt_snooze_delay); 84 85 #endif /* CONFIG_PPC64 */ 86 87 #ifdef CONFIG_PPC_FSL_BOOK3E 88 #define MAX_BIT 63 89 90 static u64 pw20_wt; 91 static u64 altivec_idle_wt; 92 93 static unsigned int get_idle_ticks_bit(u64 ns) 94 { 95 u64 cycle; 96 97 if (ns >= 10000) 98 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec; 99 else 100 cycle = div_u64(ns * tb_ticks_per_usec, 1000); 101 102 if (!cycle) 103 return 0; 104 105 return ilog2(cycle); 106 } 107 108 static void do_show_pwrmgtcr0(void *val) 109 { 110 u32 *value = val; 111 112 *value = mfspr(SPRN_PWRMGTCR0); 113 } 114 115 static ssize_t show_pw20_state(struct device *dev, 116 struct device_attribute *attr, char *buf) 117 { 118 u32 value; 119 unsigned int cpu = dev->id; 120 121 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 122 123 value &= PWRMGTCR0_PW20_WAIT; 124 125 return sprintf(buf, "%u\n", value ? 1 : 0); 126 } 127 128 static void do_store_pw20_state(void *val) 129 { 130 u32 *value = val; 131 u32 pw20_state; 132 133 pw20_state = mfspr(SPRN_PWRMGTCR0); 134 135 if (*value) 136 pw20_state |= PWRMGTCR0_PW20_WAIT; 137 else 138 pw20_state &= ~PWRMGTCR0_PW20_WAIT; 139 140 mtspr(SPRN_PWRMGTCR0, pw20_state); 141 } 142 143 static ssize_t store_pw20_state(struct device *dev, 144 struct device_attribute *attr, 145 const char *buf, size_t count) 146 { 147 u32 value; 148 unsigned int cpu = dev->id; 149 150 if (kstrtou32(buf, 0, &value)) 151 return -EINVAL; 152 153 if (value > 1) 154 return -EINVAL; 155 156 smp_call_function_single(cpu, do_store_pw20_state, &value, 1); 157 158 return count; 159 } 160 161 static ssize_t show_pw20_wait_time(struct device *dev, 162 struct device_attribute *attr, char *buf) 163 { 164 u32 value; 165 u64 tb_cycle = 1; 166 u64 time; 167 168 unsigned int cpu = dev->id; 169 170 if (!pw20_wt) { 171 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 172 value = (value & PWRMGTCR0_PW20_ENT) >> 173 PWRMGTCR0_PW20_ENT_SHIFT; 174 175 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 176 /* convert ms to ns */ 177 if (tb_ticks_per_usec > 1000) { 178 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 179 } else { 180 u32 rem_us; 181 182 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 183 &rem_us); 184 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 185 } 186 } else { 187 time = pw20_wt; 188 } 189 190 return sprintf(buf, "%llu\n", time > 0 ? time : 0); 191 } 192 193 static void set_pw20_wait_entry_bit(void *val) 194 { 195 u32 *value = val; 196 u32 pw20_idle; 197 198 pw20_idle = mfspr(SPRN_PWRMGTCR0); 199 200 /* Set Automatic PW20 Core Idle Count */ 201 /* clear count */ 202 pw20_idle &= ~PWRMGTCR0_PW20_ENT; 203 204 /* set count */ 205 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT); 206 207 mtspr(SPRN_PWRMGTCR0, pw20_idle); 208 } 209 210 static ssize_t store_pw20_wait_time(struct device *dev, 211 struct device_attribute *attr, 212 const char *buf, size_t count) 213 { 214 u32 entry_bit; 215 u64 value; 216 217 unsigned int cpu = dev->id; 218 219 if (kstrtou64(buf, 0, &value)) 220 return -EINVAL; 221 222 if (!value) 223 return -EINVAL; 224 225 entry_bit = get_idle_ticks_bit(value); 226 if (entry_bit > MAX_BIT) 227 return -EINVAL; 228 229 pw20_wt = value; 230 231 smp_call_function_single(cpu, set_pw20_wait_entry_bit, 232 &entry_bit, 1); 233 234 return count; 235 } 236 237 static ssize_t show_altivec_idle(struct device *dev, 238 struct device_attribute *attr, char *buf) 239 { 240 u32 value; 241 unsigned int cpu = dev->id; 242 243 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 244 245 value &= PWRMGTCR0_AV_IDLE_PD_EN; 246 247 return sprintf(buf, "%u\n", value ? 1 : 0); 248 } 249 250 static void do_store_altivec_idle(void *val) 251 { 252 u32 *value = val; 253 u32 altivec_idle; 254 255 altivec_idle = mfspr(SPRN_PWRMGTCR0); 256 257 if (*value) 258 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN; 259 else 260 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN; 261 262 mtspr(SPRN_PWRMGTCR0, altivec_idle); 263 } 264 265 static ssize_t store_altivec_idle(struct device *dev, 266 struct device_attribute *attr, 267 const char *buf, size_t count) 268 { 269 u32 value; 270 unsigned int cpu = dev->id; 271 272 if (kstrtou32(buf, 0, &value)) 273 return -EINVAL; 274 275 if (value > 1) 276 return -EINVAL; 277 278 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1); 279 280 return count; 281 } 282 283 static ssize_t show_altivec_idle_wait_time(struct device *dev, 284 struct device_attribute *attr, char *buf) 285 { 286 u32 value; 287 u64 tb_cycle = 1; 288 u64 time; 289 290 unsigned int cpu = dev->id; 291 292 if (!altivec_idle_wt) { 293 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 294 value = (value & PWRMGTCR0_AV_IDLE_CNT) >> 295 PWRMGTCR0_AV_IDLE_CNT_SHIFT; 296 297 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 298 /* convert ms to ns */ 299 if (tb_ticks_per_usec > 1000) { 300 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 301 } else { 302 u32 rem_us; 303 304 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 305 &rem_us); 306 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 307 } 308 } else { 309 time = altivec_idle_wt; 310 } 311 312 return sprintf(buf, "%llu\n", time > 0 ? time : 0); 313 } 314 315 static void set_altivec_idle_wait_entry_bit(void *val) 316 { 317 u32 *value = val; 318 u32 altivec_idle; 319 320 altivec_idle = mfspr(SPRN_PWRMGTCR0); 321 322 /* Set Automatic AltiVec Idle Count */ 323 /* clear count */ 324 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT; 325 326 /* set count */ 327 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT); 328 329 mtspr(SPRN_PWRMGTCR0, altivec_idle); 330 } 331 332 static ssize_t store_altivec_idle_wait_time(struct device *dev, 333 struct device_attribute *attr, 334 const char *buf, size_t count) 335 { 336 u32 entry_bit; 337 u64 value; 338 339 unsigned int cpu = dev->id; 340 341 if (kstrtou64(buf, 0, &value)) 342 return -EINVAL; 343 344 if (!value) 345 return -EINVAL; 346 347 entry_bit = get_idle_ticks_bit(value); 348 if (entry_bit > MAX_BIT) 349 return -EINVAL; 350 351 altivec_idle_wt = value; 352 353 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit, 354 &entry_bit, 1); 355 356 return count; 357 } 358 359 /* 360 * Enable/Disable interface: 361 * 0, disable. 1, enable. 362 */ 363 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state); 364 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle); 365 366 /* 367 * Set wait time interface:(Nanosecond) 368 * Example: Base on TBfreq is 41MHZ. 369 * 1~48(ns): TB[63] 370 * 49~97(ns): TB[62] 371 * 98~195(ns): TB[61] 372 * 196~390(ns): TB[60] 373 * 391~780(ns): TB[59] 374 * 781~1560(ns): TB[58] 375 * ... 376 */ 377 static DEVICE_ATTR(pw20_wait_time, 0600, 378 show_pw20_wait_time, 379 store_pw20_wait_time); 380 static DEVICE_ATTR(altivec_idle_wait_time, 0600, 381 show_altivec_idle_wait_time, 382 store_altivec_idle_wait_time); 383 #endif 384 385 /* 386 * Enabling PMCs will slow partition context switch times so we only do 387 * it the first time we write to the PMCs. 388 */ 389 390 static DEFINE_PER_CPU(char, pmcs_enabled); 391 392 void ppc_enable_pmcs(void) 393 { 394 ppc_set_pmu_inuse(1); 395 396 /* Only need to enable them once */ 397 if (__get_cpu_var(pmcs_enabled)) 398 return; 399 400 __get_cpu_var(pmcs_enabled) = 1; 401 402 if (ppc_md.enable_pmcs) 403 ppc_md.enable_pmcs(); 404 } 405 EXPORT_SYMBOL(ppc_enable_pmcs); 406 407 #define __SYSFS_SPRSETUP(NAME, ADDRESS, EXTRA) \ 408 static void read_##NAME(void *val) \ 409 { \ 410 *(unsigned long *)val = mfspr(ADDRESS); \ 411 } \ 412 static void write_##NAME(void *val) \ 413 { \ 414 EXTRA; \ 415 mtspr(ADDRESS, *(unsigned long *)val); \ 416 } \ 417 static ssize_t show_##NAME(struct device *dev, \ 418 struct device_attribute *attr, \ 419 char *buf) \ 420 { \ 421 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 422 unsigned long val; \ 423 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \ 424 return sprintf(buf, "%lx\n", val); \ 425 } \ 426 static ssize_t __used \ 427 store_##NAME(struct device *dev, struct device_attribute *attr, \ 428 const char *buf, size_t count) \ 429 { \ 430 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 431 unsigned long val; \ 432 int ret = sscanf(buf, "%lx", &val); \ 433 if (ret != 1) \ 434 return -EINVAL; \ 435 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \ 436 return count; \ 437 } 438 439 #define SYSFS_PMCSETUP(NAME, ADDRESS) \ 440 __SYSFS_SPRSETUP(NAME, ADDRESS, ppc_enable_pmcs()) 441 #define SYSFS_SPRSETUP(NAME, ADDRESS) \ 442 __SYSFS_SPRSETUP(NAME, ADDRESS, ) 443 444 /* Let's define all possible registers, we'll only hook up the ones 445 * that are implemented on the current processor 446 */ 447 448 #if defined(CONFIG_PPC64) 449 #define HAS_PPC_PMC_CLASSIC 1 450 #define HAS_PPC_PMC_IBM 1 451 #define HAS_PPC_PMC_PA6T 1 452 #elif defined(CONFIG_6xx) 453 #define HAS_PPC_PMC_CLASSIC 1 454 #define HAS_PPC_PMC_IBM 1 455 #define HAS_PPC_PMC_G4 1 456 #endif 457 458 459 #ifdef HAS_PPC_PMC_CLASSIC 460 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0); 461 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1); 462 SYSFS_PMCSETUP(pmc1, SPRN_PMC1); 463 SYSFS_PMCSETUP(pmc2, SPRN_PMC2); 464 SYSFS_PMCSETUP(pmc3, SPRN_PMC3); 465 SYSFS_PMCSETUP(pmc4, SPRN_PMC4); 466 SYSFS_PMCSETUP(pmc5, SPRN_PMC5); 467 SYSFS_PMCSETUP(pmc6, SPRN_PMC6); 468 469 #ifdef HAS_PPC_PMC_G4 470 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2); 471 #endif 472 473 #ifdef CONFIG_PPC64 474 SYSFS_PMCSETUP(pmc7, SPRN_PMC7); 475 SYSFS_PMCSETUP(pmc8, SPRN_PMC8); 476 477 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA); 478 SYSFS_SPRSETUP(purr, SPRN_PURR); 479 SYSFS_SPRSETUP(spurr, SPRN_SPURR); 480 SYSFS_SPRSETUP(dscr, SPRN_DSCR); 481 SYSFS_SPRSETUP(pir, SPRN_PIR); 482 483 /* 484 Lets only enable read for phyp resources and 485 enable write when needed with a separate function. 486 Lets be conservative and default to pseries. 487 */ 488 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra); 489 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL); 490 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr); 491 static DEVICE_ATTR(purr, 0400, show_purr, store_purr); 492 static DEVICE_ATTR(pir, 0400, show_pir, NULL); 493 494 unsigned long dscr_default = 0; 495 EXPORT_SYMBOL(dscr_default); 496 497 static void add_write_permission_dev_attr(struct device_attribute *attr) 498 { 499 attr->attr.mode |= 0200; 500 } 501 502 static ssize_t show_dscr_default(struct device *dev, 503 struct device_attribute *attr, char *buf) 504 { 505 return sprintf(buf, "%lx\n", dscr_default); 506 } 507 508 static void update_dscr(void *dummy) 509 { 510 if (!current->thread.dscr_inherit) { 511 current->thread.dscr = dscr_default; 512 mtspr(SPRN_DSCR, dscr_default); 513 } 514 } 515 516 static ssize_t __used store_dscr_default(struct device *dev, 517 struct device_attribute *attr, const char *buf, 518 size_t count) 519 { 520 unsigned long val; 521 int ret = 0; 522 523 ret = sscanf(buf, "%lx", &val); 524 if (ret != 1) 525 return -EINVAL; 526 dscr_default = val; 527 528 on_each_cpu(update_dscr, NULL, 1); 529 530 return count; 531 } 532 533 static DEVICE_ATTR(dscr_default, 0600, 534 show_dscr_default, store_dscr_default); 535 536 static void sysfs_create_dscr_default(void) 537 { 538 int err = 0; 539 if (cpu_has_feature(CPU_FTR_DSCR)) 540 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default); 541 } 542 #endif /* CONFIG_PPC64 */ 543 544 #ifdef HAS_PPC_PMC_PA6T 545 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0); 546 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1); 547 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2); 548 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3); 549 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4); 550 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5); 551 #ifdef CONFIG_DEBUG_KERNEL 552 SYSFS_SPRSETUP(hid0, SPRN_HID0); 553 SYSFS_SPRSETUP(hid1, SPRN_HID1); 554 SYSFS_SPRSETUP(hid4, SPRN_HID4); 555 SYSFS_SPRSETUP(hid5, SPRN_HID5); 556 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0); 557 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1); 558 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2); 559 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3); 560 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4); 561 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5); 562 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6); 563 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7); 564 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8); 565 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9); 566 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT); 567 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR); 568 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR); 569 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR); 570 SYSFS_SPRSETUP(der, SPRN_PA6T_DER); 571 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER); 572 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER); 573 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER); 574 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER); 575 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR); 576 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0); 577 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1); 578 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2); 579 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3); 580 #endif /* CONFIG_DEBUG_KERNEL */ 581 #endif /* HAS_PPC_PMC_PA6T */ 582 583 #ifdef HAS_PPC_PMC_IBM 584 static struct device_attribute ibm_common_attrs[] = { 585 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 586 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 587 }; 588 #endif /* HAS_PPC_PMC_G4 */ 589 590 #ifdef HAS_PPC_PMC_G4 591 static struct device_attribute g4_common_attrs[] = { 592 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 593 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 594 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2), 595 }; 596 #endif /* HAS_PPC_PMC_G4 */ 597 598 static struct device_attribute classic_pmc_attrs[] = { 599 __ATTR(pmc1, 0600, show_pmc1, store_pmc1), 600 __ATTR(pmc2, 0600, show_pmc2, store_pmc2), 601 __ATTR(pmc3, 0600, show_pmc3, store_pmc3), 602 __ATTR(pmc4, 0600, show_pmc4, store_pmc4), 603 __ATTR(pmc5, 0600, show_pmc5, store_pmc5), 604 __ATTR(pmc6, 0600, show_pmc6, store_pmc6), 605 #ifdef CONFIG_PPC64 606 __ATTR(pmc7, 0600, show_pmc7, store_pmc7), 607 __ATTR(pmc8, 0600, show_pmc8, store_pmc8), 608 #endif 609 }; 610 611 #ifdef HAS_PPC_PMC_PA6T 612 static struct device_attribute pa6t_attrs[] = { 613 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 614 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 615 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0), 616 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1), 617 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2), 618 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3), 619 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4), 620 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5), 621 #ifdef CONFIG_DEBUG_KERNEL 622 __ATTR(hid0, 0600, show_hid0, store_hid0), 623 __ATTR(hid1, 0600, show_hid1, store_hid1), 624 __ATTR(hid4, 0600, show_hid4, store_hid4), 625 __ATTR(hid5, 0600, show_hid5, store_hid5), 626 __ATTR(ima0, 0600, show_ima0, store_ima0), 627 __ATTR(ima1, 0600, show_ima1, store_ima1), 628 __ATTR(ima2, 0600, show_ima2, store_ima2), 629 __ATTR(ima3, 0600, show_ima3, store_ima3), 630 __ATTR(ima4, 0600, show_ima4, store_ima4), 631 __ATTR(ima5, 0600, show_ima5, store_ima5), 632 __ATTR(ima6, 0600, show_ima6, store_ima6), 633 __ATTR(ima7, 0600, show_ima7, store_ima7), 634 __ATTR(ima8, 0600, show_ima8, store_ima8), 635 __ATTR(ima9, 0600, show_ima9, store_ima9), 636 __ATTR(imaat, 0600, show_imaat, store_imaat), 637 __ATTR(btcr, 0600, show_btcr, store_btcr), 638 __ATTR(pccr, 0600, show_pccr, store_pccr), 639 __ATTR(rpccr, 0600, show_rpccr, store_rpccr), 640 __ATTR(der, 0600, show_der, store_der), 641 __ATTR(mer, 0600, show_mer, store_mer), 642 __ATTR(ber, 0600, show_ber, store_ber), 643 __ATTR(ier, 0600, show_ier, store_ier), 644 __ATTR(sier, 0600, show_sier, store_sier), 645 __ATTR(siar, 0600, show_siar, store_siar), 646 __ATTR(tsr0, 0600, show_tsr0, store_tsr0), 647 __ATTR(tsr1, 0600, show_tsr1, store_tsr1), 648 __ATTR(tsr2, 0600, show_tsr2, store_tsr2), 649 __ATTR(tsr3, 0600, show_tsr3, store_tsr3), 650 #endif /* CONFIG_DEBUG_KERNEL */ 651 }; 652 #endif /* HAS_PPC_PMC_PA6T */ 653 #endif /* HAS_PPC_PMC_CLASSIC */ 654 655 static void register_cpu_online(unsigned int cpu) 656 { 657 struct cpu *c = &per_cpu(cpu_devices, cpu); 658 struct device *s = &c->dev; 659 struct device_attribute *attrs, *pmc_attrs; 660 int i, nattrs; 661 662 #ifdef CONFIG_PPC64 663 if (cpu_has_feature(CPU_FTR_SMT)) 664 device_create_file(s, &dev_attr_smt_snooze_delay); 665 #endif 666 667 /* PMC stuff */ 668 switch (cur_cpu_spec->pmc_type) { 669 #ifdef HAS_PPC_PMC_IBM 670 case PPC_PMC_IBM: 671 attrs = ibm_common_attrs; 672 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); 673 pmc_attrs = classic_pmc_attrs; 674 break; 675 #endif /* HAS_PPC_PMC_IBM */ 676 #ifdef HAS_PPC_PMC_G4 677 case PPC_PMC_G4: 678 attrs = g4_common_attrs; 679 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); 680 pmc_attrs = classic_pmc_attrs; 681 break; 682 #endif /* HAS_PPC_PMC_G4 */ 683 #ifdef HAS_PPC_PMC_PA6T 684 case PPC_PMC_PA6T: 685 /* PA Semi starts counting at PMC0 */ 686 attrs = pa6t_attrs; 687 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); 688 pmc_attrs = NULL; 689 break; 690 #endif /* HAS_PPC_PMC_PA6T */ 691 default: 692 attrs = NULL; 693 nattrs = 0; 694 pmc_attrs = NULL; 695 } 696 697 for (i = 0; i < nattrs; i++) 698 device_create_file(s, &attrs[i]); 699 700 if (pmc_attrs) 701 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 702 device_create_file(s, &pmc_attrs[i]); 703 704 #ifdef CONFIG_PPC64 705 if (cpu_has_feature(CPU_FTR_MMCRA)) 706 device_create_file(s, &dev_attr_mmcra); 707 708 if (cpu_has_feature(CPU_FTR_PURR)) { 709 if (!firmware_has_feature(FW_FEATURE_LPAR)) 710 add_write_permission_dev_attr(&dev_attr_purr); 711 device_create_file(s, &dev_attr_purr); 712 } 713 714 if (cpu_has_feature(CPU_FTR_SPURR)) 715 device_create_file(s, &dev_attr_spurr); 716 717 if (cpu_has_feature(CPU_FTR_DSCR)) 718 device_create_file(s, &dev_attr_dscr); 719 720 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 721 device_create_file(s, &dev_attr_pir); 722 #endif /* CONFIG_PPC64 */ 723 724 #ifdef CONFIG_PPC_FSL_BOOK3E 725 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 726 device_create_file(s, &dev_attr_pw20_state); 727 device_create_file(s, &dev_attr_pw20_wait_time); 728 729 device_create_file(s, &dev_attr_altivec_idle); 730 device_create_file(s, &dev_attr_altivec_idle_wait_time); 731 } 732 #endif 733 cacheinfo_cpu_online(cpu); 734 } 735 736 #ifdef CONFIG_HOTPLUG_CPU 737 static void unregister_cpu_online(unsigned int cpu) 738 { 739 struct cpu *c = &per_cpu(cpu_devices, cpu); 740 struct device *s = &c->dev; 741 struct device_attribute *attrs, *pmc_attrs; 742 int i, nattrs; 743 744 BUG_ON(!c->hotpluggable); 745 746 #ifdef CONFIG_PPC64 747 if (cpu_has_feature(CPU_FTR_SMT)) 748 device_remove_file(s, &dev_attr_smt_snooze_delay); 749 #endif 750 751 /* PMC stuff */ 752 switch (cur_cpu_spec->pmc_type) { 753 #ifdef HAS_PPC_PMC_IBM 754 case PPC_PMC_IBM: 755 attrs = ibm_common_attrs; 756 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); 757 pmc_attrs = classic_pmc_attrs; 758 break; 759 #endif /* HAS_PPC_PMC_IBM */ 760 #ifdef HAS_PPC_PMC_G4 761 case PPC_PMC_G4: 762 attrs = g4_common_attrs; 763 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); 764 pmc_attrs = classic_pmc_attrs; 765 break; 766 #endif /* HAS_PPC_PMC_G4 */ 767 #ifdef HAS_PPC_PMC_PA6T 768 case PPC_PMC_PA6T: 769 /* PA Semi starts counting at PMC0 */ 770 attrs = pa6t_attrs; 771 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); 772 pmc_attrs = NULL; 773 break; 774 #endif /* HAS_PPC_PMC_PA6T */ 775 default: 776 attrs = NULL; 777 nattrs = 0; 778 pmc_attrs = NULL; 779 } 780 781 for (i = 0; i < nattrs; i++) 782 device_remove_file(s, &attrs[i]); 783 784 if (pmc_attrs) 785 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 786 device_remove_file(s, &pmc_attrs[i]); 787 788 #ifdef CONFIG_PPC64 789 if (cpu_has_feature(CPU_FTR_MMCRA)) 790 device_remove_file(s, &dev_attr_mmcra); 791 792 if (cpu_has_feature(CPU_FTR_PURR)) 793 device_remove_file(s, &dev_attr_purr); 794 795 if (cpu_has_feature(CPU_FTR_SPURR)) 796 device_remove_file(s, &dev_attr_spurr); 797 798 if (cpu_has_feature(CPU_FTR_DSCR)) 799 device_remove_file(s, &dev_attr_dscr); 800 801 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 802 device_remove_file(s, &dev_attr_pir); 803 #endif /* CONFIG_PPC64 */ 804 805 #ifdef CONFIG_PPC_FSL_BOOK3E 806 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 807 device_remove_file(s, &dev_attr_pw20_state); 808 device_remove_file(s, &dev_attr_pw20_wait_time); 809 810 device_remove_file(s, &dev_attr_altivec_idle); 811 device_remove_file(s, &dev_attr_altivec_idle_wait_time); 812 } 813 #endif 814 cacheinfo_cpu_offline(cpu); 815 } 816 817 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE 818 ssize_t arch_cpu_probe(const char *buf, size_t count) 819 { 820 if (ppc_md.cpu_probe) 821 return ppc_md.cpu_probe(buf, count); 822 823 return -EINVAL; 824 } 825 826 ssize_t arch_cpu_release(const char *buf, size_t count) 827 { 828 if (ppc_md.cpu_release) 829 return ppc_md.cpu_release(buf, count); 830 831 return -EINVAL; 832 } 833 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ 834 835 #endif /* CONFIG_HOTPLUG_CPU */ 836 837 static int sysfs_cpu_notify(struct notifier_block *self, 838 unsigned long action, void *hcpu) 839 { 840 unsigned int cpu = (unsigned int)(long)hcpu; 841 842 switch (action) { 843 case CPU_ONLINE: 844 case CPU_ONLINE_FROZEN: 845 register_cpu_online(cpu); 846 break; 847 #ifdef CONFIG_HOTPLUG_CPU 848 case CPU_DEAD: 849 case CPU_DEAD_FROZEN: 850 unregister_cpu_online(cpu); 851 break; 852 #endif 853 } 854 return NOTIFY_OK; 855 } 856 857 static struct notifier_block sysfs_cpu_nb = { 858 .notifier_call = sysfs_cpu_notify, 859 }; 860 861 static DEFINE_MUTEX(cpu_mutex); 862 863 int cpu_add_dev_attr(struct device_attribute *attr) 864 { 865 int cpu; 866 867 mutex_lock(&cpu_mutex); 868 869 for_each_possible_cpu(cpu) { 870 device_create_file(get_cpu_device(cpu), attr); 871 } 872 873 mutex_unlock(&cpu_mutex); 874 return 0; 875 } 876 EXPORT_SYMBOL_GPL(cpu_add_dev_attr); 877 878 int cpu_add_dev_attr_group(struct attribute_group *attrs) 879 { 880 int cpu; 881 struct device *dev; 882 int ret; 883 884 mutex_lock(&cpu_mutex); 885 886 for_each_possible_cpu(cpu) { 887 dev = get_cpu_device(cpu); 888 ret = sysfs_create_group(&dev->kobj, attrs); 889 WARN_ON(ret != 0); 890 } 891 892 mutex_unlock(&cpu_mutex); 893 return 0; 894 } 895 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group); 896 897 898 void cpu_remove_dev_attr(struct device_attribute *attr) 899 { 900 int cpu; 901 902 mutex_lock(&cpu_mutex); 903 904 for_each_possible_cpu(cpu) { 905 device_remove_file(get_cpu_device(cpu), attr); 906 } 907 908 mutex_unlock(&cpu_mutex); 909 } 910 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr); 911 912 void cpu_remove_dev_attr_group(struct attribute_group *attrs) 913 { 914 int cpu; 915 struct device *dev; 916 917 mutex_lock(&cpu_mutex); 918 919 for_each_possible_cpu(cpu) { 920 dev = get_cpu_device(cpu); 921 sysfs_remove_group(&dev->kobj, attrs); 922 } 923 924 mutex_unlock(&cpu_mutex); 925 } 926 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group); 927 928 929 /* NUMA stuff */ 930 931 #ifdef CONFIG_NUMA 932 static void register_nodes(void) 933 { 934 int i; 935 936 for (i = 0; i < MAX_NUMNODES; i++) 937 register_one_node(i); 938 } 939 940 int sysfs_add_device_to_node(struct device *dev, int nid) 941 { 942 struct node *node = node_devices[nid]; 943 return sysfs_create_link(&node->dev.kobj, &dev->kobj, 944 kobject_name(&dev->kobj)); 945 } 946 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node); 947 948 void sysfs_remove_device_from_node(struct device *dev, int nid) 949 { 950 struct node *node = node_devices[nid]; 951 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj)); 952 } 953 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node); 954 955 #else 956 static void register_nodes(void) 957 { 958 return; 959 } 960 961 #endif 962 963 /* Only valid if CPU is present. */ 964 static ssize_t show_physical_id(struct device *dev, 965 struct device_attribute *attr, char *buf) 966 { 967 struct cpu *cpu = container_of(dev, struct cpu, dev); 968 969 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id)); 970 } 971 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL); 972 973 static int __init topology_init(void) 974 { 975 int cpu; 976 977 register_nodes(); 978 979 cpu_notifier_register_begin(); 980 981 for_each_possible_cpu(cpu) { 982 struct cpu *c = &per_cpu(cpu_devices, cpu); 983 984 /* 985 * For now, we just see if the system supports making 986 * the RTAS calls for CPU hotplug. But, there may be a 987 * more comprehensive way to do this for an individual 988 * CPU. For instance, the boot cpu might never be valid 989 * for hotplugging. 990 */ 991 if (ppc_md.cpu_die) 992 c->hotpluggable = 1; 993 994 if (cpu_online(cpu) || c->hotpluggable) { 995 register_cpu(c, cpu); 996 997 device_create_file(&c->dev, &dev_attr_physical_id); 998 } 999 1000 if (cpu_online(cpu)) 1001 register_cpu_online(cpu); 1002 } 1003 1004 __register_cpu_notifier(&sysfs_cpu_nb); 1005 1006 cpu_notifier_register_done(); 1007 1008 #ifdef CONFIG_PPC64 1009 sysfs_create_dscr_default(); 1010 #endif /* CONFIG_PPC64 */ 1011 1012 return 0; 1013 } 1014 subsys_initcall(topology_init); 1015