1 #include <linux/device.h> 2 #include <linux/cpu.h> 3 #include <linux/smp.h> 4 #include <linux/percpu.h> 5 #include <linux/init.h> 6 #include <linux/sched.h> 7 #include <linux/export.h> 8 #include <linux/nodemask.h> 9 #include <linux/cpumask.h> 10 #include <linux/notifier.h> 11 12 #include <asm/current.h> 13 #include <asm/processor.h> 14 #include <asm/cputable.h> 15 #include <asm/hvcall.h> 16 #include <asm/prom.h> 17 #include <asm/machdep.h> 18 #include <asm/smp.h> 19 #include <asm/pmc.h> 20 #include <asm/firmware.h> 21 22 #include "cacheinfo.h" 23 24 #ifdef CONFIG_PPC64 25 #include <asm/paca.h> 26 #include <asm/lppaca.h> 27 #endif 28 29 static DEFINE_PER_CPU(struct cpu, cpu_devices); 30 31 /* 32 * SMT snooze delay stuff, 64-bit only for now 33 */ 34 35 #ifdef CONFIG_PPC64 36 37 /* Time in microseconds we delay before sleeping in the idle loop */ 38 static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 }; 39 40 static ssize_t store_smt_snooze_delay(struct device *dev, 41 struct device_attribute *attr, 42 const char *buf, 43 size_t count) 44 { 45 struct cpu *cpu = container_of(dev, struct cpu, dev); 46 ssize_t ret; 47 long snooze; 48 49 ret = sscanf(buf, "%ld", &snooze); 50 if (ret != 1) 51 return -EINVAL; 52 53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze; 54 return count; 55 } 56 57 static ssize_t show_smt_snooze_delay(struct device *dev, 58 struct device_attribute *attr, 59 char *buf) 60 { 61 struct cpu *cpu = container_of(dev, struct cpu, dev); 62 63 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id)); 64 } 65 66 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay, 67 store_smt_snooze_delay); 68 69 static int __init setup_smt_snooze_delay(char *str) 70 { 71 unsigned int cpu; 72 long snooze; 73 74 if (!cpu_has_feature(CPU_FTR_SMT)) 75 return 1; 76 77 snooze = simple_strtol(str, NULL, 10); 78 for_each_possible_cpu(cpu) 79 per_cpu(smt_snooze_delay, cpu) = snooze; 80 81 return 1; 82 } 83 __setup("smt-snooze-delay=", setup_smt_snooze_delay); 84 85 #endif /* CONFIG_PPC64 */ 86 87 #ifdef CONFIG_PPC_FSL_BOOK3E 88 #define MAX_BIT 63 89 90 static u64 pw20_wt; 91 static u64 altivec_idle_wt; 92 93 static unsigned int get_idle_ticks_bit(u64 ns) 94 { 95 u64 cycle; 96 97 if (ns >= 10000) 98 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec; 99 else 100 cycle = div_u64(ns * tb_ticks_per_usec, 1000); 101 102 if (!cycle) 103 return 0; 104 105 return ilog2(cycle); 106 } 107 108 static void do_show_pwrmgtcr0(void *val) 109 { 110 u32 *value = val; 111 112 *value = mfspr(SPRN_PWRMGTCR0); 113 } 114 115 static ssize_t show_pw20_state(struct device *dev, 116 struct device_attribute *attr, char *buf) 117 { 118 u32 value; 119 unsigned int cpu = dev->id; 120 121 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 122 123 value &= PWRMGTCR0_PW20_WAIT; 124 125 return sprintf(buf, "%u\n", value ? 1 : 0); 126 } 127 128 static void do_store_pw20_state(void *val) 129 { 130 u32 *value = val; 131 u32 pw20_state; 132 133 pw20_state = mfspr(SPRN_PWRMGTCR0); 134 135 if (*value) 136 pw20_state |= PWRMGTCR0_PW20_WAIT; 137 else 138 pw20_state &= ~PWRMGTCR0_PW20_WAIT; 139 140 mtspr(SPRN_PWRMGTCR0, pw20_state); 141 } 142 143 static ssize_t store_pw20_state(struct device *dev, 144 struct device_attribute *attr, 145 const char *buf, size_t count) 146 { 147 u32 value; 148 unsigned int cpu = dev->id; 149 150 if (kstrtou32(buf, 0, &value)) 151 return -EINVAL; 152 153 if (value > 1) 154 return -EINVAL; 155 156 smp_call_function_single(cpu, do_store_pw20_state, &value, 1); 157 158 return count; 159 } 160 161 static ssize_t show_pw20_wait_time(struct device *dev, 162 struct device_attribute *attr, char *buf) 163 { 164 u32 value; 165 u64 tb_cycle = 1; 166 u64 time; 167 168 unsigned int cpu = dev->id; 169 170 if (!pw20_wt) { 171 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 172 value = (value & PWRMGTCR0_PW20_ENT) >> 173 PWRMGTCR0_PW20_ENT_SHIFT; 174 175 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 176 /* convert ms to ns */ 177 if (tb_ticks_per_usec > 1000) { 178 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 179 } else { 180 u32 rem_us; 181 182 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 183 &rem_us); 184 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 185 } 186 } else { 187 time = pw20_wt; 188 } 189 190 return sprintf(buf, "%llu\n", time > 0 ? time : 0); 191 } 192 193 static void set_pw20_wait_entry_bit(void *val) 194 { 195 u32 *value = val; 196 u32 pw20_idle; 197 198 pw20_idle = mfspr(SPRN_PWRMGTCR0); 199 200 /* Set Automatic PW20 Core Idle Count */ 201 /* clear count */ 202 pw20_idle &= ~PWRMGTCR0_PW20_ENT; 203 204 /* set count */ 205 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT); 206 207 mtspr(SPRN_PWRMGTCR0, pw20_idle); 208 } 209 210 static ssize_t store_pw20_wait_time(struct device *dev, 211 struct device_attribute *attr, 212 const char *buf, size_t count) 213 { 214 u32 entry_bit; 215 u64 value; 216 217 unsigned int cpu = dev->id; 218 219 if (kstrtou64(buf, 0, &value)) 220 return -EINVAL; 221 222 if (!value) 223 return -EINVAL; 224 225 entry_bit = get_idle_ticks_bit(value); 226 if (entry_bit > MAX_BIT) 227 return -EINVAL; 228 229 pw20_wt = value; 230 231 smp_call_function_single(cpu, set_pw20_wait_entry_bit, 232 &entry_bit, 1); 233 234 return count; 235 } 236 237 static ssize_t show_altivec_idle(struct device *dev, 238 struct device_attribute *attr, char *buf) 239 { 240 u32 value; 241 unsigned int cpu = dev->id; 242 243 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 244 245 value &= PWRMGTCR0_AV_IDLE_PD_EN; 246 247 return sprintf(buf, "%u\n", value ? 1 : 0); 248 } 249 250 static void do_store_altivec_idle(void *val) 251 { 252 u32 *value = val; 253 u32 altivec_idle; 254 255 altivec_idle = mfspr(SPRN_PWRMGTCR0); 256 257 if (*value) 258 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN; 259 else 260 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN; 261 262 mtspr(SPRN_PWRMGTCR0, altivec_idle); 263 } 264 265 static ssize_t store_altivec_idle(struct device *dev, 266 struct device_attribute *attr, 267 const char *buf, size_t count) 268 { 269 u32 value; 270 unsigned int cpu = dev->id; 271 272 if (kstrtou32(buf, 0, &value)) 273 return -EINVAL; 274 275 if (value > 1) 276 return -EINVAL; 277 278 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1); 279 280 return count; 281 } 282 283 static ssize_t show_altivec_idle_wait_time(struct device *dev, 284 struct device_attribute *attr, char *buf) 285 { 286 u32 value; 287 u64 tb_cycle = 1; 288 u64 time; 289 290 unsigned int cpu = dev->id; 291 292 if (!altivec_idle_wt) { 293 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 294 value = (value & PWRMGTCR0_AV_IDLE_CNT) >> 295 PWRMGTCR0_AV_IDLE_CNT_SHIFT; 296 297 tb_cycle = (tb_cycle << (MAX_BIT - value + 1)); 298 /* convert ms to ns */ 299 if (tb_ticks_per_usec > 1000) { 300 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000); 301 } else { 302 u32 rem_us; 303 304 time = div_u64_rem(tb_cycle, tb_ticks_per_usec, 305 &rem_us); 306 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec; 307 } 308 } else { 309 time = altivec_idle_wt; 310 } 311 312 return sprintf(buf, "%llu\n", time > 0 ? time : 0); 313 } 314 315 static void set_altivec_idle_wait_entry_bit(void *val) 316 { 317 u32 *value = val; 318 u32 altivec_idle; 319 320 altivec_idle = mfspr(SPRN_PWRMGTCR0); 321 322 /* Set Automatic AltiVec Idle Count */ 323 /* clear count */ 324 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT; 325 326 /* set count */ 327 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT); 328 329 mtspr(SPRN_PWRMGTCR0, altivec_idle); 330 } 331 332 static ssize_t store_altivec_idle_wait_time(struct device *dev, 333 struct device_attribute *attr, 334 const char *buf, size_t count) 335 { 336 u32 entry_bit; 337 u64 value; 338 339 unsigned int cpu = dev->id; 340 341 if (kstrtou64(buf, 0, &value)) 342 return -EINVAL; 343 344 if (!value) 345 return -EINVAL; 346 347 entry_bit = get_idle_ticks_bit(value); 348 if (entry_bit > MAX_BIT) 349 return -EINVAL; 350 351 altivec_idle_wt = value; 352 353 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit, 354 &entry_bit, 1); 355 356 return count; 357 } 358 359 /* 360 * Enable/Disable interface: 361 * 0, disable. 1, enable. 362 */ 363 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state); 364 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle); 365 366 /* 367 * Set wait time interface:(Nanosecond) 368 * Example: Base on TBfreq is 41MHZ. 369 * 1~48(ns): TB[63] 370 * 49~97(ns): TB[62] 371 * 98~195(ns): TB[61] 372 * 196~390(ns): TB[60] 373 * 391~780(ns): TB[59] 374 * 781~1560(ns): TB[58] 375 * ... 376 */ 377 static DEVICE_ATTR(pw20_wait_time, 0600, 378 show_pw20_wait_time, 379 store_pw20_wait_time); 380 static DEVICE_ATTR(altivec_idle_wait_time, 0600, 381 show_altivec_idle_wait_time, 382 store_altivec_idle_wait_time); 383 #endif 384 385 /* 386 * Enabling PMCs will slow partition context switch times so we only do 387 * it the first time we write to the PMCs. 388 */ 389 390 static DEFINE_PER_CPU(char, pmcs_enabled); 391 392 void ppc_enable_pmcs(void) 393 { 394 ppc_set_pmu_inuse(1); 395 396 /* Only need to enable them once */ 397 if (__this_cpu_read(pmcs_enabled)) 398 return; 399 400 __this_cpu_write(pmcs_enabled, 1); 401 402 if (ppc_md.enable_pmcs) 403 ppc_md.enable_pmcs(); 404 } 405 EXPORT_SYMBOL(ppc_enable_pmcs); 406 407 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \ 408 static void read_##NAME(void *val) \ 409 { \ 410 *(unsigned long *)val = mfspr(ADDRESS); \ 411 } \ 412 static void write_##NAME(void *val) \ 413 { \ 414 EXTRA; \ 415 mtspr(ADDRESS, *(unsigned long *)val); \ 416 } 417 418 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \ 419 static ssize_t show_##NAME(struct device *dev, \ 420 struct device_attribute *attr, \ 421 char *buf) \ 422 { \ 423 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 424 unsigned long val; \ 425 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \ 426 return sprintf(buf, "%lx\n", val); \ 427 } \ 428 static ssize_t __used \ 429 store_##NAME(struct device *dev, struct device_attribute *attr, \ 430 const char *buf, size_t count) \ 431 { \ 432 struct cpu *cpu = container_of(dev, struct cpu, dev); \ 433 unsigned long val; \ 434 int ret = sscanf(buf, "%lx", &val); \ 435 if (ret != 1) \ 436 return -EINVAL; \ 437 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \ 438 return count; \ 439 } 440 441 #define SYSFS_PMCSETUP(NAME, ADDRESS) \ 442 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \ 443 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 444 #define SYSFS_SPRSETUP(NAME, ADDRESS) \ 445 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \ 446 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 447 448 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \ 449 __SYSFS_SPRSETUP_SHOW_STORE(NAME) 450 451 /* Let's define all possible registers, we'll only hook up the ones 452 * that are implemented on the current processor 453 */ 454 455 #if defined(CONFIG_PPC64) 456 #define HAS_PPC_PMC_CLASSIC 1 457 #define HAS_PPC_PMC_IBM 1 458 #define HAS_PPC_PMC_PA6T 1 459 #elif defined(CONFIG_6xx) 460 #define HAS_PPC_PMC_CLASSIC 1 461 #define HAS_PPC_PMC_IBM 1 462 #define HAS_PPC_PMC_G4 1 463 #endif 464 465 466 #ifdef HAS_PPC_PMC_CLASSIC 467 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0); 468 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1); 469 SYSFS_PMCSETUP(pmc1, SPRN_PMC1); 470 SYSFS_PMCSETUP(pmc2, SPRN_PMC2); 471 SYSFS_PMCSETUP(pmc3, SPRN_PMC3); 472 SYSFS_PMCSETUP(pmc4, SPRN_PMC4); 473 SYSFS_PMCSETUP(pmc5, SPRN_PMC5); 474 SYSFS_PMCSETUP(pmc6, SPRN_PMC6); 475 476 #ifdef HAS_PPC_PMC_G4 477 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2); 478 #endif 479 480 #ifdef CONFIG_PPC64 481 SYSFS_PMCSETUP(pmc7, SPRN_PMC7); 482 SYSFS_PMCSETUP(pmc8, SPRN_PMC8); 483 484 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA); 485 SYSFS_SPRSETUP(purr, SPRN_PURR); 486 SYSFS_SPRSETUP(spurr, SPRN_SPURR); 487 SYSFS_SPRSETUP(pir, SPRN_PIR); 488 SYSFS_SPRSETUP(tscr, SPRN_TSCR); 489 490 /* 491 Lets only enable read for phyp resources and 492 enable write when needed with a separate function. 493 Lets be conservative and default to pseries. 494 */ 495 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra); 496 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL); 497 static DEVICE_ATTR(purr, 0400, show_purr, store_purr); 498 static DEVICE_ATTR(pir, 0400, show_pir, NULL); 499 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr); 500 501 /* 502 * This is the system wide DSCR register default value. Any 503 * change to this default value through the sysfs interface 504 * will update all per cpu DSCR default values across the 505 * system stored in their respective PACA structures. 506 */ 507 static unsigned long dscr_default; 508 509 /** 510 * read_dscr() - Fetch the cpu specific DSCR default 511 * @val: Returned cpu specific DSCR default value 512 * 513 * This function returns the per cpu DSCR default value 514 * for any cpu which is contained in it's PACA structure. 515 */ 516 static void read_dscr(void *val) 517 { 518 *(unsigned long *)val = get_paca()->dscr_default; 519 } 520 521 522 /** 523 * write_dscr() - Update the cpu specific DSCR default 524 * @val: New cpu specific DSCR default value to update 525 * 526 * This function updates the per cpu DSCR default value 527 * for any cpu which is contained in it's PACA structure. 528 */ 529 static void write_dscr(void *val) 530 { 531 get_paca()->dscr_default = *(unsigned long *)val; 532 if (!current->thread.dscr_inherit) { 533 current->thread.dscr = *(unsigned long *)val; 534 mtspr(SPRN_DSCR, *(unsigned long *)val); 535 } 536 } 537 538 SYSFS_SPRSETUP_SHOW_STORE(dscr); 539 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr); 540 541 static void add_write_permission_dev_attr(struct device_attribute *attr) 542 { 543 attr->attr.mode |= 0200; 544 } 545 546 /** 547 * show_dscr_default() - Fetch the system wide DSCR default 548 * @dev: Device structure 549 * @attr: Device attribute structure 550 * @buf: Interface buffer 551 * 552 * This function returns the system wide DSCR default value. 553 */ 554 static ssize_t show_dscr_default(struct device *dev, 555 struct device_attribute *attr, char *buf) 556 { 557 return sprintf(buf, "%lx\n", dscr_default); 558 } 559 560 /** 561 * store_dscr_default() - Update the system wide DSCR default 562 * @dev: Device structure 563 * @attr: Device attribute structure 564 * @buf: Interface buffer 565 * @count: Size of the update 566 * 567 * This function updates the system wide DSCR default value. 568 */ 569 static ssize_t __used store_dscr_default(struct device *dev, 570 struct device_attribute *attr, const char *buf, 571 size_t count) 572 { 573 unsigned long val; 574 int ret = 0; 575 576 ret = sscanf(buf, "%lx", &val); 577 if (ret != 1) 578 return -EINVAL; 579 dscr_default = val; 580 581 on_each_cpu(write_dscr, &val, 1); 582 583 return count; 584 } 585 586 static DEVICE_ATTR(dscr_default, 0600, 587 show_dscr_default, store_dscr_default); 588 589 static void sysfs_create_dscr_default(void) 590 { 591 int err = 0; 592 if (cpu_has_feature(CPU_FTR_DSCR)) 593 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default); 594 } 595 596 void __init record_spr_defaults(void) 597 { 598 int cpu; 599 600 if (cpu_has_feature(CPU_FTR_DSCR)) { 601 dscr_default = mfspr(SPRN_DSCR); 602 for (cpu = 0; cpu < nr_cpu_ids; cpu++) 603 paca[cpu].dscr_default = dscr_default; 604 } 605 } 606 #endif /* CONFIG_PPC64 */ 607 608 #ifdef HAS_PPC_PMC_PA6T 609 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0); 610 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1); 611 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2); 612 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3); 613 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4); 614 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5); 615 #ifdef CONFIG_DEBUG_KERNEL 616 SYSFS_SPRSETUP(hid0, SPRN_HID0); 617 SYSFS_SPRSETUP(hid1, SPRN_HID1); 618 SYSFS_SPRSETUP(hid4, SPRN_HID4); 619 SYSFS_SPRSETUP(hid5, SPRN_HID5); 620 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0); 621 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1); 622 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2); 623 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3); 624 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4); 625 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5); 626 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6); 627 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7); 628 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8); 629 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9); 630 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT); 631 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR); 632 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR); 633 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR); 634 SYSFS_SPRSETUP(der, SPRN_PA6T_DER); 635 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER); 636 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER); 637 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER); 638 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER); 639 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR); 640 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0); 641 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1); 642 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2); 643 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3); 644 #endif /* CONFIG_DEBUG_KERNEL */ 645 #endif /* HAS_PPC_PMC_PA6T */ 646 647 #ifdef HAS_PPC_PMC_IBM 648 static struct device_attribute ibm_common_attrs[] = { 649 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 650 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 651 }; 652 #endif /* HAS_PPC_PMC_G4 */ 653 654 #ifdef HAS_PPC_PMC_G4 655 static struct device_attribute g4_common_attrs[] = { 656 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 657 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 658 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2), 659 }; 660 #endif /* HAS_PPC_PMC_G4 */ 661 662 static struct device_attribute classic_pmc_attrs[] = { 663 __ATTR(pmc1, 0600, show_pmc1, store_pmc1), 664 __ATTR(pmc2, 0600, show_pmc2, store_pmc2), 665 __ATTR(pmc3, 0600, show_pmc3, store_pmc3), 666 __ATTR(pmc4, 0600, show_pmc4, store_pmc4), 667 __ATTR(pmc5, 0600, show_pmc5, store_pmc5), 668 __ATTR(pmc6, 0600, show_pmc6, store_pmc6), 669 #ifdef CONFIG_PPC64 670 __ATTR(pmc7, 0600, show_pmc7, store_pmc7), 671 __ATTR(pmc8, 0600, show_pmc8, store_pmc8), 672 #endif 673 }; 674 675 #ifdef HAS_PPC_PMC_PA6T 676 static struct device_attribute pa6t_attrs[] = { 677 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0), 678 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1), 679 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0), 680 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1), 681 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2), 682 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3), 683 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4), 684 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5), 685 #ifdef CONFIG_DEBUG_KERNEL 686 __ATTR(hid0, 0600, show_hid0, store_hid0), 687 __ATTR(hid1, 0600, show_hid1, store_hid1), 688 __ATTR(hid4, 0600, show_hid4, store_hid4), 689 __ATTR(hid5, 0600, show_hid5, store_hid5), 690 __ATTR(ima0, 0600, show_ima0, store_ima0), 691 __ATTR(ima1, 0600, show_ima1, store_ima1), 692 __ATTR(ima2, 0600, show_ima2, store_ima2), 693 __ATTR(ima3, 0600, show_ima3, store_ima3), 694 __ATTR(ima4, 0600, show_ima4, store_ima4), 695 __ATTR(ima5, 0600, show_ima5, store_ima5), 696 __ATTR(ima6, 0600, show_ima6, store_ima6), 697 __ATTR(ima7, 0600, show_ima7, store_ima7), 698 __ATTR(ima8, 0600, show_ima8, store_ima8), 699 __ATTR(ima9, 0600, show_ima9, store_ima9), 700 __ATTR(imaat, 0600, show_imaat, store_imaat), 701 __ATTR(btcr, 0600, show_btcr, store_btcr), 702 __ATTR(pccr, 0600, show_pccr, store_pccr), 703 __ATTR(rpccr, 0600, show_rpccr, store_rpccr), 704 __ATTR(der, 0600, show_der, store_der), 705 __ATTR(mer, 0600, show_mer, store_mer), 706 __ATTR(ber, 0600, show_ber, store_ber), 707 __ATTR(ier, 0600, show_ier, store_ier), 708 __ATTR(sier, 0600, show_sier, store_sier), 709 __ATTR(siar, 0600, show_siar, store_siar), 710 __ATTR(tsr0, 0600, show_tsr0, store_tsr0), 711 __ATTR(tsr1, 0600, show_tsr1, store_tsr1), 712 __ATTR(tsr2, 0600, show_tsr2, store_tsr2), 713 __ATTR(tsr3, 0600, show_tsr3, store_tsr3), 714 #endif /* CONFIG_DEBUG_KERNEL */ 715 }; 716 #endif /* HAS_PPC_PMC_PA6T */ 717 #endif /* HAS_PPC_PMC_CLASSIC */ 718 719 static int register_cpu_online(unsigned int cpu) 720 { 721 struct cpu *c = &per_cpu(cpu_devices, cpu); 722 struct device *s = &c->dev; 723 struct device_attribute *attrs, *pmc_attrs; 724 int i, nattrs; 725 726 /* For cpus present at boot a reference was already grabbed in register_cpu() */ 727 if (!s->of_node) 728 s->of_node = of_get_cpu_node(cpu, NULL); 729 730 #ifdef CONFIG_PPC64 731 if (cpu_has_feature(CPU_FTR_SMT)) 732 device_create_file(s, &dev_attr_smt_snooze_delay); 733 #endif 734 735 /* PMC stuff */ 736 switch (cur_cpu_spec->pmc_type) { 737 #ifdef HAS_PPC_PMC_IBM 738 case PPC_PMC_IBM: 739 attrs = ibm_common_attrs; 740 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); 741 pmc_attrs = classic_pmc_attrs; 742 break; 743 #endif /* HAS_PPC_PMC_IBM */ 744 #ifdef HAS_PPC_PMC_G4 745 case PPC_PMC_G4: 746 attrs = g4_common_attrs; 747 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); 748 pmc_attrs = classic_pmc_attrs; 749 break; 750 #endif /* HAS_PPC_PMC_G4 */ 751 #ifdef HAS_PPC_PMC_PA6T 752 case PPC_PMC_PA6T: 753 /* PA Semi starts counting at PMC0 */ 754 attrs = pa6t_attrs; 755 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); 756 pmc_attrs = NULL; 757 break; 758 #endif /* HAS_PPC_PMC_PA6T */ 759 default: 760 attrs = NULL; 761 nattrs = 0; 762 pmc_attrs = NULL; 763 } 764 765 for (i = 0; i < nattrs; i++) 766 device_create_file(s, &attrs[i]); 767 768 if (pmc_attrs) 769 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 770 device_create_file(s, &pmc_attrs[i]); 771 772 #ifdef CONFIG_PPC64 773 if (cpu_has_feature(CPU_FTR_MMCRA)) 774 device_create_file(s, &dev_attr_mmcra); 775 776 if (cpu_has_feature(CPU_FTR_PURR)) { 777 if (!firmware_has_feature(FW_FEATURE_LPAR)) 778 add_write_permission_dev_attr(&dev_attr_purr); 779 device_create_file(s, &dev_attr_purr); 780 } 781 782 if (cpu_has_feature(CPU_FTR_SPURR)) 783 device_create_file(s, &dev_attr_spurr); 784 785 if (cpu_has_feature(CPU_FTR_DSCR)) 786 device_create_file(s, &dev_attr_dscr); 787 788 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 789 device_create_file(s, &dev_attr_pir); 790 791 if (cpu_has_feature(CPU_FTR_ARCH_206)) 792 device_create_file(s, &dev_attr_tscr); 793 #endif /* CONFIG_PPC64 */ 794 795 #ifdef CONFIG_PPC_FSL_BOOK3E 796 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 797 device_create_file(s, &dev_attr_pw20_state); 798 device_create_file(s, &dev_attr_pw20_wait_time); 799 800 device_create_file(s, &dev_attr_altivec_idle); 801 device_create_file(s, &dev_attr_altivec_idle_wait_time); 802 } 803 #endif 804 cacheinfo_cpu_online(cpu); 805 return 0; 806 } 807 808 #ifdef CONFIG_HOTPLUG_CPU 809 static int unregister_cpu_online(unsigned int cpu) 810 { 811 struct cpu *c = &per_cpu(cpu_devices, cpu); 812 struct device *s = &c->dev; 813 struct device_attribute *attrs, *pmc_attrs; 814 int i, nattrs; 815 816 BUG_ON(!c->hotpluggable); 817 818 #ifdef CONFIG_PPC64 819 if (cpu_has_feature(CPU_FTR_SMT)) 820 device_remove_file(s, &dev_attr_smt_snooze_delay); 821 #endif 822 823 /* PMC stuff */ 824 switch (cur_cpu_spec->pmc_type) { 825 #ifdef HAS_PPC_PMC_IBM 826 case PPC_PMC_IBM: 827 attrs = ibm_common_attrs; 828 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); 829 pmc_attrs = classic_pmc_attrs; 830 break; 831 #endif /* HAS_PPC_PMC_IBM */ 832 #ifdef HAS_PPC_PMC_G4 833 case PPC_PMC_G4: 834 attrs = g4_common_attrs; 835 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); 836 pmc_attrs = classic_pmc_attrs; 837 break; 838 #endif /* HAS_PPC_PMC_G4 */ 839 #ifdef HAS_PPC_PMC_PA6T 840 case PPC_PMC_PA6T: 841 /* PA Semi starts counting at PMC0 */ 842 attrs = pa6t_attrs; 843 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); 844 pmc_attrs = NULL; 845 break; 846 #endif /* HAS_PPC_PMC_PA6T */ 847 default: 848 attrs = NULL; 849 nattrs = 0; 850 pmc_attrs = NULL; 851 } 852 853 for (i = 0; i < nattrs; i++) 854 device_remove_file(s, &attrs[i]); 855 856 if (pmc_attrs) 857 for (i = 0; i < cur_cpu_spec->num_pmcs; i++) 858 device_remove_file(s, &pmc_attrs[i]); 859 860 #ifdef CONFIG_PPC64 861 if (cpu_has_feature(CPU_FTR_MMCRA)) 862 device_remove_file(s, &dev_attr_mmcra); 863 864 if (cpu_has_feature(CPU_FTR_PURR)) 865 device_remove_file(s, &dev_attr_purr); 866 867 if (cpu_has_feature(CPU_FTR_SPURR)) 868 device_remove_file(s, &dev_attr_spurr); 869 870 if (cpu_has_feature(CPU_FTR_DSCR)) 871 device_remove_file(s, &dev_attr_dscr); 872 873 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2)) 874 device_remove_file(s, &dev_attr_pir); 875 876 if (cpu_has_feature(CPU_FTR_ARCH_206)) 877 device_remove_file(s, &dev_attr_tscr); 878 #endif /* CONFIG_PPC64 */ 879 880 #ifdef CONFIG_PPC_FSL_BOOK3E 881 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 882 device_remove_file(s, &dev_attr_pw20_state); 883 device_remove_file(s, &dev_attr_pw20_wait_time); 884 885 device_remove_file(s, &dev_attr_altivec_idle); 886 device_remove_file(s, &dev_attr_altivec_idle_wait_time); 887 } 888 #endif 889 cacheinfo_cpu_offline(cpu); 890 of_node_put(s->of_node); 891 s->of_node = NULL; 892 return 0; 893 } 894 #else /* !CONFIG_HOTPLUG_CPU */ 895 #define unregister_cpu_online NULL 896 #endif 897 898 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE 899 ssize_t arch_cpu_probe(const char *buf, size_t count) 900 { 901 if (ppc_md.cpu_probe) 902 return ppc_md.cpu_probe(buf, count); 903 904 return -EINVAL; 905 } 906 907 ssize_t arch_cpu_release(const char *buf, size_t count) 908 { 909 if (ppc_md.cpu_release) 910 return ppc_md.cpu_release(buf, count); 911 912 return -EINVAL; 913 } 914 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ 915 916 static DEFINE_MUTEX(cpu_mutex); 917 918 int cpu_add_dev_attr(struct device_attribute *attr) 919 { 920 int cpu; 921 922 mutex_lock(&cpu_mutex); 923 924 for_each_possible_cpu(cpu) { 925 device_create_file(get_cpu_device(cpu), attr); 926 } 927 928 mutex_unlock(&cpu_mutex); 929 return 0; 930 } 931 EXPORT_SYMBOL_GPL(cpu_add_dev_attr); 932 933 int cpu_add_dev_attr_group(struct attribute_group *attrs) 934 { 935 int cpu; 936 struct device *dev; 937 int ret; 938 939 mutex_lock(&cpu_mutex); 940 941 for_each_possible_cpu(cpu) { 942 dev = get_cpu_device(cpu); 943 ret = sysfs_create_group(&dev->kobj, attrs); 944 WARN_ON(ret != 0); 945 } 946 947 mutex_unlock(&cpu_mutex); 948 return 0; 949 } 950 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group); 951 952 953 void cpu_remove_dev_attr(struct device_attribute *attr) 954 { 955 int cpu; 956 957 mutex_lock(&cpu_mutex); 958 959 for_each_possible_cpu(cpu) { 960 device_remove_file(get_cpu_device(cpu), attr); 961 } 962 963 mutex_unlock(&cpu_mutex); 964 } 965 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr); 966 967 void cpu_remove_dev_attr_group(struct attribute_group *attrs) 968 { 969 int cpu; 970 struct device *dev; 971 972 mutex_lock(&cpu_mutex); 973 974 for_each_possible_cpu(cpu) { 975 dev = get_cpu_device(cpu); 976 sysfs_remove_group(&dev->kobj, attrs); 977 } 978 979 mutex_unlock(&cpu_mutex); 980 } 981 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group); 982 983 984 /* NUMA stuff */ 985 986 #ifdef CONFIG_NUMA 987 static void register_nodes(void) 988 { 989 int i; 990 991 for (i = 0; i < MAX_NUMNODES; i++) 992 register_one_node(i); 993 } 994 995 int sysfs_add_device_to_node(struct device *dev, int nid) 996 { 997 struct node *node = node_devices[nid]; 998 return sysfs_create_link(&node->dev.kobj, &dev->kobj, 999 kobject_name(&dev->kobj)); 1000 } 1001 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node); 1002 1003 void sysfs_remove_device_from_node(struct device *dev, int nid) 1004 { 1005 struct node *node = node_devices[nid]; 1006 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj)); 1007 } 1008 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node); 1009 1010 #else 1011 static void register_nodes(void) 1012 { 1013 return; 1014 } 1015 1016 #endif 1017 1018 /* Only valid if CPU is present. */ 1019 static ssize_t show_physical_id(struct device *dev, 1020 struct device_attribute *attr, char *buf) 1021 { 1022 struct cpu *cpu = container_of(dev, struct cpu, dev); 1023 1024 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id)); 1025 } 1026 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL); 1027 1028 static int __init topology_init(void) 1029 { 1030 int cpu, r; 1031 1032 register_nodes(); 1033 1034 for_each_possible_cpu(cpu) { 1035 struct cpu *c = &per_cpu(cpu_devices, cpu); 1036 1037 /* 1038 * For now, we just see if the system supports making 1039 * the RTAS calls for CPU hotplug. But, there may be a 1040 * more comprehensive way to do this for an individual 1041 * CPU. For instance, the boot cpu might never be valid 1042 * for hotplugging. 1043 */ 1044 if (ppc_md.cpu_die) 1045 c->hotpluggable = 1; 1046 1047 if (cpu_online(cpu) || c->hotpluggable) { 1048 register_cpu(c, cpu); 1049 1050 device_create_file(&c->dev, &dev_attr_physical_id); 1051 } 1052 } 1053 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online", 1054 register_cpu_online, unregister_cpu_online); 1055 WARN_ON(r < 0); 1056 #ifdef CONFIG_PPC64 1057 sysfs_create_dscr_default(); 1058 #endif /* CONFIG_PPC64 */ 1059 1060 return 0; 1061 } 1062 subsys_initcall(topology_init); 1063