1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * SMP support for ppc. 4 * 5 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great 6 * deal of code from the sparc and intel versions. 7 * 8 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> 9 * 10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and 11 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com 12 */ 13 14 #undef DEBUG 15 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task_stack.h> 20 #include <linux/sched/topology.h> 21 #include <linux/smp.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/init.h> 25 #include <linux/spinlock.h> 26 #include <linux/cache.h> 27 #include <linux/err.h> 28 #include <linux/device.h> 29 #include <linux/cpu.h> 30 #include <linux/notifier.h> 31 #include <linux/topology.h> 32 #include <linux/profile.h> 33 #include <linux/processor.h> 34 #include <linux/random.h> 35 #include <linux/stackprotector.h> 36 #include <linux/pgtable.h> 37 38 #include <asm/ptrace.h> 39 #include <linux/atomic.h> 40 #include <asm/irq.h> 41 #include <asm/hw_irq.h> 42 #include <asm/kvm_ppc.h> 43 #include <asm/dbell.h> 44 #include <asm/page.h> 45 #include <asm/prom.h> 46 #include <asm/smp.h> 47 #include <asm/time.h> 48 #include <asm/machdep.h> 49 #include <asm/cputhreads.h> 50 #include <asm/cputable.h> 51 #include <asm/mpic.h> 52 #include <asm/vdso_datapage.h> 53 #ifdef CONFIG_PPC64 54 #include <asm/paca.h> 55 #endif 56 #include <asm/vdso.h> 57 #include <asm/debug.h> 58 #include <asm/kexec.h> 59 #include <asm/asm-prototypes.h> 60 #include <asm/cpu_has_feature.h> 61 #include <asm/ftrace.h> 62 #include <asm/kup.h> 63 64 #ifdef DEBUG 65 #include <asm/udbg.h> 66 #define DBG(fmt...) udbg_printf(fmt) 67 #else 68 #define DBG(fmt...) 69 #endif 70 71 #ifdef CONFIG_HOTPLUG_CPU 72 /* State of each CPU during hotplug phases */ 73 static DEFINE_PER_CPU(int, cpu_state) = { 0 }; 74 #endif 75 76 struct task_struct *secondary_current; 77 bool has_big_cores; 78 bool coregroup_enabled; 79 80 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 81 DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map); 82 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map); 83 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 84 DEFINE_PER_CPU(cpumask_var_t, cpu_coregroup_map); 85 86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 87 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 89 EXPORT_SYMBOL_GPL(has_big_cores); 90 91 enum { 92 #ifdef CONFIG_SCHED_SMT 93 smt_idx, 94 #endif 95 cache_idx, 96 mc_idx, 97 die_idx, 98 }; 99 100 #define MAX_THREAD_LIST_SIZE 8 101 #define THREAD_GROUP_SHARE_L1 1 102 struct thread_groups { 103 unsigned int property; 104 unsigned int nr_groups; 105 unsigned int threads_per_group; 106 unsigned int thread_list[MAX_THREAD_LIST_SIZE]; 107 }; 108 109 /* 110 * On big-cores system, cpu_l1_cache_map for each CPU corresponds to 111 * the set its siblings that share the L1-cache. 112 */ 113 DEFINE_PER_CPU(cpumask_var_t, cpu_l1_cache_map); 114 115 /* SMP operations for this machine */ 116 struct smp_ops_t *smp_ops; 117 118 /* Can't be static due to PowerMac hackery */ 119 volatile unsigned int cpu_callin_map[NR_CPUS]; 120 121 int smt_enabled_at_boot = 1; 122 123 /* 124 * Returns 1 if the specified cpu should be brought up during boot. 125 * Used to inhibit booting threads if they've been disabled or 126 * limited on the command line 127 */ 128 int smp_generic_cpu_bootable(unsigned int nr) 129 { 130 /* Special case - we inhibit secondary thread startup 131 * during boot if the user requests it. 132 */ 133 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) { 134 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) 135 return 0; 136 if (smt_enabled_at_boot 137 && cpu_thread_in_core(nr) >= smt_enabled_at_boot) 138 return 0; 139 } 140 141 return 1; 142 } 143 144 145 #ifdef CONFIG_PPC64 146 int smp_generic_kick_cpu(int nr) 147 { 148 if (nr < 0 || nr >= nr_cpu_ids) 149 return -EINVAL; 150 151 /* 152 * The processor is currently spinning, waiting for the 153 * cpu_start field to become non-zero After we set cpu_start, 154 * the processor will continue on to secondary_start 155 */ 156 if (!paca_ptrs[nr]->cpu_start) { 157 paca_ptrs[nr]->cpu_start = 1; 158 smp_mb(); 159 return 0; 160 } 161 162 #ifdef CONFIG_HOTPLUG_CPU 163 /* 164 * Ok it's not there, so it might be soft-unplugged, let's 165 * try to bring it back 166 */ 167 generic_set_cpu_up(nr); 168 smp_wmb(); 169 smp_send_reschedule(nr); 170 #endif /* CONFIG_HOTPLUG_CPU */ 171 172 return 0; 173 } 174 #endif /* CONFIG_PPC64 */ 175 176 static irqreturn_t call_function_action(int irq, void *data) 177 { 178 generic_smp_call_function_interrupt(); 179 return IRQ_HANDLED; 180 } 181 182 static irqreturn_t reschedule_action(int irq, void *data) 183 { 184 scheduler_ipi(); 185 return IRQ_HANDLED; 186 } 187 188 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 189 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) 190 { 191 timer_broadcast_interrupt(); 192 return IRQ_HANDLED; 193 } 194 #endif 195 196 #ifdef CONFIG_NMI_IPI 197 static irqreturn_t nmi_ipi_action(int irq, void *data) 198 { 199 smp_handle_nmi_ipi(get_irq_regs()); 200 return IRQ_HANDLED; 201 } 202 #endif 203 204 static irq_handler_t smp_ipi_action[] = { 205 [PPC_MSG_CALL_FUNCTION] = call_function_action, 206 [PPC_MSG_RESCHEDULE] = reschedule_action, 207 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 208 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, 209 #endif 210 #ifdef CONFIG_NMI_IPI 211 [PPC_MSG_NMI_IPI] = nmi_ipi_action, 212 #endif 213 }; 214 215 /* 216 * The NMI IPI is a fallback and not truly non-maskable. It is simpler 217 * than going through the call function infrastructure, and strongly 218 * serialized, so it is more appropriate for debugging. 219 */ 220 const char *smp_ipi_name[] = { 221 [PPC_MSG_CALL_FUNCTION] = "ipi call function", 222 [PPC_MSG_RESCHEDULE] = "ipi reschedule", 223 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 224 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", 225 #endif 226 #ifdef CONFIG_NMI_IPI 227 [PPC_MSG_NMI_IPI] = "nmi ipi", 228 #endif 229 }; 230 231 /* optional function to request ipi, for controllers with >= 4 ipis */ 232 int smp_request_message_ipi(int virq, int msg) 233 { 234 int err; 235 236 if (msg < 0 || msg > PPC_MSG_NMI_IPI) 237 return -EINVAL; 238 #ifndef CONFIG_NMI_IPI 239 if (msg == PPC_MSG_NMI_IPI) 240 return 1; 241 #endif 242 243 err = request_irq(virq, smp_ipi_action[msg], 244 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, 245 smp_ipi_name[msg], NULL); 246 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", 247 virq, smp_ipi_name[msg], err); 248 249 return err; 250 } 251 252 #ifdef CONFIG_PPC_SMP_MUXED_IPI 253 struct cpu_messages { 254 long messages; /* current messages */ 255 }; 256 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); 257 258 void smp_muxed_ipi_set_message(int cpu, int msg) 259 { 260 struct cpu_messages *info = &per_cpu(ipi_message, cpu); 261 char *message = (char *)&info->messages; 262 263 /* 264 * Order previous accesses before accesses in the IPI handler. 265 */ 266 smp_mb(); 267 message[msg] = 1; 268 } 269 270 void smp_muxed_ipi_message_pass(int cpu, int msg) 271 { 272 smp_muxed_ipi_set_message(cpu, msg); 273 274 /* 275 * cause_ipi functions are required to include a full barrier 276 * before doing whatever causes the IPI. 277 */ 278 smp_ops->cause_ipi(cpu); 279 } 280 281 #ifdef __BIG_ENDIAN__ 282 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) 283 #else 284 #define IPI_MESSAGE(A) (1uL << (8 * (A))) 285 #endif 286 287 irqreturn_t smp_ipi_demux(void) 288 { 289 mb(); /* order any irq clear */ 290 291 return smp_ipi_demux_relaxed(); 292 } 293 294 /* sync-free variant. Callers should ensure synchronization */ 295 irqreturn_t smp_ipi_demux_relaxed(void) 296 { 297 struct cpu_messages *info; 298 unsigned long all; 299 300 info = this_cpu_ptr(&ipi_message); 301 do { 302 all = xchg(&info->messages, 0); 303 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) 304 /* 305 * Must check for PPC_MSG_RM_HOST_ACTION messages 306 * before PPC_MSG_CALL_FUNCTION messages because when 307 * a VM is destroyed, we call kick_all_cpus_sync() 308 * to ensure that any pending PPC_MSG_RM_HOST_ACTION 309 * messages have completed before we free any VCPUs. 310 */ 311 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION)) 312 kvmppc_xics_ipi_action(); 313 #endif 314 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) 315 generic_smp_call_function_interrupt(); 316 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) 317 scheduler_ipi(); 318 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 319 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) 320 timer_broadcast_interrupt(); 321 #endif 322 #ifdef CONFIG_NMI_IPI 323 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI)) 324 nmi_ipi_action(0, NULL); 325 #endif 326 } while (info->messages); 327 328 return IRQ_HANDLED; 329 } 330 #endif /* CONFIG_PPC_SMP_MUXED_IPI */ 331 332 static inline void do_message_pass(int cpu, int msg) 333 { 334 if (smp_ops->message_pass) 335 smp_ops->message_pass(cpu, msg); 336 #ifdef CONFIG_PPC_SMP_MUXED_IPI 337 else 338 smp_muxed_ipi_message_pass(cpu, msg); 339 #endif 340 } 341 342 void smp_send_reschedule(int cpu) 343 { 344 if (likely(smp_ops)) 345 do_message_pass(cpu, PPC_MSG_RESCHEDULE); 346 } 347 EXPORT_SYMBOL_GPL(smp_send_reschedule); 348 349 void arch_send_call_function_single_ipi(int cpu) 350 { 351 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); 352 } 353 354 void arch_send_call_function_ipi_mask(const struct cpumask *mask) 355 { 356 unsigned int cpu; 357 358 for_each_cpu(cpu, mask) 359 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); 360 } 361 362 #ifdef CONFIG_NMI_IPI 363 364 /* 365 * "NMI IPI" system. 366 * 367 * NMI IPIs may not be recoverable, so should not be used as ongoing part of 368 * a running system. They can be used for crash, debug, halt/reboot, etc. 369 * 370 * The IPI call waits with interrupts disabled until all targets enter the 371 * NMI handler, then returns. Subsequent IPIs can be issued before targets 372 * have returned from their handlers, so there is no guarantee about 373 * concurrency or re-entrancy. 374 * 375 * A new NMI can be issued before all targets exit the handler. 376 * 377 * The IPI call may time out without all targets entering the NMI handler. 378 * In that case, there is some logic to recover (and ignore subsequent 379 * NMI interrupts that may eventually be raised), but the platform interrupt 380 * handler may not be able to distinguish this from other exception causes, 381 * which may cause a crash. 382 */ 383 384 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0); 385 static struct cpumask nmi_ipi_pending_mask; 386 static bool nmi_ipi_busy = false; 387 static void (*nmi_ipi_function)(struct pt_regs *) = NULL; 388 389 static void nmi_ipi_lock_start(unsigned long *flags) 390 { 391 raw_local_irq_save(*flags); 392 hard_irq_disable(); 393 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) { 394 raw_local_irq_restore(*flags); 395 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); 396 raw_local_irq_save(*flags); 397 hard_irq_disable(); 398 } 399 } 400 401 static void nmi_ipi_lock(void) 402 { 403 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) 404 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); 405 } 406 407 static void nmi_ipi_unlock(void) 408 { 409 smp_mb(); 410 WARN_ON(atomic_read(&__nmi_ipi_lock) != 1); 411 atomic_set(&__nmi_ipi_lock, 0); 412 } 413 414 static void nmi_ipi_unlock_end(unsigned long *flags) 415 { 416 nmi_ipi_unlock(); 417 raw_local_irq_restore(*flags); 418 } 419 420 /* 421 * Platform NMI handler calls this to ack 422 */ 423 int smp_handle_nmi_ipi(struct pt_regs *regs) 424 { 425 void (*fn)(struct pt_regs *) = NULL; 426 unsigned long flags; 427 int me = raw_smp_processor_id(); 428 int ret = 0; 429 430 /* 431 * Unexpected NMIs are possible here because the interrupt may not 432 * be able to distinguish NMI IPIs from other types of NMIs, or 433 * because the caller may have timed out. 434 */ 435 nmi_ipi_lock_start(&flags); 436 if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) { 437 cpumask_clear_cpu(me, &nmi_ipi_pending_mask); 438 fn = READ_ONCE(nmi_ipi_function); 439 WARN_ON_ONCE(!fn); 440 ret = 1; 441 } 442 nmi_ipi_unlock_end(&flags); 443 444 if (fn) 445 fn(regs); 446 447 return ret; 448 } 449 450 static void do_smp_send_nmi_ipi(int cpu, bool safe) 451 { 452 if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu)) 453 return; 454 455 if (cpu >= 0) { 456 do_message_pass(cpu, PPC_MSG_NMI_IPI); 457 } else { 458 int c; 459 460 for_each_online_cpu(c) { 461 if (c == raw_smp_processor_id()) 462 continue; 463 do_message_pass(c, PPC_MSG_NMI_IPI); 464 } 465 } 466 } 467 468 /* 469 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS. 470 * - fn is the target callback function. 471 * - delay_us > 0 is the delay before giving up waiting for targets to 472 * begin executing the handler, == 0 specifies indefinite delay. 473 */ 474 static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), 475 u64 delay_us, bool safe) 476 { 477 unsigned long flags; 478 int me = raw_smp_processor_id(); 479 int ret = 1; 480 481 BUG_ON(cpu == me); 482 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS); 483 484 if (unlikely(!smp_ops)) 485 return 0; 486 487 nmi_ipi_lock_start(&flags); 488 while (nmi_ipi_busy) { 489 nmi_ipi_unlock_end(&flags); 490 spin_until_cond(!nmi_ipi_busy); 491 nmi_ipi_lock_start(&flags); 492 } 493 nmi_ipi_busy = true; 494 nmi_ipi_function = fn; 495 496 WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask)); 497 498 if (cpu < 0) { 499 /* ALL_OTHERS */ 500 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask); 501 cpumask_clear_cpu(me, &nmi_ipi_pending_mask); 502 } else { 503 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask); 504 } 505 506 nmi_ipi_unlock(); 507 508 /* Interrupts remain hard disabled */ 509 510 do_smp_send_nmi_ipi(cpu, safe); 511 512 nmi_ipi_lock(); 513 /* nmi_ipi_busy is set here, so unlock/lock is okay */ 514 while (!cpumask_empty(&nmi_ipi_pending_mask)) { 515 nmi_ipi_unlock(); 516 udelay(1); 517 nmi_ipi_lock(); 518 if (delay_us) { 519 delay_us--; 520 if (!delay_us) 521 break; 522 } 523 } 524 525 if (!cpumask_empty(&nmi_ipi_pending_mask)) { 526 /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */ 527 ret = 0; 528 cpumask_clear(&nmi_ipi_pending_mask); 529 } 530 531 nmi_ipi_function = NULL; 532 nmi_ipi_busy = false; 533 534 nmi_ipi_unlock_end(&flags); 535 536 return ret; 537 } 538 539 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) 540 { 541 return __smp_send_nmi_ipi(cpu, fn, delay_us, false); 542 } 543 544 int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) 545 { 546 return __smp_send_nmi_ipi(cpu, fn, delay_us, true); 547 } 548 #endif /* CONFIG_NMI_IPI */ 549 550 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 551 void tick_broadcast(const struct cpumask *mask) 552 { 553 unsigned int cpu; 554 555 for_each_cpu(cpu, mask) 556 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); 557 } 558 #endif 559 560 #ifdef CONFIG_DEBUGGER 561 void debugger_ipi_callback(struct pt_regs *regs) 562 { 563 debugger_ipi(regs); 564 } 565 566 void smp_send_debugger_break(void) 567 { 568 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000); 569 } 570 #endif 571 572 #ifdef CONFIG_KEXEC_CORE 573 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) 574 { 575 int cpu; 576 577 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000); 578 if (kdump_in_progress() && crash_wake_offline) { 579 for_each_present_cpu(cpu) { 580 if (cpu_online(cpu)) 581 continue; 582 /* 583 * crash_ipi_callback will wait for 584 * all cpus, including offline CPUs. 585 * We don't care about nmi_ipi_function. 586 * Offline cpus will jump straight into 587 * crash_ipi_callback, we can skip the 588 * entire NMI dance and waiting for 589 * cpus to clear pending mask, etc. 590 */ 591 do_smp_send_nmi_ipi(cpu, false); 592 } 593 } 594 } 595 #endif 596 597 #ifdef CONFIG_NMI_IPI 598 static void nmi_stop_this_cpu(struct pt_regs *regs) 599 { 600 /* 601 * IRQs are already hard disabled by the smp_handle_nmi_ipi. 602 */ 603 spin_begin(); 604 while (1) 605 spin_cpu_relax(); 606 } 607 608 void smp_send_stop(void) 609 { 610 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000); 611 } 612 613 #else /* CONFIG_NMI_IPI */ 614 615 static void stop_this_cpu(void *dummy) 616 { 617 hard_irq_disable(); 618 spin_begin(); 619 while (1) 620 spin_cpu_relax(); 621 } 622 623 void smp_send_stop(void) 624 { 625 static bool stopped = false; 626 627 /* 628 * Prevent waiting on csd lock from a previous smp_send_stop. 629 * This is racy, but in general callers try to do the right 630 * thing and only fire off one smp_send_stop (e.g., see 631 * kernel/panic.c) 632 */ 633 if (stopped) 634 return; 635 636 stopped = true; 637 638 smp_call_function(stop_this_cpu, NULL, 0); 639 } 640 #endif /* CONFIG_NMI_IPI */ 641 642 struct task_struct *current_set[NR_CPUS]; 643 644 static void smp_store_cpu_info(int id) 645 { 646 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); 647 #ifdef CONFIG_PPC_FSL_BOOK3E 648 per_cpu(next_tlbcam_idx, id) 649 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; 650 #endif 651 } 652 653 /* 654 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so 655 * rather than just passing around the cpumask we pass around a function that 656 * returns the that cpumask for the given CPU. 657 */ 658 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int)) 659 { 660 cpumask_set_cpu(i, get_cpumask(j)); 661 cpumask_set_cpu(j, get_cpumask(i)); 662 } 663 664 #ifdef CONFIG_HOTPLUG_CPU 665 static void set_cpus_unrelated(int i, int j, 666 struct cpumask *(*get_cpumask)(int)) 667 { 668 cpumask_clear_cpu(i, get_cpumask(j)); 669 cpumask_clear_cpu(j, get_cpumask(i)); 670 } 671 #endif 672 673 /* 674 * Extends set_cpus_related. Instead of setting one CPU at a time in 675 * dstmask, set srcmask at oneshot. dstmask should be super set of srcmask. 676 */ 677 static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int), 678 struct cpumask *(*dstmask)(int)) 679 { 680 struct cpumask *mask; 681 int k; 682 683 mask = srcmask(j); 684 for_each_cpu(k, srcmask(i)) 685 cpumask_or(dstmask(k), dstmask(k), mask); 686 687 if (i == j) 688 return; 689 690 mask = srcmask(i); 691 for_each_cpu(k, srcmask(j)) 692 cpumask_or(dstmask(k), dstmask(k), mask); 693 } 694 695 /* 696 * parse_thread_groups: Parses the "ibm,thread-groups" device tree 697 * property for the CPU device node @dn and stores 698 * the parsed output in the thread_groups 699 * structure @tg if the ibm,thread-groups[0] 700 * matches @property. 701 * 702 * @dn: The device node of the CPU device. 703 * @tg: Pointer to a thread group structure into which the parsed 704 * output of "ibm,thread-groups" is stored. 705 * @property: The property of the thread-group that the caller is 706 * interested in. 707 * 708 * ibm,thread-groups[0..N-1] array defines which group of threads in 709 * the CPU-device node can be grouped together based on the property. 710 * 711 * ibm,thread-groups[0] tells us the property based on which the 712 * threads are being grouped together. If this value is 1, it implies 713 * that the threads in the same group share L1, translation cache. 714 * 715 * ibm,thread-groups[1] tells us how many such thread groups exist. 716 * 717 * ibm,thread-groups[2] tells us the number of threads in each such 718 * group. 719 * 720 * ibm,thread-groups[3..N-1] is the list of threads identified by 721 * "ibm,ppc-interrupt-server#s" arranged as per their membership in 722 * the grouping. 723 * 724 * Example: If ibm,thread-groups = [1,2,4,5,6,7,8,9,10,11,12] it 725 * implies that there are 2 groups of 4 threads each, where each group 726 * of threads share L1, translation cache. 727 * 728 * The "ibm,ppc-interrupt-server#s" of the first group is {5,6,7,8} 729 * and the "ibm,ppc-interrupt-server#s" of the second group is {9, 10, 730 * 11, 12} structure 731 * 732 * Returns 0 on success, -EINVAL if the property does not exist, 733 * -ENODATA if property does not have a value, and -EOVERFLOW if the 734 * property data isn't large enough. 735 */ 736 static int parse_thread_groups(struct device_node *dn, 737 struct thread_groups *tg, 738 unsigned int property) 739 { 740 int i; 741 u32 thread_group_array[3 + MAX_THREAD_LIST_SIZE]; 742 u32 *thread_list; 743 size_t total_threads; 744 int ret; 745 746 ret = of_property_read_u32_array(dn, "ibm,thread-groups", 747 thread_group_array, 3); 748 if (ret) 749 return ret; 750 751 tg->property = thread_group_array[0]; 752 tg->nr_groups = thread_group_array[1]; 753 tg->threads_per_group = thread_group_array[2]; 754 if (tg->property != property || 755 tg->nr_groups < 1 || 756 tg->threads_per_group < 1) 757 return -ENODATA; 758 759 total_threads = tg->nr_groups * tg->threads_per_group; 760 761 ret = of_property_read_u32_array(dn, "ibm,thread-groups", 762 thread_group_array, 763 3 + total_threads); 764 if (ret) 765 return ret; 766 767 thread_list = &thread_group_array[3]; 768 769 for (i = 0 ; i < total_threads; i++) 770 tg->thread_list[i] = thread_list[i]; 771 772 return 0; 773 } 774 775 /* 776 * get_cpu_thread_group_start : Searches the thread group in tg->thread_list 777 * that @cpu belongs to. 778 * 779 * @cpu : The logical CPU whose thread group is being searched. 780 * @tg : The thread-group structure of the CPU node which @cpu belongs 781 * to. 782 * 783 * Returns the index to tg->thread_list that points to the the start 784 * of the thread_group that @cpu belongs to. 785 * 786 * Returns -1 if cpu doesn't belong to any of the groups pointed to by 787 * tg->thread_list. 788 */ 789 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg) 790 { 791 int hw_cpu_id = get_hard_smp_processor_id(cpu); 792 int i, j; 793 794 for (i = 0; i < tg->nr_groups; i++) { 795 int group_start = i * tg->threads_per_group; 796 797 for (j = 0; j < tg->threads_per_group; j++) { 798 int idx = group_start + j; 799 800 if (tg->thread_list[idx] == hw_cpu_id) 801 return group_start; 802 } 803 } 804 805 return -1; 806 } 807 808 static int init_cpu_l1_cache_map(int cpu) 809 810 { 811 struct device_node *dn = of_get_cpu_node(cpu, NULL); 812 struct thread_groups tg = {.property = 0, 813 .nr_groups = 0, 814 .threads_per_group = 0}; 815 int first_thread = cpu_first_thread_sibling(cpu); 816 int i, cpu_group_start = -1, err = 0; 817 818 if (!dn) 819 return -ENODATA; 820 821 err = parse_thread_groups(dn, &tg, THREAD_GROUP_SHARE_L1); 822 if (err) 823 goto out; 824 825 cpu_group_start = get_cpu_thread_group_start(cpu, &tg); 826 827 if (unlikely(cpu_group_start == -1)) { 828 WARN_ON_ONCE(1); 829 err = -ENODATA; 830 goto out; 831 } 832 833 zalloc_cpumask_var_node(&per_cpu(cpu_l1_cache_map, cpu), 834 GFP_KERNEL, cpu_to_node(cpu)); 835 836 for (i = first_thread; i < first_thread + threads_per_core; i++) { 837 int i_group_start = get_cpu_thread_group_start(i, &tg); 838 839 if (unlikely(i_group_start == -1)) { 840 WARN_ON_ONCE(1); 841 err = -ENODATA; 842 goto out; 843 } 844 845 if (i_group_start == cpu_group_start) 846 cpumask_set_cpu(i, per_cpu(cpu_l1_cache_map, cpu)); 847 } 848 849 out: 850 of_node_put(dn); 851 return err; 852 } 853 854 static bool shared_caches; 855 856 #ifdef CONFIG_SCHED_SMT 857 /* cpumask of CPUs with asymmetric SMT dependency */ 858 static int powerpc_smt_flags(void) 859 { 860 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; 861 862 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { 863 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); 864 flags |= SD_ASYM_PACKING; 865 } 866 return flags; 867 } 868 #endif 869 870 /* 871 * P9 has a slightly odd architecture where pairs of cores share an L2 cache. 872 * This topology makes it *much* cheaper to migrate tasks between adjacent cores 873 * since the migrated task remains cache hot. We want to take advantage of this 874 * at the scheduler level so an extra topology level is required. 875 */ 876 static int powerpc_shared_cache_flags(void) 877 { 878 return SD_SHARE_PKG_RESOURCES; 879 } 880 881 /* 882 * We can't just pass cpu_l2_cache_mask() directly because 883 * returns a non-const pointer and the compiler barfs on that. 884 */ 885 static const struct cpumask *shared_cache_mask(int cpu) 886 { 887 return per_cpu(cpu_l2_cache_map, cpu); 888 } 889 890 #ifdef CONFIG_SCHED_SMT 891 static const struct cpumask *smallcore_smt_mask(int cpu) 892 { 893 return cpu_smallcore_mask(cpu); 894 } 895 #endif 896 897 static struct cpumask *cpu_coregroup_mask(int cpu) 898 { 899 return per_cpu(cpu_coregroup_map, cpu); 900 } 901 902 static bool has_coregroup_support(void) 903 { 904 return coregroup_enabled; 905 } 906 907 static const struct cpumask *cpu_mc_mask(int cpu) 908 { 909 return cpu_coregroup_mask(cpu); 910 } 911 912 static struct sched_domain_topology_level powerpc_topology[] = { 913 #ifdef CONFIG_SCHED_SMT 914 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, 915 #endif 916 { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, 917 { cpu_mc_mask, SD_INIT_NAME(MC) }, 918 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 919 { NULL, }, 920 }; 921 922 static int init_big_cores(void) 923 { 924 int cpu; 925 926 for_each_possible_cpu(cpu) { 927 int err = init_cpu_l1_cache_map(cpu); 928 929 if (err) 930 return err; 931 932 zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu), 933 GFP_KERNEL, 934 cpu_to_node(cpu)); 935 } 936 937 has_big_cores = true; 938 return 0; 939 } 940 941 void __init smp_prepare_cpus(unsigned int max_cpus) 942 { 943 unsigned int cpu; 944 945 DBG("smp_prepare_cpus\n"); 946 947 /* 948 * setup_cpu may need to be called on the boot cpu. We havent 949 * spun any cpus up but lets be paranoid. 950 */ 951 BUG_ON(boot_cpuid != smp_processor_id()); 952 953 /* Fixup boot cpu */ 954 smp_store_cpu_info(boot_cpuid); 955 cpu_callin_map[boot_cpuid] = 1; 956 957 for_each_possible_cpu(cpu) { 958 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), 959 GFP_KERNEL, cpu_to_node(cpu)); 960 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu), 961 GFP_KERNEL, cpu_to_node(cpu)); 962 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), 963 GFP_KERNEL, cpu_to_node(cpu)); 964 if (has_coregroup_support()) 965 zalloc_cpumask_var_node(&per_cpu(cpu_coregroup_map, cpu), 966 GFP_KERNEL, cpu_to_node(cpu)); 967 968 #ifdef CONFIG_NEED_MULTIPLE_NODES 969 /* 970 * numa_node_id() works after this. 971 */ 972 if (cpu_present(cpu)) { 973 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); 974 set_cpu_numa_mem(cpu, 975 local_memory_node(numa_cpu_lookup_table[cpu])); 976 } 977 #endif 978 /* 979 * cpu_core_map is now more updated and exists only since 980 * its been exported for long. It only will have a snapshot 981 * of cpu_cpu_mask. 982 */ 983 cpumask_copy(per_cpu(cpu_core_map, cpu), cpu_cpu_mask(cpu)); 984 } 985 986 /* Init the cpumasks so the boot CPU is related to itself */ 987 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); 988 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid)); 989 990 if (has_coregroup_support()) 991 cpumask_set_cpu(boot_cpuid, cpu_coregroup_mask(boot_cpuid)); 992 993 init_big_cores(); 994 if (has_big_cores) { 995 cpumask_set_cpu(boot_cpuid, 996 cpu_smallcore_mask(boot_cpuid)); 997 } 998 999 if (smp_ops && smp_ops->probe) 1000 smp_ops->probe(); 1001 } 1002 1003 void smp_prepare_boot_cpu(void) 1004 { 1005 BUG_ON(smp_processor_id() != boot_cpuid); 1006 #ifdef CONFIG_PPC64 1007 paca_ptrs[boot_cpuid]->__current = current; 1008 #endif 1009 set_numa_node(numa_cpu_lookup_table[boot_cpuid]); 1010 current_set[boot_cpuid] = current; 1011 } 1012 1013 #ifdef CONFIG_HOTPLUG_CPU 1014 1015 int generic_cpu_disable(void) 1016 { 1017 unsigned int cpu = smp_processor_id(); 1018 1019 if (cpu == boot_cpuid) 1020 return -EBUSY; 1021 1022 set_cpu_online(cpu, false); 1023 #ifdef CONFIG_PPC64 1024 vdso_data->processorCount--; 1025 #endif 1026 /* Update affinity of all IRQs previously aimed at this CPU */ 1027 irq_migrate_all_off_this_cpu(); 1028 1029 /* 1030 * Depending on the details of the interrupt controller, it's possible 1031 * that one of the interrupts we just migrated away from this CPU is 1032 * actually already pending on this CPU. If we leave it in that state 1033 * the interrupt will never be EOI'ed, and will never fire again. So 1034 * temporarily enable interrupts here, to allow any pending interrupt to 1035 * be received (and EOI'ed), before we take this CPU offline. 1036 */ 1037 local_irq_enable(); 1038 mdelay(1); 1039 local_irq_disable(); 1040 1041 return 0; 1042 } 1043 1044 void generic_cpu_die(unsigned int cpu) 1045 { 1046 int i; 1047 1048 for (i = 0; i < 100; i++) { 1049 smp_rmb(); 1050 if (is_cpu_dead(cpu)) 1051 return; 1052 msleep(100); 1053 } 1054 printk(KERN_ERR "CPU%d didn't die...\n", cpu); 1055 } 1056 1057 void generic_set_cpu_dead(unsigned int cpu) 1058 { 1059 per_cpu(cpu_state, cpu) = CPU_DEAD; 1060 } 1061 1062 /* 1063 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise 1064 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), 1065 * which makes the delay in generic_cpu_die() not happen. 1066 */ 1067 void generic_set_cpu_up(unsigned int cpu) 1068 { 1069 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 1070 } 1071 1072 int generic_check_cpu_restart(unsigned int cpu) 1073 { 1074 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; 1075 } 1076 1077 int is_cpu_dead(unsigned int cpu) 1078 { 1079 return per_cpu(cpu_state, cpu) == CPU_DEAD; 1080 } 1081 1082 static bool secondaries_inhibited(void) 1083 { 1084 return kvm_hv_mode_active(); 1085 } 1086 1087 #else /* HOTPLUG_CPU */ 1088 1089 #define secondaries_inhibited() 0 1090 1091 #endif 1092 1093 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) 1094 { 1095 #ifdef CONFIG_PPC64 1096 paca_ptrs[cpu]->__current = idle; 1097 paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) + 1098 THREAD_SIZE - STACK_FRAME_OVERHEAD; 1099 #endif 1100 idle->cpu = cpu; 1101 secondary_current = current_set[cpu] = idle; 1102 } 1103 1104 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 1105 { 1106 int rc, c; 1107 1108 /* 1109 * Don't allow secondary threads to come online if inhibited 1110 */ 1111 if (threads_per_core > 1 && secondaries_inhibited() && 1112 cpu_thread_in_subcore(cpu)) 1113 return -EBUSY; 1114 1115 if (smp_ops == NULL || 1116 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) 1117 return -EINVAL; 1118 1119 cpu_idle_thread_init(cpu, tidle); 1120 1121 /* 1122 * The platform might need to allocate resources prior to bringing 1123 * up the CPU 1124 */ 1125 if (smp_ops->prepare_cpu) { 1126 rc = smp_ops->prepare_cpu(cpu); 1127 if (rc) 1128 return rc; 1129 } 1130 1131 /* Make sure callin-map entry is 0 (can be leftover a CPU 1132 * hotplug 1133 */ 1134 cpu_callin_map[cpu] = 0; 1135 1136 /* The information for processor bringup must 1137 * be written out to main store before we release 1138 * the processor. 1139 */ 1140 smp_mb(); 1141 1142 /* wake up cpus */ 1143 DBG("smp: kicking cpu %d\n", cpu); 1144 rc = smp_ops->kick_cpu(cpu); 1145 if (rc) { 1146 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); 1147 return rc; 1148 } 1149 1150 /* 1151 * wait to see if the cpu made a callin (is actually up). 1152 * use this value that I found through experimentation. 1153 * -- Cort 1154 */ 1155 if (system_state < SYSTEM_RUNNING) 1156 for (c = 50000; c && !cpu_callin_map[cpu]; c--) 1157 udelay(100); 1158 #ifdef CONFIG_HOTPLUG_CPU 1159 else 1160 /* 1161 * CPUs can take much longer to come up in the 1162 * hotplug case. Wait five seconds. 1163 */ 1164 for (c = 5000; c && !cpu_callin_map[cpu]; c--) 1165 msleep(1); 1166 #endif 1167 1168 if (!cpu_callin_map[cpu]) { 1169 printk(KERN_ERR "Processor %u is stuck.\n", cpu); 1170 return -ENOENT; 1171 } 1172 1173 DBG("Processor %u found.\n", cpu); 1174 1175 if (smp_ops->give_timebase) 1176 smp_ops->give_timebase(); 1177 1178 /* Wait until cpu puts itself in the online & active maps */ 1179 spin_until_cond(cpu_online(cpu)); 1180 1181 return 0; 1182 } 1183 1184 /* Return the value of the reg property corresponding to the given 1185 * logical cpu. 1186 */ 1187 int cpu_to_core_id(int cpu) 1188 { 1189 struct device_node *np; 1190 const __be32 *reg; 1191 int id = -1; 1192 1193 np = of_get_cpu_node(cpu, NULL); 1194 if (!np) 1195 goto out; 1196 1197 reg = of_get_property(np, "reg", NULL); 1198 if (!reg) 1199 goto out; 1200 1201 id = be32_to_cpup(reg); 1202 out: 1203 of_node_put(np); 1204 return id; 1205 } 1206 EXPORT_SYMBOL_GPL(cpu_to_core_id); 1207 1208 /* Helper routines for cpu to core mapping */ 1209 int cpu_core_index_of_thread(int cpu) 1210 { 1211 return cpu >> threads_shift; 1212 } 1213 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); 1214 1215 int cpu_first_thread_of_core(int core) 1216 { 1217 return core << threads_shift; 1218 } 1219 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); 1220 1221 /* Must be called when no change can occur to cpu_present_mask, 1222 * i.e. during cpu online or offline. 1223 */ 1224 static struct device_node *cpu_to_l2cache(int cpu) 1225 { 1226 struct device_node *np; 1227 struct device_node *cache; 1228 1229 if (!cpu_present(cpu)) 1230 return NULL; 1231 1232 np = of_get_cpu_node(cpu, NULL); 1233 if (np == NULL) 1234 return NULL; 1235 1236 cache = of_find_next_cache_node(np); 1237 1238 of_node_put(np); 1239 1240 return cache; 1241 } 1242 1243 static bool update_mask_by_l2(int cpu, cpumask_var_t *mask) 1244 { 1245 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask; 1246 struct device_node *l2_cache, *np; 1247 int i; 1248 1249 if (has_big_cores) 1250 submask_fn = cpu_smallcore_mask; 1251 1252 l2_cache = cpu_to_l2cache(cpu); 1253 if (!l2_cache || !*mask) { 1254 /* Assume only core siblings share cache with this CPU */ 1255 for_each_cpu(i, submask_fn(cpu)) 1256 set_cpus_related(cpu, i, cpu_l2_cache_mask); 1257 1258 return false; 1259 } 1260 1261 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu)); 1262 1263 /* Update l2-cache mask with all the CPUs that are part of submask */ 1264 or_cpumasks_related(cpu, cpu, submask_fn, cpu_l2_cache_mask); 1265 1266 /* Skip all CPUs already part of current CPU l2-cache mask */ 1267 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(cpu)); 1268 1269 for_each_cpu(i, *mask) { 1270 /* 1271 * when updating the marks the current CPU has not been marked 1272 * online, but we need to update the cache masks 1273 */ 1274 np = cpu_to_l2cache(i); 1275 1276 /* Skip all CPUs already part of current CPU l2-cache */ 1277 if (np == l2_cache) { 1278 or_cpumasks_related(cpu, i, submask_fn, cpu_l2_cache_mask); 1279 cpumask_andnot(*mask, *mask, submask_fn(i)); 1280 } else { 1281 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(i)); 1282 } 1283 1284 of_node_put(np); 1285 } 1286 of_node_put(l2_cache); 1287 1288 return true; 1289 } 1290 1291 #ifdef CONFIG_HOTPLUG_CPU 1292 static void remove_cpu_from_masks(int cpu) 1293 { 1294 struct cpumask *(*mask_fn)(int) = cpu_sibling_mask; 1295 int i; 1296 1297 if (shared_caches) 1298 mask_fn = cpu_l2_cache_mask; 1299 1300 for_each_cpu(i, mask_fn(cpu)) { 1301 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask); 1302 set_cpus_unrelated(cpu, i, cpu_sibling_mask); 1303 if (has_big_cores) 1304 set_cpus_unrelated(cpu, i, cpu_smallcore_mask); 1305 } 1306 1307 if (has_coregroup_support()) { 1308 for_each_cpu(i, cpu_coregroup_mask(cpu)) 1309 set_cpus_unrelated(cpu, i, cpu_coregroup_mask); 1310 } 1311 } 1312 #endif 1313 1314 static inline void add_cpu_to_smallcore_masks(int cpu) 1315 { 1316 int i; 1317 1318 if (!has_big_cores) 1319 return; 1320 1321 cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu)); 1322 1323 for_each_cpu(i, per_cpu(cpu_l1_cache_map, cpu)) { 1324 if (cpu_online(i)) 1325 set_cpus_related(i, cpu, cpu_smallcore_mask); 1326 } 1327 } 1328 1329 static void update_coregroup_mask(int cpu, cpumask_var_t *mask) 1330 { 1331 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask; 1332 int coregroup_id = cpu_to_coregroup_id(cpu); 1333 int i; 1334 1335 if (shared_caches) 1336 submask_fn = cpu_l2_cache_mask; 1337 1338 if (!*mask) { 1339 /* Assume only siblings are part of this CPU's coregroup */ 1340 for_each_cpu(i, submask_fn(cpu)) 1341 set_cpus_related(cpu, i, cpu_coregroup_mask); 1342 1343 return; 1344 } 1345 1346 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu)); 1347 1348 /* Update coregroup mask with all the CPUs that are part of submask */ 1349 or_cpumasks_related(cpu, cpu, submask_fn, cpu_coregroup_mask); 1350 1351 /* Skip all CPUs already part of coregroup mask */ 1352 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(cpu)); 1353 1354 for_each_cpu(i, *mask) { 1355 /* Skip all CPUs not part of this coregroup */ 1356 if (coregroup_id == cpu_to_coregroup_id(i)) { 1357 or_cpumasks_related(cpu, i, submask_fn, cpu_coregroup_mask); 1358 cpumask_andnot(*mask, *mask, submask_fn(i)); 1359 } else { 1360 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(i)); 1361 } 1362 } 1363 } 1364 1365 static void add_cpu_to_masks(int cpu) 1366 { 1367 int first_thread = cpu_first_thread_sibling(cpu); 1368 cpumask_var_t mask; 1369 int i; 1370 1371 /* 1372 * This CPU will not be in the online mask yet so we need to manually 1373 * add it to it's own thread sibling mask. 1374 */ 1375 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 1376 1377 for (i = first_thread; i < first_thread + threads_per_core; i++) 1378 if (cpu_online(i)) 1379 set_cpus_related(i, cpu, cpu_sibling_mask); 1380 1381 add_cpu_to_smallcore_masks(cpu); 1382 1383 /* In CPU-hotplug path, hence use GFP_ATOMIC */ 1384 alloc_cpumask_var_node(&mask, GFP_ATOMIC, cpu_to_node(cpu)); 1385 update_mask_by_l2(cpu, &mask); 1386 1387 if (has_coregroup_support()) 1388 update_coregroup_mask(cpu, &mask); 1389 1390 free_cpumask_var(mask); 1391 } 1392 1393 /* Activate a secondary processor. */ 1394 void start_secondary(void *unused) 1395 { 1396 unsigned int cpu = smp_processor_id(); 1397 1398 mmgrab(&init_mm); 1399 current->active_mm = &init_mm; 1400 1401 smp_store_cpu_info(cpu); 1402 set_dec(tb_ticks_per_jiffy); 1403 preempt_disable(); 1404 cpu_callin_map[cpu] = 1; 1405 1406 if (smp_ops->setup_cpu) 1407 smp_ops->setup_cpu(cpu); 1408 if (smp_ops->take_timebase) 1409 smp_ops->take_timebase(); 1410 1411 secondary_cpu_time_init(); 1412 1413 #ifdef CONFIG_PPC64 1414 if (system_state == SYSTEM_RUNNING) 1415 vdso_data->processorCount++; 1416 1417 vdso_getcpu_init(); 1418 #endif 1419 /* Update topology CPU masks */ 1420 add_cpu_to_masks(cpu); 1421 1422 /* 1423 * Check for any shared caches. Note that this must be done on a 1424 * per-core basis because one core in the pair might be disabled. 1425 */ 1426 if (!shared_caches) { 1427 struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask; 1428 struct cpumask *mask = cpu_l2_cache_mask(cpu); 1429 1430 if (has_big_cores) 1431 sibling_mask = cpu_smallcore_mask; 1432 1433 if (cpumask_weight(mask) > cpumask_weight(sibling_mask(cpu))) 1434 shared_caches = true; 1435 } 1436 1437 set_numa_node(numa_cpu_lookup_table[cpu]); 1438 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); 1439 1440 smp_wmb(); 1441 notify_cpu_starting(cpu); 1442 set_cpu_online(cpu, true); 1443 1444 boot_init_stack_canary(); 1445 1446 local_irq_enable(); 1447 1448 /* We can enable ftrace for secondary cpus now */ 1449 this_cpu_enable_ftrace(); 1450 1451 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 1452 1453 BUG(); 1454 } 1455 1456 int setup_profiling_timer(unsigned int multiplier) 1457 { 1458 return 0; 1459 } 1460 1461 static void fixup_topology(void) 1462 { 1463 int i; 1464 1465 #ifdef CONFIG_SCHED_SMT 1466 if (has_big_cores) { 1467 pr_info("Big cores detected but using small core scheduling\n"); 1468 powerpc_topology[smt_idx].mask = smallcore_smt_mask; 1469 } 1470 #endif 1471 1472 if (!has_coregroup_support()) 1473 powerpc_topology[mc_idx].mask = powerpc_topology[cache_idx].mask; 1474 1475 /* 1476 * Try to consolidate topology levels here instead of 1477 * allowing scheduler to degenerate. 1478 * - Dont consolidate if masks are different. 1479 * - Dont consolidate if sd_flags exists and are different. 1480 */ 1481 for (i = 1; i <= die_idx; i++) { 1482 if (powerpc_topology[i].mask != powerpc_topology[i - 1].mask) 1483 continue; 1484 1485 if (powerpc_topology[i].sd_flags && powerpc_topology[i - 1].sd_flags && 1486 powerpc_topology[i].sd_flags != powerpc_topology[i - 1].sd_flags) 1487 continue; 1488 1489 if (!powerpc_topology[i - 1].sd_flags) 1490 powerpc_topology[i - 1].sd_flags = powerpc_topology[i].sd_flags; 1491 1492 powerpc_topology[i].mask = powerpc_topology[i + 1].mask; 1493 powerpc_topology[i].sd_flags = powerpc_topology[i + 1].sd_flags; 1494 #ifdef CONFIG_SCHED_DEBUG 1495 powerpc_topology[i].name = powerpc_topology[i + 1].name; 1496 #endif 1497 } 1498 } 1499 1500 void __init smp_cpus_done(unsigned int max_cpus) 1501 { 1502 /* 1503 * We are running pinned to the boot CPU, see rest_init(). 1504 */ 1505 if (smp_ops && smp_ops->setup_cpu) 1506 smp_ops->setup_cpu(boot_cpuid); 1507 1508 if (smp_ops && smp_ops->bringup_done) 1509 smp_ops->bringup_done(); 1510 1511 dump_numa_cpu_topology(); 1512 1513 fixup_topology(); 1514 set_sched_topology(powerpc_topology); 1515 } 1516 1517 #ifdef CONFIG_HOTPLUG_CPU 1518 int __cpu_disable(void) 1519 { 1520 int cpu = smp_processor_id(); 1521 int err; 1522 1523 if (!smp_ops->cpu_disable) 1524 return -ENOSYS; 1525 1526 this_cpu_disable_ftrace(); 1527 1528 err = smp_ops->cpu_disable(); 1529 if (err) 1530 return err; 1531 1532 /* Update sibling maps */ 1533 remove_cpu_from_masks(cpu); 1534 1535 return 0; 1536 } 1537 1538 void __cpu_die(unsigned int cpu) 1539 { 1540 if (smp_ops->cpu_die) 1541 smp_ops->cpu_die(cpu); 1542 } 1543 1544 void arch_cpu_idle_dead(void) 1545 { 1546 sched_preempt_enable_no_resched(); 1547 1548 /* 1549 * Disable on the down path. This will be re-enabled by 1550 * start_secondary() via start_secondary_resume() below 1551 */ 1552 this_cpu_disable_ftrace(); 1553 1554 if (smp_ops->cpu_offline_self) 1555 smp_ops->cpu_offline_self(); 1556 1557 /* If we return, we re-enter start_secondary */ 1558 start_secondary_resume(); 1559 } 1560 1561 #endif 1562