1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * Common boot and setup code. 5 * 6 * Copyright (C) 2001 PPC64 Team, IBM Corp 7 */ 8 9 #include <linux/export.h> 10 #include <linux/string.h> 11 #include <linux/sched.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/reboot.h> 15 #include <linux/delay.h> 16 #include <linux/initrd.h> 17 #include <linux/seq_file.h> 18 #include <linux/ioport.h> 19 #include <linux/console.h> 20 #include <linux/utsname.h> 21 #include <linux/tty.h> 22 #include <linux/root_dev.h> 23 #include <linux/notifier.h> 24 #include <linux/cpu.h> 25 #include <linux/unistd.h> 26 #include <linux/serial.h> 27 #include <linux/serial_8250.h> 28 #include <linux/memblock.h> 29 #include <linux/pci.h> 30 #include <linux/lockdep.h> 31 #include <linux/memory.h> 32 #include <linux/nmi.h> 33 #include <linux/pgtable.h> 34 #include <linux/of.h> 35 #include <linux/of_fdt.h> 36 37 #include <asm/kvm_guest.h> 38 #include <asm/io.h> 39 #include <asm/kdump.h> 40 #include <asm/processor.h> 41 #include <asm/smp.h> 42 #include <asm/elf.h> 43 #include <asm/machdep.h> 44 #include <asm/paca.h> 45 #include <asm/time.h> 46 #include <asm/cputable.h> 47 #include <asm/dt_cpu_ftrs.h> 48 #include <asm/sections.h> 49 #include <asm/btext.h> 50 #include <asm/nvram.h> 51 #include <asm/setup.h> 52 #include <asm/rtas.h> 53 #include <asm/iommu.h> 54 #include <asm/serial.h> 55 #include <asm/cache.h> 56 #include <asm/page.h> 57 #include <asm/mmu.h> 58 #include <asm/firmware.h> 59 #include <asm/xmon.h> 60 #include <asm/udbg.h> 61 #include <asm/kexec.h> 62 #include <asm/code-patching.h> 63 #include <asm/ftrace.h> 64 #include <asm/opal.h> 65 #include <asm/cputhreads.h> 66 #include <asm/hw_irq.h> 67 #include <asm/feature-fixups.h> 68 #include <asm/kup.h> 69 #include <asm/early_ioremap.h> 70 #include <asm/pgalloc.h> 71 72 #include "setup.h" 73 74 int spinning_secondaries; 75 u64 ppc64_pft_size; 76 77 struct ppc64_caches ppc64_caches = { 78 .l1d = { 79 .block_size = 0x40, 80 .log_block_size = 6, 81 }, 82 .l1i = { 83 .block_size = 0x40, 84 .log_block_size = 6 85 }, 86 }; 87 EXPORT_SYMBOL_GPL(ppc64_caches); 88 89 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 90 void __init setup_tlb_core_data(void) 91 { 92 int cpu; 93 94 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 95 96 for_each_possible_cpu(cpu) { 97 int first = cpu_first_thread_sibling(cpu); 98 99 /* 100 * If we boot via kdump on a non-primary thread, 101 * make sure we point at the thread that actually 102 * set up this TLB. 103 */ 104 if (cpu_first_thread_sibling(boot_cpuid) == first) 105 first = boot_cpuid; 106 107 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; 108 109 /* 110 * If we have threads, we need either tlbsrx. 111 * or e6500 tablewalk mode, or else TLB handlers 112 * will be racy and could produce duplicate entries. 113 * Should we panic instead? 114 */ 115 WARN_ONCE(smt_enabled_at_boot >= 2 && 116 book3e_htw_mode != PPC_HTW_E6500, 117 "%s: unsupported MMU configuration\n", __func__); 118 } 119 } 120 #endif 121 122 #ifdef CONFIG_SMP 123 124 static char *smt_enabled_cmdline; 125 126 /* Look for ibm,smt-enabled OF option */ 127 void __init check_smt_enabled(void) 128 { 129 struct device_node *dn; 130 const char *smt_option; 131 132 /* Default to enabling all threads */ 133 smt_enabled_at_boot = threads_per_core; 134 135 /* Allow the command line to overrule the OF option */ 136 if (smt_enabled_cmdline) { 137 if (!strcmp(smt_enabled_cmdline, "on")) 138 smt_enabled_at_boot = threads_per_core; 139 else if (!strcmp(smt_enabled_cmdline, "off")) 140 smt_enabled_at_boot = 0; 141 else { 142 int smt; 143 int rc; 144 145 rc = kstrtoint(smt_enabled_cmdline, 10, &smt); 146 if (!rc) 147 smt_enabled_at_boot = 148 min(threads_per_core, smt); 149 } 150 } else { 151 dn = of_find_node_by_path("/options"); 152 if (dn) { 153 smt_option = of_get_property(dn, "ibm,smt-enabled", 154 NULL); 155 156 if (smt_option) { 157 if (!strcmp(smt_option, "on")) 158 smt_enabled_at_boot = threads_per_core; 159 else if (!strcmp(smt_option, "off")) 160 smt_enabled_at_boot = 0; 161 } 162 163 of_node_put(dn); 164 } 165 } 166 } 167 168 /* Look for smt-enabled= cmdline option */ 169 static int __init early_smt_enabled(char *p) 170 { 171 smt_enabled_cmdline = p; 172 return 0; 173 } 174 early_param("smt-enabled", early_smt_enabled); 175 176 #endif /* CONFIG_SMP */ 177 178 /** Fix up paca fields required for the boot cpu */ 179 static void __init fixup_boot_paca(void) 180 { 181 /* The boot cpu is started */ 182 get_paca()->cpu_start = 1; 183 /* Allow percpu accesses to work until we setup percpu data */ 184 get_paca()->data_offset = 0; 185 /* Mark interrupts disabled in PACA */ 186 irq_soft_mask_set(IRQS_DISABLED); 187 } 188 189 static void __init configure_exceptions(void) 190 { 191 /* 192 * Setup the trampolines from the lowmem exception vectors 193 * to the kdump kernel when not using a relocatable kernel. 194 */ 195 setup_kdump_trampoline(); 196 197 /* Under a PAPR hypervisor, we need hypercalls */ 198 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 199 /* 200 * - PR KVM does not support AIL mode interrupts in the host 201 * while a PR guest is running. 202 * 203 * - SCV system call interrupt vectors are only implemented for 204 * AIL mode interrupts. 205 * 206 * - On pseries, AIL mode can only be enabled and disabled 207 * system-wide so when a PR VM is created on a pseries host, 208 * all CPUs of the host are set to AIL=0 mode. 209 * 210 * - Therefore host CPUs must not execute scv while a PR VM 211 * exists. 212 * 213 * - SCV support can not be disabled dynamically because the 214 * feature is advertised to host userspace. Disabling the 215 * facility and emulating it would be possible but is not 216 * implemented. 217 * 218 * - So SCV support is blanket disabled if PR KVM could possibly 219 * run. That is, PR support compiled in, booting on pseries 220 * with hash MMU. 221 */ 222 if (IS_ENABLED(CONFIG_KVM_BOOK3S_PR_POSSIBLE) && !radix_enabled()) { 223 init_task.thread.fscr &= ~FSCR_SCV; 224 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV; 225 } 226 227 /* Enable AIL if possible */ 228 if (!pseries_enable_reloc_on_exc()) { 229 init_task.thread.fscr &= ~FSCR_SCV; 230 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV; 231 } 232 233 /* 234 * Tell the hypervisor that we want our exceptions to 235 * be taken in little endian mode. 236 * 237 * We don't call this for big endian as our calling convention 238 * makes us always enter in BE, and the call may fail under 239 * some circumstances with kdump. 240 */ 241 #ifdef __LITTLE_ENDIAN__ 242 pseries_little_endian_exceptions(); 243 #endif 244 } else { 245 /* Set endian mode using OPAL */ 246 if (firmware_has_feature(FW_FEATURE_OPAL)) 247 opal_configure_cores(); 248 249 /* AIL on native is done in cpu_ready_for_interrupts() */ 250 } 251 } 252 253 static void cpu_ready_for_interrupts(void) 254 { 255 /* 256 * Enable AIL if supported, and we are in hypervisor mode. This 257 * is called once for every processor. 258 * 259 * If we are not in hypervisor mode the job is done once for 260 * the whole partition in configure_exceptions(). 261 */ 262 if (cpu_has_feature(CPU_FTR_HVMODE)) { 263 unsigned long lpcr = mfspr(SPRN_LPCR); 264 unsigned long new_lpcr = lpcr; 265 266 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 267 /* P10 DD1 does not have HAIL */ 268 if (pvr_version_is(PVR_POWER10) && 269 (mfspr(SPRN_PVR) & 0xf00) == 0x100) 270 new_lpcr |= LPCR_AIL_3; 271 else 272 new_lpcr |= LPCR_HAIL; 273 } else if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 274 new_lpcr |= LPCR_AIL_3; 275 } 276 277 if (new_lpcr != lpcr) 278 mtspr(SPRN_LPCR, new_lpcr); 279 } 280 281 /* 282 * Set HFSCR:TM based on CPU features: 283 * In the special case of TM no suspend (P9N DD2.1), Linux is 284 * told TM is off via the dt-ftrs but told to (partially) use 285 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM] 286 * will be off from dt-ftrs but we need to turn it on for the 287 * no suspend case. 288 */ 289 if (cpu_has_feature(CPU_FTR_HVMODE)) { 290 if (cpu_has_feature(CPU_FTR_TM_COMP)) 291 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM); 292 else 293 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM); 294 } 295 296 /* Set IR and DR in PACA MSR */ 297 get_paca()->kernel_msr = MSR_KERNEL; 298 } 299 300 unsigned long spr_default_dscr = 0; 301 302 static void __init record_spr_defaults(void) 303 { 304 if (early_cpu_has_feature(CPU_FTR_DSCR)) 305 spr_default_dscr = mfspr(SPRN_DSCR); 306 } 307 308 /* 309 * Early initialization entry point. This is called by head.S 310 * with MMU translation disabled. We rely on the "feature" of 311 * the CPU that ignores the top 2 bits of the address in real 312 * mode so we can access kernel globals normally provided we 313 * only toy with things in the RMO region. From here, we do 314 * some early parsing of the device-tree to setup out MEMBLOCK 315 * data structures, and allocate & initialize the hash table 316 * and segment tables so we can start running with translation 317 * enabled. 318 * 319 * It is this function which will call the probe() callback of 320 * the various platform types and copy the matching one to the 321 * global ppc_md structure. Your platform can eventually do 322 * some very early initializations from the probe() routine, but 323 * this is not recommended, be very careful as, for example, the 324 * device-tree is not accessible via normal means at this point. 325 */ 326 327 void __init early_setup(unsigned long dt_ptr) 328 { 329 static __initdata struct paca_struct boot_paca; 330 331 /* -------- printk is _NOT_ safe to use here ! ------- */ 332 333 /* 334 * Assume we're on cpu 0 for now. 335 * 336 * We need to load a PACA very early for a few reasons. 337 * 338 * The stack protector canary is stored in the paca, so as soon as we 339 * call any stack protected code we need r13 pointing somewhere valid. 340 * 341 * If we are using kcov it will call in_task() in its instrumentation, 342 * which relies on the current task from the PACA. 343 * 344 * dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as 345 * printk(), which can trigger both stack protector and kcov. 346 * 347 * percpu variables and spin locks also use the paca. 348 * 349 * So set up a temporary paca. It will be replaced below once we know 350 * what CPU we are on. 351 */ 352 initialise_paca(&boot_paca, 0); 353 setup_paca(&boot_paca); 354 fixup_boot_paca(); 355 356 /* -------- printk is now safe to use ------- */ 357 358 /* Try new device tree based feature discovery ... */ 359 if (!dt_cpu_ftrs_init(__va(dt_ptr))) 360 /* Otherwise use the old style CPU table */ 361 identify_cpu(0, mfspr(SPRN_PVR)); 362 363 /* Enable early debugging if any specified (see udbg.h) */ 364 udbg_early_init(); 365 366 udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr); 367 368 /* 369 * Do early initialization using the flattened device 370 * tree, such as retrieving the physical memory map or 371 * calculating/retrieving the hash table size. 372 */ 373 early_init_devtree(__va(dt_ptr)); 374 375 /* Now we know the logical id of our boot cpu, setup the paca. */ 376 if (boot_cpuid != 0) { 377 /* Poison paca_ptrs[0] again if it's not the boot cpu */ 378 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0])); 379 } 380 setup_paca(paca_ptrs[boot_cpuid]); 381 fixup_boot_paca(); 382 383 /* 384 * Configure exception handlers. This include setting up trampolines 385 * if needed, setting exception endian mode, etc... 386 */ 387 configure_exceptions(); 388 389 /* 390 * Configure Kernel Userspace Protection. This needs to happen before 391 * feature fixups for platforms that implement this using features. 392 */ 393 setup_kup(); 394 395 /* Apply all the dynamic patching */ 396 apply_feature_fixups(); 397 setup_feature_keys(); 398 399 /* Initialize the hash table or TLB handling */ 400 early_init_mmu(); 401 402 early_ioremap_setup(); 403 404 /* 405 * After firmware and early platform setup code has set things up, 406 * we note the SPR values for configurable control/performance 407 * registers, and use those as initial defaults. 408 */ 409 record_spr_defaults(); 410 411 /* 412 * At this point, we can let interrupts switch to virtual mode 413 * (the MMU has been setup), so adjust the MSR in the PACA to 414 * have IR and DR set and enable AIL if it exists 415 */ 416 cpu_ready_for_interrupts(); 417 418 /* 419 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it 420 * will only actually get enabled on the boot cpu much later once 421 * ftrace itself has been initialized. 422 */ 423 this_cpu_enable_ftrace(); 424 425 udbg_printf(" <- %s()\n", __func__); 426 427 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 428 /* 429 * This needs to be done *last* (after the above udbg_printf() even) 430 * 431 * Right after we return from this function, we turn on the MMU 432 * which means the real-mode access trick that btext does will 433 * no longer work, it needs to switch to using a real MMU 434 * mapping. This call will ensure that it does 435 */ 436 btext_map(); 437 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 438 } 439 440 #ifdef CONFIG_SMP 441 void early_setup_secondary(void) 442 { 443 /* Mark interrupts disabled in PACA */ 444 irq_soft_mask_set(IRQS_DISABLED); 445 446 /* Initialize the hash table or TLB handling */ 447 early_init_mmu_secondary(); 448 449 /* Perform any KUP setup that is per-cpu */ 450 setup_kup(); 451 452 /* 453 * At this point, we can let interrupts switch to virtual mode 454 * (the MMU has been setup), so adjust the MSR in the PACA to 455 * have IR and DR set. 456 */ 457 cpu_ready_for_interrupts(); 458 } 459 460 #endif /* CONFIG_SMP */ 461 462 void panic_smp_self_stop(void) 463 { 464 hard_irq_disable(); 465 spin_begin(); 466 while (1) 467 spin_cpu_relax(); 468 } 469 470 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 471 static bool use_spinloop(void) 472 { 473 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) { 474 /* 475 * See comments in head_64.S -- not all platforms insert 476 * secondaries at __secondary_hold and wait at the spin 477 * loop. 478 */ 479 if (firmware_has_feature(FW_FEATURE_OPAL)) 480 return false; 481 return true; 482 } 483 484 /* 485 * When book3e boots from kexec, the ePAPR spin table does 486 * not get used. 487 */ 488 return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); 489 } 490 491 void smp_release_cpus(void) 492 { 493 unsigned long *ptr; 494 int i; 495 496 if (!use_spinloop()) 497 return; 498 499 /* All secondary cpus are spinning on a common spinloop, release them 500 * all now so they can start to spin on their individual paca 501 * spinloops. For non SMP kernels, the secondary cpus never get out 502 * of the common spinloop. 503 */ 504 505 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 506 - PHYSICAL_START); 507 *ptr = ppc_function_entry(generic_secondary_smp_init); 508 509 /* And wait a bit for them to catch up */ 510 for (i = 0; i < 100000; i++) { 511 mb(); 512 HMT_low(); 513 if (spinning_secondaries == 0) 514 break; 515 udelay(1); 516 } 517 pr_debug("spinning_secondaries = %d\n", spinning_secondaries); 518 } 519 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */ 520 521 /* 522 * Initialize some remaining members of the ppc64_caches and systemcfg 523 * structures 524 * (at least until we get rid of them completely). This is mostly some 525 * cache informations about the CPU that will be used by cache flush 526 * routines and/or provided to userland 527 */ 528 529 static void __init init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize, 530 u32 bsize, u32 sets) 531 { 532 info->size = size; 533 info->sets = sets; 534 info->line_size = lsize; 535 info->block_size = bsize; 536 info->log_block_size = __ilog2(bsize); 537 if (bsize) 538 info->blocks_per_page = PAGE_SIZE / bsize; 539 else 540 info->blocks_per_page = 0; 541 542 if (sets == 0) 543 info->assoc = 0xffff; 544 else 545 info->assoc = size / (sets * lsize); 546 } 547 548 static bool __init parse_cache_info(struct device_node *np, 549 bool icache, 550 struct ppc_cache_info *info) 551 { 552 static const char *ipropnames[] __initdata = { 553 "i-cache-size", 554 "i-cache-sets", 555 "i-cache-block-size", 556 "i-cache-line-size", 557 }; 558 static const char *dpropnames[] __initdata = { 559 "d-cache-size", 560 "d-cache-sets", 561 "d-cache-block-size", 562 "d-cache-line-size", 563 }; 564 const char **propnames = icache ? ipropnames : dpropnames; 565 const __be32 *sizep, *lsizep, *bsizep, *setsp; 566 u32 size, lsize, bsize, sets; 567 bool success = true; 568 569 size = 0; 570 sets = -1u; 571 lsize = bsize = cur_cpu_spec->dcache_bsize; 572 sizep = of_get_property(np, propnames[0], NULL); 573 if (sizep != NULL) 574 size = be32_to_cpu(*sizep); 575 setsp = of_get_property(np, propnames[1], NULL); 576 if (setsp != NULL) 577 sets = be32_to_cpu(*setsp); 578 bsizep = of_get_property(np, propnames[2], NULL); 579 lsizep = of_get_property(np, propnames[3], NULL); 580 if (bsizep == NULL) 581 bsizep = lsizep; 582 if (lsizep == NULL) 583 lsizep = bsizep; 584 if (lsizep != NULL) 585 lsize = be32_to_cpu(*lsizep); 586 if (bsizep != NULL) 587 bsize = be32_to_cpu(*bsizep); 588 if (sizep == NULL || bsizep == NULL || lsizep == NULL) 589 success = false; 590 591 /* 592 * OF is weird .. it represents fully associative caches 593 * as "1 way" which doesn't make much sense and doesn't 594 * leave room for direct mapped. We'll assume that 0 595 * in OF means direct mapped for that reason. 596 */ 597 if (sets == 1) 598 sets = 0; 599 else if (sets == 0) 600 sets = 1; 601 602 init_cache_info(info, size, lsize, bsize, sets); 603 604 return success; 605 } 606 607 void __init initialize_cache_info(void) 608 { 609 struct device_node *cpu = NULL, *l2, *l3 = NULL; 610 u32 pvr; 611 612 /* 613 * All shipping POWER8 machines have a firmware bug that 614 * puts incorrect information in the device-tree. This will 615 * be (hopefully) fixed for future chips but for now hard 616 * code the values if we are running on one of these 617 */ 618 pvr = PVR_VER(mfspr(SPRN_PVR)); 619 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E || 620 pvr == PVR_POWER8NVL) { 621 /* size lsize blk sets */ 622 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32); 623 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64); 624 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512); 625 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); 626 } else 627 cpu = of_find_node_by_type(NULL, "cpu"); 628 629 /* 630 * We're assuming *all* of the CPUs have the same 631 * d-cache and i-cache sizes... -Peter 632 */ 633 if (cpu) { 634 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d)) 635 pr_warn("Argh, can't find dcache properties !\n"); 636 637 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i)) 638 pr_warn("Argh, can't find icache properties !\n"); 639 640 /* 641 * Try to find the L2 and L3 if any. Assume they are 642 * unified and use the D-side properties. 643 */ 644 l2 = of_find_next_cache_node(cpu); 645 of_node_put(cpu); 646 if (l2) { 647 parse_cache_info(l2, false, &ppc64_caches.l2); 648 l3 = of_find_next_cache_node(l2); 649 of_node_put(l2); 650 } 651 if (l3) { 652 parse_cache_info(l3, false, &ppc64_caches.l3); 653 of_node_put(l3); 654 } 655 } 656 657 /* For use by binfmt_elf */ 658 dcache_bsize = ppc64_caches.l1d.block_size; 659 icache_bsize = ppc64_caches.l1i.block_size; 660 661 cur_cpu_spec->dcache_bsize = dcache_bsize; 662 cur_cpu_spec->icache_bsize = icache_bsize; 663 } 664 665 /* 666 * This returns the limit below which memory accesses to the linear 667 * mapping are guarnateed not to cause an architectural exception (e.g., 668 * TLB or SLB miss fault). 669 * 670 * This is used to allocate PACAs and various interrupt stacks that 671 * that are accessed early in interrupt handlers that must not cause 672 * re-entrant interrupts. 673 */ 674 __init u64 ppc64_bolted_size(void) 675 { 676 #ifdef CONFIG_PPC_BOOK3E 677 /* Freescale BookE bolts the entire linear mapping */ 678 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */ 679 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 680 return linear_map_top; 681 /* Other BookE, we assume the first GB is bolted */ 682 return 1ul << 30; 683 #else 684 /* BookS radix, does not take faults on linear mapping */ 685 if (early_radix_enabled()) 686 return ULONG_MAX; 687 688 /* BookS hash, the first segment is bolted */ 689 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT)) 690 return 1UL << SID_SHIFT_1T; 691 return 1UL << SID_SHIFT; 692 #endif 693 } 694 695 static void *__init alloc_stack(unsigned long limit, int cpu) 696 { 697 void *ptr; 698 699 BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16); 700 701 ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_ALIGN, 702 MEMBLOCK_LOW_LIMIT, limit, 703 early_cpu_to_node(cpu)); 704 if (!ptr) 705 panic("cannot allocate stacks"); 706 707 return ptr; 708 } 709 710 void __init irqstack_early_init(void) 711 { 712 u64 limit = ppc64_bolted_size(); 713 unsigned int i; 714 715 /* 716 * Interrupt stacks must be in the first segment since we 717 * cannot afford to take SLB misses on them. They are not 718 * accessed in realmode. 719 */ 720 for_each_possible_cpu(i) { 721 softirq_ctx[i] = alloc_stack(limit, i); 722 hardirq_ctx[i] = alloc_stack(limit, i); 723 } 724 } 725 726 #ifdef CONFIG_PPC_BOOK3E 727 void __init exc_lvl_early_init(void) 728 { 729 unsigned int i; 730 731 for_each_possible_cpu(i) { 732 void *sp; 733 734 sp = alloc_stack(ULONG_MAX, i); 735 critirq_ctx[i] = sp; 736 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE; 737 738 sp = alloc_stack(ULONG_MAX, i); 739 dbgirq_ctx[i] = sp; 740 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE; 741 742 sp = alloc_stack(ULONG_MAX, i); 743 mcheckirq_ctx[i] = sp; 744 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE; 745 } 746 747 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 748 patch_exception(0x040, exc_debug_debug_book3e); 749 } 750 #endif 751 752 /* 753 * Stack space used when we detect a bad kernel stack pointer, and 754 * early in SMP boots before relocation is enabled. Exclusive emergency 755 * stack for machine checks. 756 */ 757 void __init emergency_stack_init(void) 758 { 759 u64 limit, mce_limit; 760 unsigned int i; 761 762 /* 763 * Emergency stacks must be under 256MB, we cannot afford to take 764 * SLB misses on them. The ABI also requires them to be 128-byte 765 * aligned. 766 * 767 * Since we use these as temporary stacks during secondary CPU 768 * bringup, machine check, system reset, and HMI, we need to get 769 * at them in real mode. This means they must also be within the RMO 770 * region. 771 * 772 * The IRQ stacks allocated elsewhere in this file are zeroed and 773 * initialized in kernel/irq.c. These are initialized here in order 774 * to have emergency stacks available as early as possible. 775 */ 776 limit = mce_limit = min(ppc64_bolted_size(), ppc64_rma_size); 777 778 /* 779 * Machine check on pseries calls rtas, but can't use the static 780 * rtas_args due to a machine check hitting while the lock is held. 781 * rtas args have to be under 4GB, so the machine check stack is 782 * limited to 4GB so args can be put on stack. 783 */ 784 if (firmware_has_feature(FW_FEATURE_LPAR) && mce_limit > SZ_4G) 785 mce_limit = SZ_4G; 786 787 for_each_possible_cpu(i) { 788 paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE; 789 790 #ifdef CONFIG_PPC_BOOK3S_64 791 /* emergency stack for NMI exception handling. */ 792 paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE; 793 794 /* emergency stack for machine check exception handling. */ 795 paca_ptrs[i]->mc_emergency_sp = alloc_stack(mce_limit, i) + THREAD_SIZE; 796 #endif 797 } 798 } 799 800 #ifdef CONFIG_SMP 801 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 802 { 803 if (early_cpu_to_node(from) == early_cpu_to_node(to)) 804 return LOCAL_DISTANCE; 805 else 806 return REMOTE_DISTANCE; 807 } 808 809 static __init int pcpu_cpu_to_node(int cpu) 810 { 811 return early_cpu_to_node(cpu); 812 } 813 814 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 815 EXPORT_SYMBOL(__per_cpu_offset); 816 817 void __init setup_per_cpu_areas(void) 818 { 819 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 820 size_t atom_size; 821 unsigned long delta; 822 unsigned int cpu; 823 int rc = -EINVAL; 824 825 /* 826 * BookE and BookS radix are historical values and should be revisited. 827 */ 828 if (IS_ENABLED(CONFIG_PPC_BOOK3E)) { 829 atom_size = SZ_1M; 830 } else if (radix_enabled()) { 831 atom_size = PAGE_SIZE; 832 } else if (IS_ENABLED(CONFIG_PPC_64S_HASH_MMU)) { 833 /* 834 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 835 * to group units. For larger mappings, use 1M atom which 836 * should be large enough to contain a number of units. 837 */ 838 if (mmu_linear_psize == MMU_PAGE_4K) 839 atom_size = PAGE_SIZE; 840 else 841 atom_size = SZ_1M; 842 } 843 844 if (pcpu_chosen_fc != PCPU_FC_PAGE) { 845 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 846 pcpu_cpu_to_node); 847 if (rc) 848 pr_warn("PERCPU: %s allocator failed (%d), " 849 "falling back to page size\n", 850 pcpu_fc_names[pcpu_chosen_fc], rc); 851 } 852 853 if (rc < 0) 854 rc = pcpu_page_first_chunk(0, pcpu_cpu_to_node); 855 if (rc < 0) 856 panic("cannot initialize percpu area (err=%d)", rc); 857 858 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 859 for_each_possible_cpu(cpu) { 860 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 861 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu]; 862 } 863 } 864 #endif 865 866 #ifdef CONFIG_MEMORY_HOTPLUG 867 unsigned long memory_block_size_bytes(void) 868 { 869 if (ppc_md.memory_block_size) 870 return ppc_md.memory_block_size(); 871 872 return MIN_MEMORY_BLOCK_SIZE; 873 } 874 #endif 875 876 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 877 struct ppc_pci_io ppc_pci_io; 878 EXPORT_SYMBOL(ppc_pci_io); 879 #endif 880 881 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF 882 u64 hw_nmi_get_sample_period(int watchdog_thresh) 883 { 884 return ppc_proc_freq * watchdog_thresh; 885 } 886 #endif 887 888 /* 889 * The perf based hardlockup detector breaks PMU event based branches, so 890 * disable it by default. Book3S has a soft-nmi hardlockup detector based 891 * on the decrementer interrupt, so it does not suffer from this problem. 892 * 893 * It is likely to get false positives in KVM guests, so disable it there 894 * by default too. PowerVM will not stop or arbitrarily oversubscribe 895 * CPUs, but give a minimum regular allotment even with SPLPAR, so enable 896 * the detector for non-KVM guests, assume PowerVM. 897 */ 898 static int __init disable_hardlockup_detector(void) 899 { 900 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF 901 hardlockup_detector_disable(); 902 #else 903 if (firmware_has_feature(FW_FEATURE_LPAR)) { 904 if (is_kvm_guest()) 905 hardlockup_detector_disable(); 906 } 907 #endif 908 909 return 0; 910 } 911 early_initcall(disable_hardlockup_detector); 912