1 /* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/export.h> 14 #include <linux/string.h> 15 #include <linux/sched.h> 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/reboot.h> 19 #include <linux/delay.h> 20 #include <linux/initrd.h> 21 #include <linux/seq_file.h> 22 #include <linux/ioport.h> 23 #include <linux/console.h> 24 #include <linux/utsname.h> 25 #include <linux/tty.h> 26 #include <linux/root_dev.h> 27 #include <linux/notifier.h> 28 #include <linux/cpu.h> 29 #include <linux/unistd.h> 30 #include <linux/serial.h> 31 #include <linux/serial_8250.h> 32 #include <linux/bootmem.h> 33 #include <linux/pci.h> 34 #include <linux/lockdep.h> 35 #include <linux/memblock.h> 36 #include <linux/memory.h> 37 #include <linux/nmi.h> 38 39 #include <asm/debugfs.h> 40 #include <asm/io.h> 41 #include <asm/kdump.h> 42 #include <asm/prom.h> 43 #include <asm/processor.h> 44 #include <asm/pgtable.h> 45 #include <asm/smp.h> 46 #include <asm/elf.h> 47 #include <asm/machdep.h> 48 #include <asm/paca.h> 49 #include <asm/time.h> 50 #include <asm/cputable.h> 51 #include <asm/dt_cpu_ftrs.h> 52 #include <asm/sections.h> 53 #include <asm/btext.h> 54 #include <asm/nvram.h> 55 #include <asm/setup.h> 56 #include <asm/rtas.h> 57 #include <asm/iommu.h> 58 #include <asm/serial.h> 59 #include <asm/cache.h> 60 #include <asm/page.h> 61 #include <asm/mmu.h> 62 #include <asm/firmware.h> 63 #include <asm/xmon.h> 64 #include <asm/udbg.h> 65 #include <asm/kexec.h> 66 #include <asm/code-patching.h> 67 #include <asm/livepatch.h> 68 #include <asm/opal.h> 69 #include <asm/cputhreads.h> 70 #include <asm/hw_irq.h> 71 72 #include "setup.h" 73 74 #ifdef DEBUG 75 #define DBG(fmt...) udbg_printf(fmt) 76 #else 77 #define DBG(fmt...) 78 #endif 79 80 int spinning_secondaries; 81 u64 ppc64_pft_size; 82 83 struct ppc64_caches ppc64_caches = { 84 .l1d = { 85 .block_size = 0x40, 86 .log_block_size = 6, 87 }, 88 .l1i = { 89 .block_size = 0x40, 90 .log_block_size = 6 91 }, 92 }; 93 EXPORT_SYMBOL_GPL(ppc64_caches); 94 95 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 96 void __init setup_tlb_core_data(void) 97 { 98 int cpu; 99 100 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 101 102 for_each_possible_cpu(cpu) { 103 int first = cpu_first_thread_sibling(cpu); 104 105 /* 106 * If we boot via kdump on a non-primary thread, 107 * make sure we point at the thread that actually 108 * set up this TLB. 109 */ 110 if (cpu_first_thread_sibling(boot_cpuid) == first) 111 first = boot_cpuid; 112 113 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; 114 115 /* 116 * If we have threads, we need either tlbsrx. 117 * or e6500 tablewalk mode, or else TLB handlers 118 * will be racy and could produce duplicate entries. 119 * Should we panic instead? 120 */ 121 WARN_ONCE(smt_enabled_at_boot >= 2 && 122 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 123 book3e_htw_mode != PPC_HTW_E6500, 124 "%s: unsupported MMU configuration\n", __func__); 125 } 126 } 127 #endif 128 129 #ifdef CONFIG_SMP 130 131 static char *smt_enabled_cmdline; 132 133 /* Look for ibm,smt-enabled OF option */ 134 void __init check_smt_enabled(void) 135 { 136 struct device_node *dn; 137 const char *smt_option; 138 139 /* Default to enabling all threads */ 140 smt_enabled_at_boot = threads_per_core; 141 142 /* Allow the command line to overrule the OF option */ 143 if (smt_enabled_cmdline) { 144 if (!strcmp(smt_enabled_cmdline, "on")) 145 smt_enabled_at_boot = threads_per_core; 146 else if (!strcmp(smt_enabled_cmdline, "off")) 147 smt_enabled_at_boot = 0; 148 else { 149 int smt; 150 int rc; 151 152 rc = kstrtoint(smt_enabled_cmdline, 10, &smt); 153 if (!rc) 154 smt_enabled_at_boot = 155 min(threads_per_core, smt); 156 } 157 } else { 158 dn = of_find_node_by_path("/options"); 159 if (dn) { 160 smt_option = of_get_property(dn, "ibm,smt-enabled", 161 NULL); 162 163 if (smt_option) { 164 if (!strcmp(smt_option, "on")) 165 smt_enabled_at_boot = threads_per_core; 166 else if (!strcmp(smt_option, "off")) 167 smt_enabled_at_boot = 0; 168 } 169 170 of_node_put(dn); 171 } 172 } 173 } 174 175 /* Look for smt-enabled= cmdline option */ 176 static int __init early_smt_enabled(char *p) 177 { 178 smt_enabled_cmdline = p; 179 return 0; 180 } 181 early_param("smt-enabled", early_smt_enabled); 182 183 #endif /* CONFIG_SMP */ 184 185 /** Fix up paca fields required for the boot cpu */ 186 static void __init fixup_boot_paca(void) 187 { 188 /* The boot cpu is started */ 189 get_paca()->cpu_start = 1; 190 /* Allow percpu accesses to work until we setup percpu data */ 191 get_paca()->data_offset = 0; 192 /* Mark interrupts disabled in PACA */ 193 irq_soft_mask_set(IRQS_DISABLED); 194 } 195 196 static void __init configure_exceptions(void) 197 { 198 /* 199 * Setup the trampolines from the lowmem exception vectors 200 * to the kdump kernel when not using a relocatable kernel. 201 */ 202 setup_kdump_trampoline(); 203 204 /* Under a PAPR hypervisor, we need hypercalls */ 205 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 206 /* Enable AIL if possible */ 207 pseries_enable_reloc_on_exc(); 208 209 /* 210 * Tell the hypervisor that we want our exceptions to 211 * be taken in little endian mode. 212 * 213 * We don't call this for big endian as our calling convention 214 * makes us always enter in BE, and the call may fail under 215 * some circumstances with kdump. 216 */ 217 #ifdef __LITTLE_ENDIAN__ 218 pseries_little_endian_exceptions(); 219 #endif 220 } else { 221 /* Set endian mode using OPAL */ 222 if (firmware_has_feature(FW_FEATURE_OPAL)) 223 opal_configure_cores(); 224 225 /* AIL on native is done in cpu_ready_for_interrupts() */ 226 } 227 } 228 229 static void cpu_ready_for_interrupts(void) 230 { 231 /* 232 * Enable AIL if supported, and we are in hypervisor mode. This 233 * is called once for every processor. 234 * 235 * If we are not in hypervisor mode the job is done once for 236 * the whole partition in configure_exceptions(). 237 */ 238 if (cpu_has_feature(CPU_FTR_HVMODE) && 239 cpu_has_feature(CPU_FTR_ARCH_207S)) { 240 unsigned long lpcr = mfspr(SPRN_LPCR); 241 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); 242 } 243 244 /* 245 * Fixup HFSCR:TM based on CPU features. The bit is set by our 246 * early asm init because at that point we haven't updated our 247 * CPU features from firmware and device-tree. Here we have, 248 * so let's do it. 249 */ 250 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP)) 251 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM); 252 253 /* Set IR and DR in PACA MSR */ 254 get_paca()->kernel_msr = MSR_KERNEL; 255 } 256 257 unsigned long spr_default_dscr = 0; 258 259 void __init record_spr_defaults(void) 260 { 261 if (early_cpu_has_feature(CPU_FTR_DSCR)) 262 spr_default_dscr = mfspr(SPRN_DSCR); 263 } 264 265 /* 266 * Early initialization entry point. This is called by head.S 267 * with MMU translation disabled. We rely on the "feature" of 268 * the CPU that ignores the top 2 bits of the address in real 269 * mode so we can access kernel globals normally provided we 270 * only toy with things in the RMO region. From here, we do 271 * some early parsing of the device-tree to setup out MEMBLOCK 272 * data structures, and allocate & initialize the hash table 273 * and segment tables so we can start running with translation 274 * enabled. 275 * 276 * It is this function which will call the probe() callback of 277 * the various platform types and copy the matching one to the 278 * global ppc_md structure. Your platform can eventually do 279 * some very early initializations from the probe() routine, but 280 * this is not recommended, be very careful as, for example, the 281 * device-tree is not accessible via normal means at this point. 282 */ 283 284 void __init early_setup(unsigned long dt_ptr) 285 { 286 static __initdata struct paca_struct boot_paca; 287 288 /* -------- printk is _NOT_ safe to use here ! ------- */ 289 290 /* Try new device tree based feature discovery ... */ 291 if (!dt_cpu_ftrs_init(__va(dt_ptr))) 292 /* Otherwise use the old style CPU table */ 293 identify_cpu(0, mfspr(SPRN_PVR)); 294 295 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 296 initialise_paca(&boot_paca, 0); 297 setup_paca(&boot_paca); 298 fixup_boot_paca(); 299 300 /* -------- printk is now safe to use ------- */ 301 302 /* Enable early debugging if any specified (see udbg.h) */ 303 udbg_early_init(); 304 305 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 306 307 /* 308 * Do early initialization using the flattened device 309 * tree, such as retrieving the physical memory map or 310 * calculating/retrieving the hash table size. 311 */ 312 early_init_devtree(__va(dt_ptr)); 313 314 /* Now we know the logical id of our boot cpu, setup the paca. */ 315 if (boot_cpuid != 0) { 316 /* Poison paca_ptrs[0] again if it's not the boot cpu */ 317 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0])); 318 } 319 setup_paca(paca_ptrs[boot_cpuid]); 320 fixup_boot_paca(); 321 322 /* 323 * Configure exception handlers. This include setting up trampolines 324 * if needed, setting exception endian mode, etc... 325 */ 326 configure_exceptions(); 327 328 /* Apply all the dynamic patching */ 329 apply_feature_fixups(); 330 setup_feature_keys(); 331 332 /* Initialize the hash table or TLB handling */ 333 early_init_mmu(); 334 335 /* 336 * After firmware and early platform setup code has set things up, 337 * we note the SPR values for configurable control/performance 338 * registers, and use those as initial defaults. 339 */ 340 record_spr_defaults(); 341 342 /* 343 * At this point, we can let interrupts switch to virtual mode 344 * (the MMU has been setup), so adjust the MSR in the PACA to 345 * have IR and DR set and enable AIL if it exists 346 */ 347 cpu_ready_for_interrupts(); 348 349 /* 350 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it 351 * will only actually get enabled on the boot cpu much later once 352 * ftrace itself has been initialized. 353 */ 354 this_cpu_enable_ftrace(); 355 356 DBG(" <- early_setup()\n"); 357 358 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 359 /* 360 * This needs to be done *last* (after the above DBG() even) 361 * 362 * Right after we return from this function, we turn on the MMU 363 * which means the real-mode access trick that btext does will 364 * no longer work, it needs to switch to using a real MMU 365 * mapping. This call will ensure that it does 366 */ 367 btext_map(); 368 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 369 } 370 371 #ifdef CONFIG_SMP 372 void early_setup_secondary(void) 373 { 374 /* Mark interrupts disabled in PACA */ 375 irq_soft_mask_set(IRQS_DISABLED); 376 377 /* Initialize the hash table or TLB handling */ 378 early_init_mmu_secondary(); 379 380 /* 381 * At this point, we can let interrupts switch to virtual mode 382 * (the MMU has been setup), so adjust the MSR in the PACA to 383 * have IR and DR set. 384 */ 385 cpu_ready_for_interrupts(); 386 } 387 388 #endif /* CONFIG_SMP */ 389 390 void panic_smp_self_stop(void) 391 { 392 hard_irq_disable(); 393 spin_begin(); 394 while (1) 395 spin_cpu_relax(); 396 } 397 398 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 399 static bool use_spinloop(void) 400 { 401 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) { 402 /* 403 * See comments in head_64.S -- not all platforms insert 404 * secondaries at __secondary_hold and wait at the spin 405 * loop. 406 */ 407 if (firmware_has_feature(FW_FEATURE_OPAL)) 408 return false; 409 return true; 410 } 411 412 /* 413 * When book3e boots from kexec, the ePAPR spin table does 414 * not get used. 415 */ 416 return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); 417 } 418 419 void smp_release_cpus(void) 420 { 421 unsigned long *ptr; 422 int i; 423 424 if (!use_spinloop()) 425 return; 426 427 DBG(" -> smp_release_cpus()\n"); 428 429 /* All secondary cpus are spinning on a common spinloop, release them 430 * all now so they can start to spin on their individual paca 431 * spinloops. For non SMP kernels, the secondary cpus never get out 432 * of the common spinloop. 433 */ 434 435 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 436 - PHYSICAL_START); 437 *ptr = ppc_function_entry(generic_secondary_smp_init); 438 439 /* And wait a bit for them to catch up */ 440 for (i = 0; i < 100000; i++) { 441 mb(); 442 HMT_low(); 443 if (spinning_secondaries == 0) 444 break; 445 udelay(1); 446 } 447 DBG("spinning_secondaries = %d\n", spinning_secondaries); 448 449 DBG(" <- smp_release_cpus()\n"); 450 } 451 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */ 452 453 /* 454 * Initialize some remaining members of the ppc64_caches and systemcfg 455 * structures 456 * (at least until we get rid of them completely). This is mostly some 457 * cache informations about the CPU that will be used by cache flush 458 * routines and/or provided to userland 459 */ 460 461 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize, 462 u32 bsize, u32 sets) 463 { 464 info->size = size; 465 info->sets = sets; 466 info->line_size = lsize; 467 info->block_size = bsize; 468 info->log_block_size = __ilog2(bsize); 469 if (bsize) 470 info->blocks_per_page = PAGE_SIZE / bsize; 471 else 472 info->blocks_per_page = 0; 473 474 if (sets == 0) 475 info->assoc = 0xffff; 476 else 477 info->assoc = size / (sets * lsize); 478 } 479 480 static bool __init parse_cache_info(struct device_node *np, 481 bool icache, 482 struct ppc_cache_info *info) 483 { 484 static const char *ipropnames[] __initdata = { 485 "i-cache-size", 486 "i-cache-sets", 487 "i-cache-block-size", 488 "i-cache-line-size", 489 }; 490 static const char *dpropnames[] __initdata = { 491 "d-cache-size", 492 "d-cache-sets", 493 "d-cache-block-size", 494 "d-cache-line-size", 495 }; 496 const char **propnames = icache ? ipropnames : dpropnames; 497 const __be32 *sizep, *lsizep, *bsizep, *setsp; 498 u32 size, lsize, bsize, sets; 499 bool success = true; 500 501 size = 0; 502 sets = -1u; 503 lsize = bsize = cur_cpu_spec->dcache_bsize; 504 sizep = of_get_property(np, propnames[0], NULL); 505 if (sizep != NULL) 506 size = be32_to_cpu(*sizep); 507 setsp = of_get_property(np, propnames[1], NULL); 508 if (setsp != NULL) 509 sets = be32_to_cpu(*setsp); 510 bsizep = of_get_property(np, propnames[2], NULL); 511 lsizep = of_get_property(np, propnames[3], NULL); 512 if (bsizep == NULL) 513 bsizep = lsizep; 514 if (lsizep != NULL) 515 lsize = be32_to_cpu(*lsizep); 516 if (bsizep != NULL) 517 bsize = be32_to_cpu(*bsizep); 518 if (sizep == NULL || bsizep == NULL || lsizep == NULL) 519 success = false; 520 521 /* 522 * OF is weird .. it represents fully associative caches 523 * as "1 way" which doesn't make much sense and doesn't 524 * leave room for direct mapped. We'll assume that 0 525 * in OF means direct mapped for that reason. 526 */ 527 if (sets == 1) 528 sets = 0; 529 else if (sets == 0) 530 sets = 1; 531 532 init_cache_info(info, size, lsize, bsize, sets); 533 534 return success; 535 } 536 537 void __init initialize_cache_info(void) 538 { 539 struct device_node *cpu = NULL, *l2, *l3 = NULL; 540 u32 pvr; 541 542 DBG(" -> initialize_cache_info()\n"); 543 544 /* 545 * All shipping POWER8 machines have a firmware bug that 546 * puts incorrect information in the device-tree. This will 547 * be (hopefully) fixed for future chips but for now hard 548 * code the values if we are running on one of these 549 */ 550 pvr = PVR_VER(mfspr(SPRN_PVR)); 551 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E || 552 pvr == PVR_POWER8NVL) { 553 /* size lsize blk sets */ 554 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32); 555 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64); 556 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512); 557 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); 558 } else 559 cpu = of_find_node_by_type(NULL, "cpu"); 560 561 /* 562 * We're assuming *all* of the CPUs have the same 563 * d-cache and i-cache sizes... -Peter 564 */ 565 if (cpu) { 566 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d)) 567 DBG("Argh, can't find dcache properties !\n"); 568 569 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i)) 570 DBG("Argh, can't find icache properties !\n"); 571 572 /* 573 * Try to find the L2 and L3 if any. Assume they are 574 * unified and use the D-side properties. 575 */ 576 l2 = of_find_next_cache_node(cpu); 577 of_node_put(cpu); 578 if (l2) { 579 parse_cache_info(l2, false, &ppc64_caches.l2); 580 l3 = of_find_next_cache_node(l2); 581 of_node_put(l2); 582 } 583 if (l3) { 584 parse_cache_info(l3, false, &ppc64_caches.l3); 585 of_node_put(l3); 586 } 587 } 588 589 /* For use by binfmt_elf */ 590 dcache_bsize = ppc64_caches.l1d.block_size; 591 icache_bsize = ppc64_caches.l1i.block_size; 592 593 cur_cpu_spec->dcache_bsize = dcache_bsize; 594 cur_cpu_spec->icache_bsize = icache_bsize; 595 596 DBG(" <- initialize_cache_info()\n"); 597 } 598 599 /* 600 * This returns the limit below which memory accesses to the linear 601 * mapping are guarnateed not to cause an architectural exception (e.g., 602 * TLB or SLB miss fault). 603 * 604 * This is used to allocate PACAs and various interrupt stacks that 605 * that are accessed early in interrupt handlers that must not cause 606 * re-entrant interrupts. 607 */ 608 __init u64 ppc64_bolted_size(void) 609 { 610 #ifdef CONFIG_PPC_BOOK3E 611 /* Freescale BookE bolts the entire linear mapping */ 612 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */ 613 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 614 return linear_map_top; 615 /* Other BookE, we assume the first GB is bolted */ 616 return 1ul << 30; 617 #else 618 /* BookS radix, does not take faults on linear mapping */ 619 if (early_radix_enabled()) 620 return ULONG_MAX; 621 622 /* BookS hash, the first segment is bolted */ 623 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT)) 624 return 1UL << SID_SHIFT_1T; 625 return 1UL << SID_SHIFT; 626 #endif 627 } 628 629 static void *__init alloc_stack(unsigned long limit, int cpu) 630 { 631 unsigned long pa; 632 633 pa = memblock_alloc_base_nid(THREAD_SIZE, THREAD_SIZE, limit, 634 early_cpu_to_node(cpu), MEMBLOCK_NONE); 635 if (!pa) { 636 pa = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 637 if (!pa) 638 panic("cannot allocate stacks"); 639 } 640 641 return __va(pa); 642 } 643 644 void __init irqstack_early_init(void) 645 { 646 u64 limit = ppc64_bolted_size(); 647 unsigned int i; 648 649 /* 650 * Interrupt stacks must be in the first segment since we 651 * cannot afford to take SLB misses on them. They are not 652 * accessed in realmode. 653 */ 654 for_each_possible_cpu(i) { 655 softirq_ctx[i] = alloc_stack(limit, i); 656 hardirq_ctx[i] = alloc_stack(limit, i); 657 } 658 } 659 660 #ifdef CONFIG_PPC_BOOK3E 661 void __init exc_lvl_early_init(void) 662 { 663 unsigned int i; 664 665 for_each_possible_cpu(i) { 666 void *sp; 667 668 sp = alloc_stack(ULONG_MAX, i); 669 critirq_ctx[i] = sp; 670 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE; 671 672 sp = alloc_stack(ULONG_MAX, i); 673 dbgirq_ctx[i] = sp; 674 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE; 675 676 sp = alloc_stack(ULONG_MAX, i); 677 mcheckirq_ctx[i] = sp; 678 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE; 679 } 680 681 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 682 patch_exception(0x040, exc_debug_debug_book3e); 683 } 684 #endif 685 686 /* 687 * Emergency stacks are used for a range of things, from asynchronous 688 * NMIs (system reset, machine check) to synchronous, process context. 689 * We set preempt_count to zero, even though that isn't necessarily correct. To 690 * get the right value we'd need to copy it from the previous thread_info, but 691 * doing that might fault causing more problems. 692 * TODO: what to do with accounting? 693 */ 694 static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu) 695 { 696 ti->task = NULL; 697 ti->cpu = cpu; 698 ti->preempt_count = 0; 699 ti->local_flags = 0; 700 ti->flags = 0; 701 klp_init_thread_info(ti); 702 } 703 704 /* 705 * Stack space used when we detect a bad kernel stack pointer, and 706 * early in SMP boots before relocation is enabled. Exclusive emergency 707 * stack for machine checks. 708 */ 709 void __init emergency_stack_init(void) 710 { 711 u64 limit; 712 unsigned int i; 713 714 /* 715 * Emergency stacks must be under 256MB, we cannot afford to take 716 * SLB misses on them. The ABI also requires them to be 128-byte 717 * aligned. 718 * 719 * Since we use these as temporary stacks during secondary CPU 720 * bringup, machine check, system reset, and HMI, we need to get 721 * at them in real mode. This means they must also be within the RMO 722 * region. 723 * 724 * The IRQ stacks allocated elsewhere in this file are zeroed and 725 * initialized in kernel/irq.c. These are initialized here in order 726 * to have emergency stacks available as early as possible. 727 */ 728 limit = min(ppc64_bolted_size(), ppc64_rma_size); 729 730 for_each_possible_cpu(i) { 731 struct thread_info *ti; 732 733 ti = alloc_stack(limit, i); 734 memset(ti, 0, THREAD_SIZE); 735 emerg_stack_init_thread_info(ti, i); 736 paca_ptrs[i]->emergency_sp = (void *)ti + THREAD_SIZE; 737 738 #ifdef CONFIG_PPC_BOOK3S_64 739 /* emergency stack for NMI exception handling. */ 740 ti = alloc_stack(limit, i); 741 memset(ti, 0, THREAD_SIZE); 742 emerg_stack_init_thread_info(ti, i); 743 paca_ptrs[i]->nmi_emergency_sp = (void *)ti + THREAD_SIZE; 744 745 /* emergency stack for machine check exception handling. */ 746 ti = alloc_stack(limit, i); 747 memset(ti, 0, THREAD_SIZE); 748 emerg_stack_init_thread_info(ti, i); 749 paca_ptrs[i]->mc_emergency_sp = (void *)ti + THREAD_SIZE; 750 #endif 751 } 752 } 753 754 #ifdef CONFIG_SMP 755 #define PCPU_DYN_SIZE () 756 757 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 758 { 759 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align, 760 __pa(MAX_DMA_ADDRESS)); 761 } 762 763 static void __init pcpu_fc_free(void *ptr, size_t size) 764 { 765 free_bootmem(__pa(ptr), size); 766 } 767 768 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 769 { 770 if (early_cpu_to_node(from) == early_cpu_to_node(to)) 771 return LOCAL_DISTANCE; 772 else 773 return REMOTE_DISTANCE; 774 } 775 776 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 777 EXPORT_SYMBOL(__per_cpu_offset); 778 779 void __init setup_per_cpu_areas(void) 780 { 781 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 782 size_t atom_size; 783 unsigned long delta; 784 unsigned int cpu; 785 int rc; 786 787 /* 788 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 789 * to group units. For larger mappings, use 1M atom which 790 * should be large enough to contain a number of units. 791 */ 792 if (mmu_linear_psize == MMU_PAGE_4K) 793 atom_size = PAGE_SIZE; 794 else 795 atom_size = 1 << 20; 796 797 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 798 pcpu_fc_alloc, pcpu_fc_free); 799 if (rc < 0) 800 panic("cannot initialize percpu area (err=%d)", rc); 801 802 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 803 for_each_possible_cpu(cpu) { 804 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 805 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu]; 806 } 807 } 808 #endif 809 810 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 811 unsigned long memory_block_size_bytes(void) 812 { 813 if (ppc_md.memory_block_size) 814 return ppc_md.memory_block_size(); 815 816 return MIN_MEMORY_BLOCK_SIZE; 817 } 818 #endif 819 820 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 821 struct ppc_pci_io ppc_pci_io; 822 EXPORT_SYMBOL(ppc_pci_io); 823 #endif 824 825 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF 826 u64 hw_nmi_get_sample_period(int watchdog_thresh) 827 { 828 return ppc_proc_freq * watchdog_thresh; 829 } 830 #endif 831 832 /* 833 * The perf based hardlockup detector breaks PMU event based branches, so 834 * disable it by default. Book3S has a soft-nmi hardlockup detector based 835 * on the decrementer interrupt, so it does not suffer from this problem. 836 * 837 * It is likely to get false positives in VM guests, so disable it there 838 * by default too. 839 */ 840 static int __init disable_hardlockup_detector(void) 841 { 842 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF 843 hardlockup_detector_disable(); 844 #else 845 if (firmware_has_feature(FW_FEATURE_LPAR)) 846 hardlockup_detector_disable(); 847 #endif 848 849 return 0; 850 } 851 early_initcall(disable_hardlockup_detector); 852 853 #ifdef CONFIG_PPC_BOOK3S_64 854 static enum l1d_flush_type enabled_flush_types; 855 static void *l1d_flush_fallback_area; 856 static bool no_rfi_flush; 857 bool rfi_flush; 858 859 static int __init handle_no_rfi_flush(char *p) 860 { 861 pr_info("rfi-flush: disabled on command line."); 862 no_rfi_flush = true; 863 return 0; 864 } 865 early_param("no_rfi_flush", handle_no_rfi_flush); 866 867 /* 868 * The RFI flush is not KPTI, but because users will see doco that says to use 869 * nopti we hijack that option here to also disable the RFI flush. 870 */ 871 static int __init handle_no_pti(char *p) 872 { 873 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n"); 874 handle_no_rfi_flush(NULL); 875 return 0; 876 } 877 early_param("nopti", handle_no_pti); 878 879 static void do_nothing(void *unused) 880 { 881 /* 882 * We don't need to do the flush explicitly, just enter+exit kernel is 883 * sufficient, the RFI exit handlers will do the right thing. 884 */ 885 } 886 887 void rfi_flush_enable(bool enable) 888 { 889 if (enable) { 890 do_rfi_flush_fixups(enabled_flush_types); 891 on_each_cpu(do_nothing, NULL, 1); 892 } else 893 do_rfi_flush_fixups(L1D_FLUSH_NONE); 894 895 rfi_flush = enable; 896 } 897 898 static void __ref init_fallback_flush(void) 899 { 900 u64 l1d_size, limit; 901 int cpu; 902 903 /* Only allocate the fallback flush area once (at boot time). */ 904 if (l1d_flush_fallback_area) 905 return; 906 907 l1d_size = ppc64_caches.l1d.size; 908 909 /* 910 * If there is no d-cache-size property in the device tree, l1d_size 911 * could be zero. That leads to the loop in the asm wrapping around to 912 * 2^64-1, and then walking off the end of the fallback area and 913 * eventually causing a page fault which is fatal. Just default to 914 * something vaguely sane. 915 */ 916 if (!l1d_size) 917 l1d_size = (64 * 1024); 918 919 limit = min(ppc64_bolted_size(), ppc64_rma_size); 920 921 /* 922 * Align to L1d size, and size it at 2x L1d size, to catch possible 923 * hardware prefetch runoff. We don't have a recipe for load patterns to 924 * reliably avoid the prefetcher. 925 */ 926 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit)); 927 memset(l1d_flush_fallback_area, 0, l1d_size * 2); 928 929 for_each_possible_cpu(cpu) { 930 struct paca_struct *paca = paca_ptrs[cpu]; 931 paca->rfi_flush_fallback_area = l1d_flush_fallback_area; 932 paca->l1d_flush_size = l1d_size; 933 } 934 } 935 936 void setup_rfi_flush(enum l1d_flush_type types, bool enable) 937 { 938 if (types & L1D_FLUSH_FALLBACK) { 939 pr_info("rfi-flush: fallback displacement flush available\n"); 940 init_fallback_flush(); 941 } 942 943 if (types & L1D_FLUSH_ORI) 944 pr_info("rfi-flush: ori type flush available\n"); 945 946 if (types & L1D_FLUSH_MTTRIG) 947 pr_info("rfi-flush: mttrig type flush available\n"); 948 949 enabled_flush_types = types; 950 951 if (!no_rfi_flush) 952 rfi_flush_enable(enable); 953 } 954 955 #ifdef CONFIG_DEBUG_FS 956 static int rfi_flush_set(void *data, u64 val) 957 { 958 bool enable; 959 960 if (val == 1) 961 enable = true; 962 else if (val == 0) 963 enable = false; 964 else 965 return -EINVAL; 966 967 /* Only do anything if we're changing state */ 968 if (enable != rfi_flush) 969 rfi_flush_enable(enable); 970 971 return 0; 972 } 973 974 static int rfi_flush_get(void *data, u64 *val) 975 { 976 *val = rfi_flush ? 1 : 0; 977 return 0; 978 } 979 980 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n"); 981 982 static __init int rfi_flush_debugfs_init(void) 983 { 984 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush); 985 return 0; 986 } 987 device_initcall(rfi_flush_debugfs_init); 988 #endif 989 #endif /* CONFIG_PPC_BOOK3S_64 */ 990