1 /* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #define DEBUG 14 15 #include <linux/export.h> 16 #include <linux/string.h> 17 #include <linux/sched.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/reboot.h> 21 #include <linux/delay.h> 22 #include <linux/initrd.h> 23 #include <linux/seq_file.h> 24 #include <linux/ioport.h> 25 #include <linux/console.h> 26 #include <linux/utsname.h> 27 #include <linux/tty.h> 28 #include <linux/root_dev.h> 29 #include <linux/notifier.h> 30 #include <linux/cpu.h> 31 #include <linux/unistd.h> 32 #include <linux/serial.h> 33 #include <linux/serial_8250.h> 34 #include <linux/bootmem.h> 35 #include <linux/pci.h> 36 #include <linux/lockdep.h> 37 #include <linux/memblock.h> 38 #include <linux/hugetlb.h> 39 #include <linux/memory.h> 40 #include <linux/nmi.h> 41 42 #include <asm/io.h> 43 #include <asm/kdump.h> 44 #include <asm/prom.h> 45 #include <asm/processor.h> 46 #include <asm/pgtable.h> 47 #include <asm/smp.h> 48 #include <asm/elf.h> 49 #include <asm/machdep.h> 50 #include <asm/paca.h> 51 #include <asm/time.h> 52 #include <asm/cputable.h> 53 #include <asm/sections.h> 54 #include <asm/btext.h> 55 #include <asm/nvram.h> 56 #include <asm/setup.h> 57 #include <asm/rtas.h> 58 #include <asm/iommu.h> 59 #include <asm/serial.h> 60 #include <asm/cache.h> 61 #include <asm/page.h> 62 #include <asm/mmu.h> 63 #include <asm/firmware.h> 64 #include <asm/xmon.h> 65 #include <asm/udbg.h> 66 #include <asm/kexec.h> 67 #include <asm/mmu_context.h> 68 #include <asm/code-patching.h> 69 #include <asm/kvm_ppc.h> 70 #include <asm/hugetlb.h> 71 #include <asm/epapr_hcalls.h> 72 73 #ifdef DEBUG 74 #define DBG(fmt...) udbg_printf(fmt) 75 #else 76 #define DBG(fmt...) 77 #endif 78 79 int spinning_secondaries; 80 u64 ppc64_pft_size; 81 82 /* Pick defaults since we might want to patch instructions 83 * before we've read this from the device tree. 84 */ 85 struct ppc64_caches ppc64_caches = { 86 .dline_size = 0x40, 87 .log_dline_size = 6, 88 .iline_size = 0x40, 89 .log_iline_size = 6 90 }; 91 EXPORT_SYMBOL_GPL(ppc64_caches); 92 93 /* 94 * These are used in binfmt_elf.c to put aux entries on the stack 95 * for each elf executable being started. 96 */ 97 int dcache_bsize; 98 int icache_bsize; 99 int ucache_bsize; 100 101 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 102 static void setup_tlb_core_data(void) 103 { 104 int cpu; 105 106 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 107 108 for_each_possible_cpu(cpu) { 109 int first = cpu_first_thread_sibling(cpu); 110 111 /* 112 * If we boot via kdump on a non-primary thread, 113 * make sure we point at the thread that actually 114 * set up this TLB. 115 */ 116 if (cpu_first_thread_sibling(boot_cpuid) == first) 117 first = boot_cpuid; 118 119 paca[cpu].tcd_ptr = &paca[first].tcd; 120 121 /* 122 * If we have threads, we need either tlbsrx. 123 * or e6500 tablewalk mode, or else TLB handlers 124 * will be racy and could produce duplicate entries. 125 */ 126 if (smt_enabled_at_boot >= 2 && 127 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 128 book3e_htw_mode != PPC_HTW_E6500) { 129 /* Should we panic instead? */ 130 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", 131 __func__); 132 } 133 } 134 } 135 #else 136 static void setup_tlb_core_data(void) 137 { 138 } 139 #endif 140 141 #ifdef CONFIG_SMP 142 143 static char *smt_enabled_cmdline; 144 145 /* Look for ibm,smt-enabled OF option */ 146 static void check_smt_enabled(void) 147 { 148 struct device_node *dn; 149 const char *smt_option; 150 151 /* Default to enabling all threads */ 152 smt_enabled_at_boot = threads_per_core; 153 154 /* Allow the command line to overrule the OF option */ 155 if (smt_enabled_cmdline) { 156 if (!strcmp(smt_enabled_cmdline, "on")) 157 smt_enabled_at_boot = threads_per_core; 158 else if (!strcmp(smt_enabled_cmdline, "off")) 159 smt_enabled_at_boot = 0; 160 else { 161 int smt; 162 int rc; 163 164 rc = kstrtoint(smt_enabled_cmdline, 10, &smt); 165 if (!rc) 166 smt_enabled_at_boot = 167 min(threads_per_core, smt); 168 } 169 } else { 170 dn = of_find_node_by_path("/options"); 171 if (dn) { 172 smt_option = of_get_property(dn, "ibm,smt-enabled", 173 NULL); 174 175 if (smt_option) { 176 if (!strcmp(smt_option, "on")) 177 smt_enabled_at_boot = threads_per_core; 178 else if (!strcmp(smt_option, "off")) 179 smt_enabled_at_boot = 0; 180 } 181 182 of_node_put(dn); 183 } 184 } 185 } 186 187 /* Look for smt-enabled= cmdline option */ 188 static int __init early_smt_enabled(char *p) 189 { 190 smt_enabled_cmdline = p; 191 return 0; 192 } 193 early_param("smt-enabled", early_smt_enabled); 194 195 #else 196 #define check_smt_enabled() 197 #endif /* CONFIG_SMP */ 198 199 /** Fix up paca fields required for the boot cpu */ 200 static void fixup_boot_paca(void) 201 { 202 /* The boot cpu is started */ 203 get_paca()->cpu_start = 1; 204 /* Allow percpu accesses to work until we setup percpu data */ 205 get_paca()->data_offset = 0; 206 } 207 208 static void cpu_ready_for_interrupts(void) 209 { 210 /* Set IR and DR in PACA MSR */ 211 get_paca()->kernel_msr = MSR_KERNEL; 212 213 /* 214 * Enable AIL if supported, and we are in hypervisor mode. If we are 215 * not in hypervisor mode, we enable relocation-on interrupts later 216 * in pSeries_setup_arch() using the H_SET_MODE hcall. 217 */ 218 if (cpu_has_feature(CPU_FTR_HVMODE) && 219 cpu_has_feature(CPU_FTR_ARCH_207S)) { 220 unsigned long lpcr = mfspr(SPRN_LPCR); 221 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); 222 } 223 } 224 225 /* 226 * Early initialization entry point. This is called by head.S 227 * with MMU translation disabled. We rely on the "feature" of 228 * the CPU that ignores the top 2 bits of the address in real 229 * mode so we can access kernel globals normally provided we 230 * only toy with things in the RMO region. From here, we do 231 * some early parsing of the device-tree to setup out MEMBLOCK 232 * data structures, and allocate & initialize the hash table 233 * and segment tables so we can start running with translation 234 * enabled. 235 * 236 * It is this function which will call the probe() callback of 237 * the various platform types and copy the matching one to the 238 * global ppc_md structure. Your platform can eventually do 239 * some very early initializations from the probe() routine, but 240 * this is not recommended, be very careful as, for example, the 241 * device-tree is not accessible via normal means at this point. 242 */ 243 244 void __init early_setup(unsigned long dt_ptr) 245 { 246 static __initdata struct paca_struct boot_paca; 247 248 /* -------- printk is _NOT_ safe to use here ! ------- */ 249 250 /* Identify CPU type */ 251 identify_cpu(0, mfspr(SPRN_PVR)); 252 253 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 254 initialise_paca(&boot_paca, 0); 255 setup_paca(&boot_paca); 256 fixup_boot_paca(); 257 258 /* Initialize lockdep early or else spinlocks will blow */ 259 lockdep_init(); 260 261 /* -------- printk is now safe to use ------- */ 262 263 /* Enable early debugging if any specified (see udbg.h) */ 264 udbg_early_init(); 265 266 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 267 268 /* 269 * Do early initialization using the flattened device 270 * tree, such as retrieving the physical memory map or 271 * calculating/retrieving the hash table size. 272 */ 273 early_init_devtree(__va(dt_ptr)); 274 275 epapr_paravirt_early_init(); 276 277 /* Now we know the logical id of our boot cpu, setup the paca. */ 278 setup_paca(&paca[boot_cpuid]); 279 fixup_boot_paca(); 280 281 /* Probe the machine type */ 282 probe_machine(); 283 284 setup_kdump_trampoline(); 285 286 DBG("Found, Initializing memory management...\n"); 287 288 /* Initialize the hash table or TLB handling */ 289 early_init_mmu(); 290 291 /* 292 * At this point, we can let interrupts switch to virtual mode 293 * (the MMU has been setup), so adjust the MSR in the PACA to 294 * have IR and DR set and enable AIL if it exists 295 */ 296 cpu_ready_for_interrupts(); 297 298 /* Reserve large chunks of memory for use by CMA for KVM */ 299 kvm_cma_reserve(); 300 301 /* 302 * Reserve any gigantic pages requested on the command line. 303 * memblock needs to have been initialized by the time this is 304 * called since this will reserve memory. 305 */ 306 reserve_hugetlb_gpages(); 307 308 DBG(" <- early_setup()\n"); 309 310 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 311 /* 312 * This needs to be done *last* (after the above DBG() even) 313 * 314 * Right after we return from this function, we turn on the MMU 315 * which means the real-mode access trick that btext does will 316 * no longer work, it needs to switch to using a real MMU 317 * mapping. This call will ensure that it does 318 */ 319 btext_map(); 320 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 321 } 322 323 #ifdef CONFIG_SMP 324 void early_setup_secondary(void) 325 { 326 /* Mark interrupts enabled in PACA */ 327 get_paca()->soft_enabled = 0; 328 329 /* Initialize the hash table or TLB handling */ 330 early_init_mmu_secondary(); 331 332 /* 333 * At this point, we can let interrupts switch to virtual mode 334 * (the MMU has been setup), so adjust the MSR in the PACA to 335 * have IR and DR set. 336 */ 337 cpu_ready_for_interrupts(); 338 } 339 340 #endif /* CONFIG_SMP */ 341 342 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 343 static bool use_spinloop(void) 344 { 345 if (!IS_ENABLED(CONFIG_PPC_BOOK3E)) 346 return true; 347 348 /* 349 * When book3e boots from kexec, the ePAPR spin table does 350 * not get used. 351 */ 352 return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); 353 } 354 355 void smp_release_cpus(void) 356 { 357 unsigned long *ptr; 358 int i; 359 360 if (!use_spinloop()) 361 return; 362 363 DBG(" -> smp_release_cpus()\n"); 364 365 /* All secondary cpus are spinning on a common spinloop, release them 366 * all now so they can start to spin on their individual paca 367 * spinloops. For non SMP kernels, the secondary cpus never get out 368 * of the common spinloop. 369 */ 370 371 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 372 - PHYSICAL_START); 373 *ptr = ppc_function_entry(generic_secondary_smp_init); 374 375 /* And wait a bit for them to catch up */ 376 for (i = 0; i < 100000; i++) { 377 mb(); 378 HMT_low(); 379 if (spinning_secondaries == 0) 380 break; 381 udelay(1); 382 } 383 DBG("spinning_secondaries = %d\n", spinning_secondaries); 384 385 DBG(" <- smp_release_cpus()\n"); 386 } 387 #endif /* CONFIG_SMP || CONFIG_KEXEC */ 388 389 /* 390 * Initialize some remaining members of the ppc64_caches and systemcfg 391 * structures 392 * (at least until we get rid of them completely). This is mostly some 393 * cache informations about the CPU that will be used by cache flush 394 * routines and/or provided to userland 395 */ 396 static void __init initialize_cache_info(void) 397 { 398 struct device_node *np; 399 unsigned long num_cpus = 0; 400 401 DBG(" -> initialize_cache_info()\n"); 402 403 for_each_node_by_type(np, "cpu") { 404 num_cpus += 1; 405 406 /* 407 * We're assuming *all* of the CPUs have the same 408 * d-cache and i-cache sizes... -Peter 409 */ 410 if (num_cpus == 1) { 411 const __be32 *sizep, *lsizep; 412 u32 size, lsize; 413 414 size = 0; 415 lsize = cur_cpu_spec->dcache_bsize; 416 sizep = of_get_property(np, "d-cache-size", NULL); 417 if (sizep != NULL) 418 size = be32_to_cpu(*sizep); 419 lsizep = of_get_property(np, "d-cache-block-size", 420 NULL); 421 /* fallback if block size missing */ 422 if (lsizep == NULL) 423 lsizep = of_get_property(np, 424 "d-cache-line-size", 425 NULL); 426 if (lsizep != NULL) 427 lsize = be32_to_cpu(*lsizep); 428 if (sizep == NULL || lsizep == NULL) 429 DBG("Argh, can't find dcache properties ! " 430 "sizep: %p, lsizep: %p\n", sizep, lsizep); 431 432 ppc64_caches.dsize = size; 433 ppc64_caches.dline_size = lsize; 434 ppc64_caches.log_dline_size = __ilog2(lsize); 435 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 436 437 size = 0; 438 lsize = cur_cpu_spec->icache_bsize; 439 sizep = of_get_property(np, "i-cache-size", NULL); 440 if (sizep != NULL) 441 size = be32_to_cpu(*sizep); 442 lsizep = of_get_property(np, "i-cache-block-size", 443 NULL); 444 if (lsizep == NULL) 445 lsizep = of_get_property(np, 446 "i-cache-line-size", 447 NULL); 448 if (lsizep != NULL) 449 lsize = be32_to_cpu(*lsizep); 450 if (sizep == NULL || lsizep == NULL) 451 DBG("Argh, can't find icache properties ! " 452 "sizep: %p, lsizep: %p\n", sizep, lsizep); 453 454 ppc64_caches.isize = size; 455 ppc64_caches.iline_size = lsize; 456 ppc64_caches.log_iline_size = __ilog2(lsize); 457 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 458 } 459 } 460 461 DBG(" <- initialize_cache_info()\n"); 462 } 463 464 465 /* 466 * Do some initial setup of the system. The parameters are those which 467 * were passed in from the bootloader. 468 */ 469 void __init setup_system(void) 470 { 471 DBG(" -> setup_system()\n"); 472 473 /* Apply the CPUs-specific and firmware specific fixups to kernel 474 * text (nop out sections not relevant to this CPU or this firmware) 475 */ 476 do_feature_fixups(cur_cpu_spec->cpu_features, 477 &__start___ftr_fixup, &__stop___ftr_fixup); 478 do_feature_fixups(cur_cpu_spec->mmu_features, 479 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 480 do_feature_fixups(powerpc_firmware_features, 481 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 482 do_lwsync_fixups(cur_cpu_spec->cpu_features, 483 &__start___lwsync_fixup, &__stop___lwsync_fixup); 484 do_final_fixups(); 485 486 /* 487 * Unflatten the device-tree passed by prom_init or kexec 488 */ 489 unflatten_device_tree(); 490 491 /* 492 * Fill the ppc64_caches & systemcfg structures with informations 493 * retrieved from the device-tree. 494 */ 495 initialize_cache_info(); 496 497 #ifdef CONFIG_PPC_RTAS 498 /* 499 * Initialize RTAS if available 500 */ 501 rtas_initialize(); 502 #endif /* CONFIG_PPC_RTAS */ 503 504 /* 505 * Check if we have an initrd provided via the device-tree 506 */ 507 check_for_initrd(); 508 509 /* 510 * Do some platform specific early initializations, that includes 511 * setting up the hash table pointers. It also sets up some interrupt-mapping 512 * related options that will be used by finish_device_tree() 513 */ 514 if (ppc_md.init_early) 515 ppc_md.init_early(); 516 517 /* 518 * We can discover serial ports now since the above did setup the 519 * hash table management for us, thus ioremap works. We do that early 520 * so that further code can be debugged 521 */ 522 find_legacy_serial_ports(); 523 524 /* 525 * Register early console 526 */ 527 register_early_udbg_console(); 528 529 /* 530 * Initialize xmon 531 */ 532 xmon_setup(); 533 534 smp_setup_cpu_maps(); 535 check_smt_enabled(); 536 setup_tlb_core_data(); 537 538 /* 539 * Freescale Book3e parts spin in a loop provided by firmware, 540 * so smp_release_cpus() does nothing for them 541 */ 542 #if defined(CONFIG_SMP) 543 /* Release secondary cpus out of their spinloops at 0x60 now that 544 * we can map physical -> logical CPU ids 545 */ 546 smp_release_cpus(); 547 #endif 548 549 pr_info("Starting Linux %s %s\n", init_utsname()->machine, 550 init_utsname()->version); 551 552 pr_info("-----------------------------------------------------\n"); 553 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 554 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); 555 556 if (ppc64_caches.dline_size != 0x80) 557 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); 558 if (ppc64_caches.iline_size != 0x80) 559 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); 560 561 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); 562 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); 563 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); 564 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, 565 cur_cpu_spec->cpu_user_features2); 566 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); 567 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); 568 569 #ifdef CONFIG_PPC_STD_MMU_64 570 if (htab_address) 571 pr_info("htab_address = 0x%p\n", htab_address); 572 573 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 574 #endif 575 576 if (PHYSICAL_START > 0) 577 pr_info("physical_start = 0x%llx\n", 578 (unsigned long long)PHYSICAL_START); 579 pr_info("-----------------------------------------------------\n"); 580 581 DBG(" <- setup_system()\n"); 582 } 583 584 /* This returns the limit below which memory accesses to the linear 585 * mapping are guarnateed not to cause a TLB or SLB miss. This is 586 * used to allocate interrupt or emergency stacks for which our 587 * exception entry path doesn't deal with being interrupted. 588 */ 589 static u64 safe_stack_limit(void) 590 { 591 #ifdef CONFIG_PPC_BOOK3E 592 /* Freescale BookE bolts the entire linear mapping */ 593 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 594 return linear_map_top; 595 /* Other BookE, we assume the first GB is bolted */ 596 return 1ul << 30; 597 #else 598 /* BookS, the first segment is bolted */ 599 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 600 return 1UL << SID_SHIFT_1T; 601 return 1UL << SID_SHIFT; 602 #endif 603 } 604 605 static void __init irqstack_early_init(void) 606 { 607 u64 limit = safe_stack_limit(); 608 unsigned int i; 609 610 /* 611 * Interrupt stacks must be in the first segment since we 612 * cannot afford to take SLB misses on them. 613 */ 614 for_each_possible_cpu(i) { 615 softirq_ctx[i] = (struct thread_info *) 616 __va(memblock_alloc_base(THREAD_SIZE, 617 THREAD_SIZE, limit)); 618 hardirq_ctx[i] = (struct thread_info *) 619 __va(memblock_alloc_base(THREAD_SIZE, 620 THREAD_SIZE, limit)); 621 } 622 } 623 624 #ifdef CONFIG_PPC_BOOK3E 625 static void __init exc_lvl_early_init(void) 626 { 627 unsigned int i; 628 unsigned long sp; 629 630 for_each_possible_cpu(i) { 631 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 632 critirq_ctx[i] = (struct thread_info *)__va(sp); 633 paca[i].crit_kstack = __va(sp + THREAD_SIZE); 634 635 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 636 dbgirq_ctx[i] = (struct thread_info *)__va(sp); 637 paca[i].dbg_kstack = __va(sp + THREAD_SIZE); 638 639 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 640 mcheckirq_ctx[i] = (struct thread_info *)__va(sp); 641 paca[i].mc_kstack = __va(sp + THREAD_SIZE); 642 } 643 644 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 645 patch_exception(0x040, exc_debug_debug_book3e); 646 } 647 #else 648 #define exc_lvl_early_init() 649 #endif 650 651 /* 652 * Stack space used when we detect a bad kernel stack pointer, and 653 * early in SMP boots before relocation is enabled. Exclusive emergency 654 * stack for machine checks. 655 */ 656 static void __init emergency_stack_init(void) 657 { 658 u64 limit; 659 unsigned int i; 660 661 /* 662 * Emergency stacks must be under 256MB, we cannot afford to take 663 * SLB misses on them. The ABI also requires them to be 128-byte 664 * aligned. 665 * 666 * Since we use these as temporary stacks during secondary CPU 667 * bringup, we need to get at them in real mode. This means they 668 * must also be within the RMO region. 669 */ 670 limit = min(safe_stack_limit(), ppc64_rma_size); 671 672 for_each_possible_cpu(i) { 673 unsigned long sp; 674 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 675 sp += THREAD_SIZE; 676 paca[i].emergency_sp = __va(sp); 677 678 #ifdef CONFIG_PPC_BOOK3S_64 679 /* emergency stack for machine check exception handling. */ 680 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 681 sp += THREAD_SIZE; 682 paca[i].mc_emergency_sp = __va(sp); 683 #endif 684 } 685 } 686 687 /* 688 * Called into from start_kernel this initializes memblock, which is used 689 * to manage page allocation until mem_init is called. 690 */ 691 void __init setup_arch(char **cmdline_p) 692 { 693 *cmdline_p = boot_command_line; 694 695 /* 696 * Set cache line size based on type of cpu as a default. 697 * Systems with OF can look in the properties on the cpu node(s) 698 * for a possibly more accurate value. 699 */ 700 dcache_bsize = ppc64_caches.dline_size; 701 icache_bsize = ppc64_caches.iline_size; 702 703 if (ppc_md.panic) 704 setup_panic(); 705 706 init_mm.start_code = (unsigned long)_stext; 707 init_mm.end_code = (unsigned long) _etext; 708 init_mm.end_data = (unsigned long) _edata; 709 init_mm.brk = klimit; 710 #ifdef CONFIG_PPC_64K_PAGES 711 init_mm.context.pte_frag = NULL; 712 #endif 713 #ifdef CONFIG_SPAPR_TCE_IOMMU 714 mm_iommu_init(&init_mm.context); 715 #endif 716 irqstack_early_init(); 717 exc_lvl_early_init(); 718 emergency_stack_init(); 719 720 initmem_init(); 721 722 #ifdef CONFIG_DUMMY_CONSOLE 723 conswitchp = &dummy_con; 724 #endif 725 726 if (ppc_md.setup_arch) 727 ppc_md.setup_arch(); 728 729 paging_init(); 730 731 /* Initialize the MMU context management stuff */ 732 mmu_context_init(); 733 734 /* Interrupt code needs to be 64K-aligned */ 735 if ((unsigned long)_stext & 0xffff) 736 panic("Kernelbase not 64K-aligned (0x%lx)!\n", 737 (unsigned long)_stext); 738 } 739 740 #ifdef CONFIG_SMP 741 #define PCPU_DYN_SIZE () 742 743 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 744 { 745 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 746 __pa(MAX_DMA_ADDRESS)); 747 } 748 749 static void __init pcpu_fc_free(void *ptr, size_t size) 750 { 751 free_bootmem(__pa(ptr), size); 752 } 753 754 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 755 { 756 if (cpu_to_node(from) == cpu_to_node(to)) 757 return LOCAL_DISTANCE; 758 else 759 return REMOTE_DISTANCE; 760 } 761 762 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 763 EXPORT_SYMBOL(__per_cpu_offset); 764 765 void __init setup_per_cpu_areas(void) 766 { 767 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 768 size_t atom_size; 769 unsigned long delta; 770 unsigned int cpu; 771 int rc; 772 773 /* 774 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 775 * to group units. For larger mappings, use 1M atom which 776 * should be large enough to contain a number of units. 777 */ 778 if (mmu_linear_psize == MMU_PAGE_4K) 779 atom_size = PAGE_SIZE; 780 else 781 atom_size = 1 << 20; 782 783 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 784 pcpu_fc_alloc, pcpu_fc_free); 785 if (rc < 0) 786 panic("cannot initialize percpu area (err=%d)", rc); 787 788 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 789 for_each_possible_cpu(cpu) { 790 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 791 paca[cpu].data_offset = __per_cpu_offset[cpu]; 792 } 793 } 794 #endif 795 796 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 797 unsigned long memory_block_size_bytes(void) 798 { 799 if (ppc_md.memory_block_size) 800 return ppc_md.memory_block_size(); 801 802 return MIN_MEMORY_BLOCK_SIZE; 803 } 804 #endif 805 806 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 807 struct ppc_pci_io ppc_pci_io; 808 EXPORT_SYMBOL(ppc_pci_io); 809 #endif 810 811 #ifdef CONFIG_HARDLOCKUP_DETECTOR 812 u64 hw_nmi_get_sample_period(int watchdog_thresh) 813 { 814 return ppc_proc_freq * watchdog_thresh; 815 } 816 817 /* 818 * The hardlockup detector breaks PMU event based branches and is likely 819 * to get false positives in KVM guests, so disable it by default. 820 */ 821 static int __init disable_hardlockup_detector(void) 822 { 823 hardlockup_detector_disable(); 824 825 return 0; 826 } 827 early_initcall(disable_hardlockup_detector); 828 #endif 829