1 /* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #define DEBUG 14 15 #include <linux/export.h> 16 #include <linux/string.h> 17 #include <linux/sched.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/reboot.h> 21 #include <linux/delay.h> 22 #include <linux/initrd.h> 23 #include <linux/seq_file.h> 24 #include <linux/ioport.h> 25 #include <linux/console.h> 26 #include <linux/utsname.h> 27 #include <linux/tty.h> 28 #include <linux/root_dev.h> 29 #include <linux/notifier.h> 30 #include <linux/cpu.h> 31 #include <linux/unistd.h> 32 #include <linux/serial.h> 33 #include <linux/serial_8250.h> 34 #include <linux/bootmem.h> 35 #include <linux/pci.h> 36 #include <linux/lockdep.h> 37 #include <linux/memblock.h> 38 #include <linux/hugetlb.h> 39 #include <linux/memory.h> 40 41 #include <asm/io.h> 42 #include <asm/kdump.h> 43 #include <asm/prom.h> 44 #include <asm/processor.h> 45 #include <asm/pgtable.h> 46 #include <asm/smp.h> 47 #include <asm/elf.h> 48 #include <asm/machdep.h> 49 #include <asm/paca.h> 50 #include <asm/time.h> 51 #include <asm/cputable.h> 52 #include <asm/sections.h> 53 #include <asm/btext.h> 54 #include <asm/nvram.h> 55 #include <asm/setup.h> 56 #include <asm/rtas.h> 57 #include <asm/iommu.h> 58 #include <asm/serial.h> 59 #include <asm/cache.h> 60 #include <asm/page.h> 61 #include <asm/mmu.h> 62 #include <asm/firmware.h> 63 #include <asm/xmon.h> 64 #include <asm/udbg.h> 65 #include <asm/kexec.h> 66 #include <asm/mmu_context.h> 67 #include <asm/code-patching.h> 68 #include <asm/kvm_ppc.h> 69 #include <asm/hugetlb.h> 70 #include <asm/epapr_hcalls.h> 71 72 #ifdef DEBUG 73 #define DBG(fmt...) udbg_printf(fmt) 74 #else 75 #define DBG(fmt...) 76 #endif 77 78 int spinning_secondaries; 79 u64 ppc64_pft_size; 80 81 /* Pick defaults since we might want to patch instructions 82 * before we've read this from the device tree. 83 */ 84 struct ppc64_caches ppc64_caches = { 85 .dline_size = 0x40, 86 .log_dline_size = 6, 87 .iline_size = 0x40, 88 .log_iline_size = 6 89 }; 90 EXPORT_SYMBOL_GPL(ppc64_caches); 91 92 /* 93 * These are used in binfmt_elf.c to put aux entries on the stack 94 * for each elf executable being started. 95 */ 96 int dcache_bsize; 97 int icache_bsize; 98 int ucache_bsize; 99 100 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 101 static void setup_tlb_core_data(void) 102 { 103 int cpu; 104 105 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 106 107 for_each_possible_cpu(cpu) { 108 int first = cpu_first_thread_sibling(cpu); 109 110 paca[cpu].tcd_ptr = &paca[first].tcd; 111 112 /* 113 * If we have threads, we need either tlbsrx. 114 * or e6500 tablewalk mode, or else TLB handlers 115 * will be racy and could produce duplicate entries. 116 */ 117 if (smt_enabled_at_boot >= 2 && 118 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 119 book3e_htw_mode != PPC_HTW_E6500) { 120 /* Should we panic instead? */ 121 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", 122 __func__); 123 } 124 } 125 } 126 #else 127 static void setup_tlb_core_data(void) 128 { 129 } 130 #endif 131 132 #ifdef CONFIG_SMP 133 134 static char *smt_enabled_cmdline; 135 136 /* Look for ibm,smt-enabled OF option */ 137 static void check_smt_enabled(void) 138 { 139 struct device_node *dn; 140 const char *smt_option; 141 142 /* Default to enabling all threads */ 143 smt_enabled_at_boot = threads_per_core; 144 145 /* Allow the command line to overrule the OF option */ 146 if (smt_enabled_cmdline) { 147 if (!strcmp(smt_enabled_cmdline, "on")) 148 smt_enabled_at_boot = threads_per_core; 149 else if (!strcmp(smt_enabled_cmdline, "off")) 150 smt_enabled_at_boot = 0; 151 else { 152 int smt; 153 int rc; 154 155 rc = kstrtoint(smt_enabled_cmdline, 10, &smt); 156 if (!rc) 157 smt_enabled_at_boot = 158 min(threads_per_core, smt); 159 } 160 } else { 161 dn = of_find_node_by_path("/options"); 162 if (dn) { 163 smt_option = of_get_property(dn, "ibm,smt-enabled", 164 NULL); 165 166 if (smt_option) { 167 if (!strcmp(smt_option, "on")) 168 smt_enabled_at_boot = threads_per_core; 169 else if (!strcmp(smt_option, "off")) 170 smt_enabled_at_boot = 0; 171 } 172 173 of_node_put(dn); 174 } 175 } 176 } 177 178 /* Look for smt-enabled= cmdline option */ 179 static int __init early_smt_enabled(char *p) 180 { 181 smt_enabled_cmdline = p; 182 return 0; 183 } 184 early_param("smt-enabled", early_smt_enabled); 185 186 #else 187 #define check_smt_enabled() 188 #endif /* CONFIG_SMP */ 189 190 /** Fix up paca fields required for the boot cpu */ 191 static void fixup_boot_paca(void) 192 { 193 /* The boot cpu is started */ 194 get_paca()->cpu_start = 1; 195 /* Allow percpu accesses to work until we setup percpu data */ 196 get_paca()->data_offset = 0; 197 } 198 199 static void cpu_ready_for_interrupts(void) 200 { 201 /* Set IR and DR in PACA MSR */ 202 get_paca()->kernel_msr = MSR_KERNEL; 203 204 /* 205 * Enable AIL if supported, and we are in hypervisor mode. If we are 206 * not in hypervisor mode, we enable relocation-on interrupts later 207 * in pSeries_setup_arch() using the H_SET_MODE hcall. 208 */ 209 if (cpu_has_feature(CPU_FTR_HVMODE) && 210 cpu_has_feature(CPU_FTR_ARCH_207S)) { 211 unsigned long lpcr = mfspr(SPRN_LPCR); 212 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); 213 } 214 } 215 216 /* 217 * Early initialization entry point. This is called by head.S 218 * with MMU translation disabled. We rely on the "feature" of 219 * the CPU that ignores the top 2 bits of the address in real 220 * mode so we can access kernel globals normally provided we 221 * only toy with things in the RMO region. From here, we do 222 * some early parsing of the device-tree to setup out MEMBLOCK 223 * data structures, and allocate & initialize the hash table 224 * and segment tables so we can start running with translation 225 * enabled. 226 * 227 * It is this function which will call the probe() callback of 228 * the various platform types and copy the matching one to the 229 * global ppc_md structure. Your platform can eventually do 230 * some very early initializations from the probe() routine, but 231 * this is not recommended, be very careful as, for example, the 232 * device-tree is not accessible via normal means at this point. 233 */ 234 235 void __init early_setup(unsigned long dt_ptr) 236 { 237 static __initdata struct paca_struct boot_paca; 238 239 /* -------- printk is _NOT_ safe to use here ! ------- */ 240 241 /* Identify CPU type */ 242 identify_cpu(0, mfspr(SPRN_PVR)); 243 244 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 245 initialise_paca(&boot_paca, 0); 246 setup_paca(&boot_paca); 247 fixup_boot_paca(); 248 249 /* Initialize lockdep early or else spinlocks will blow */ 250 lockdep_init(); 251 252 /* -------- printk is now safe to use ------- */ 253 254 /* Enable early debugging if any specified (see udbg.h) */ 255 udbg_early_init(); 256 257 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 258 259 /* 260 * Do early initialization using the flattened device 261 * tree, such as retrieving the physical memory map or 262 * calculating/retrieving the hash table size. 263 */ 264 early_init_devtree(__va(dt_ptr)); 265 266 epapr_paravirt_early_init(); 267 268 /* Now we know the logical id of our boot cpu, setup the paca. */ 269 setup_paca(&paca[boot_cpuid]); 270 fixup_boot_paca(); 271 272 /* Probe the machine type */ 273 probe_machine(); 274 275 setup_kdump_trampoline(); 276 277 DBG("Found, Initializing memory management...\n"); 278 279 /* Initialize the hash table or TLB handling */ 280 early_init_mmu(); 281 282 /* 283 * At this point, we can let interrupts switch to virtual mode 284 * (the MMU has been setup), so adjust the MSR in the PACA to 285 * have IR and DR set and enable AIL if it exists 286 */ 287 cpu_ready_for_interrupts(); 288 289 /* Reserve large chunks of memory for use by CMA for KVM */ 290 kvm_cma_reserve(); 291 292 /* 293 * Reserve any gigantic pages requested on the command line. 294 * memblock needs to have been initialized by the time this is 295 * called since this will reserve memory. 296 */ 297 reserve_hugetlb_gpages(); 298 299 DBG(" <- early_setup()\n"); 300 301 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 302 /* 303 * This needs to be done *last* (after the above DBG() even) 304 * 305 * Right after we return from this function, we turn on the MMU 306 * which means the real-mode access trick that btext does will 307 * no longer work, it needs to switch to using a real MMU 308 * mapping. This call will ensure that it does 309 */ 310 btext_map(); 311 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 312 } 313 314 #ifdef CONFIG_SMP 315 void early_setup_secondary(void) 316 { 317 /* Mark interrupts enabled in PACA */ 318 get_paca()->soft_enabled = 0; 319 320 /* Initialize the hash table or TLB handling */ 321 early_init_mmu_secondary(); 322 323 /* 324 * At this point, we can let interrupts switch to virtual mode 325 * (the MMU has been setup), so adjust the MSR in the PACA to 326 * have IR and DR set. 327 */ 328 cpu_ready_for_interrupts(); 329 } 330 331 #endif /* CONFIG_SMP */ 332 333 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 334 void smp_release_cpus(void) 335 { 336 unsigned long *ptr; 337 int i; 338 339 DBG(" -> smp_release_cpus()\n"); 340 341 /* All secondary cpus are spinning on a common spinloop, release them 342 * all now so they can start to spin on their individual paca 343 * spinloops. For non SMP kernels, the secondary cpus never get out 344 * of the common spinloop. 345 */ 346 347 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 348 - PHYSICAL_START); 349 *ptr = ppc_function_entry(generic_secondary_smp_init); 350 351 /* And wait a bit for them to catch up */ 352 for (i = 0; i < 100000; i++) { 353 mb(); 354 HMT_low(); 355 if (spinning_secondaries == 0) 356 break; 357 udelay(1); 358 } 359 DBG("spinning_secondaries = %d\n", spinning_secondaries); 360 361 DBG(" <- smp_release_cpus()\n"); 362 } 363 #endif /* CONFIG_SMP || CONFIG_KEXEC */ 364 365 /* 366 * Initialize some remaining members of the ppc64_caches and systemcfg 367 * structures 368 * (at least until we get rid of them completely). This is mostly some 369 * cache informations about the CPU that will be used by cache flush 370 * routines and/or provided to userland 371 */ 372 static void __init initialize_cache_info(void) 373 { 374 struct device_node *np; 375 unsigned long num_cpus = 0; 376 377 DBG(" -> initialize_cache_info()\n"); 378 379 for_each_node_by_type(np, "cpu") { 380 num_cpus += 1; 381 382 /* 383 * We're assuming *all* of the CPUs have the same 384 * d-cache and i-cache sizes... -Peter 385 */ 386 if (num_cpus == 1) { 387 const __be32 *sizep, *lsizep; 388 u32 size, lsize; 389 390 size = 0; 391 lsize = cur_cpu_spec->dcache_bsize; 392 sizep = of_get_property(np, "d-cache-size", NULL); 393 if (sizep != NULL) 394 size = be32_to_cpu(*sizep); 395 lsizep = of_get_property(np, "d-cache-block-size", 396 NULL); 397 /* fallback if block size missing */ 398 if (lsizep == NULL) 399 lsizep = of_get_property(np, 400 "d-cache-line-size", 401 NULL); 402 if (lsizep != NULL) 403 lsize = be32_to_cpu(*lsizep); 404 if (sizep == NULL || lsizep == NULL) 405 DBG("Argh, can't find dcache properties ! " 406 "sizep: %p, lsizep: %p\n", sizep, lsizep); 407 408 ppc64_caches.dsize = size; 409 ppc64_caches.dline_size = lsize; 410 ppc64_caches.log_dline_size = __ilog2(lsize); 411 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 412 413 size = 0; 414 lsize = cur_cpu_spec->icache_bsize; 415 sizep = of_get_property(np, "i-cache-size", NULL); 416 if (sizep != NULL) 417 size = be32_to_cpu(*sizep); 418 lsizep = of_get_property(np, "i-cache-block-size", 419 NULL); 420 if (lsizep == NULL) 421 lsizep = of_get_property(np, 422 "i-cache-line-size", 423 NULL); 424 if (lsizep != NULL) 425 lsize = be32_to_cpu(*lsizep); 426 if (sizep == NULL || lsizep == NULL) 427 DBG("Argh, can't find icache properties ! " 428 "sizep: %p, lsizep: %p\n", sizep, lsizep); 429 430 ppc64_caches.isize = size; 431 ppc64_caches.iline_size = lsize; 432 ppc64_caches.log_iline_size = __ilog2(lsize); 433 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 434 } 435 } 436 437 DBG(" <- initialize_cache_info()\n"); 438 } 439 440 441 /* 442 * Do some initial setup of the system. The parameters are those which 443 * were passed in from the bootloader. 444 */ 445 void __init setup_system(void) 446 { 447 DBG(" -> setup_system()\n"); 448 449 /* Apply the CPUs-specific and firmware specific fixups to kernel 450 * text (nop out sections not relevant to this CPU or this firmware) 451 */ 452 do_feature_fixups(cur_cpu_spec->cpu_features, 453 &__start___ftr_fixup, &__stop___ftr_fixup); 454 do_feature_fixups(cur_cpu_spec->mmu_features, 455 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 456 do_feature_fixups(powerpc_firmware_features, 457 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 458 do_lwsync_fixups(cur_cpu_spec->cpu_features, 459 &__start___lwsync_fixup, &__stop___lwsync_fixup); 460 do_final_fixups(); 461 462 /* 463 * Unflatten the device-tree passed by prom_init or kexec 464 */ 465 unflatten_device_tree(); 466 467 /* 468 * Fill the ppc64_caches & systemcfg structures with informations 469 * retrieved from the device-tree. 470 */ 471 initialize_cache_info(); 472 473 #ifdef CONFIG_PPC_RTAS 474 /* 475 * Initialize RTAS if available 476 */ 477 rtas_initialize(); 478 #endif /* CONFIG_PPC_RTAS */ 479 480 /* 481 * Check if we have an initrd provided via the device-tree 482 */ 483 check_for_initrd(); 484 485 /* 486 * Do some platform specific early initializations, that includes 487 * setting up the hash table pointers. It also sets up some interrupt-mapping 488 * related options that will be used by finish_device_tree() 489 */ 490 if (ppc_md.init_early) 491 ppc_md.init_early(); 492 493 /* 494 * We can discover serial ports now since the above did setup the 495 * hash table management for us, thus ioremap works. We do that early 496 * so that further code can be debugged 497 */ 498 find_legacy_serial_ports(); 499 500 /* 501 * Register early console 502 */ 503 register_early_udbg_console(); 504 505 /* 506 * Initialize xmon 507 */ 508 xmon_setup(); 509 510 smp_setup_cpu_maps(); 511 check_smt_enabled(); 512 setup_tlb_core_data(); 513 514 /* 515 * Freescale Book3e parts spin in a loop provided by firmware, 516 * so smp_release_cpus() does nothing for them 517 */ 518 #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_FSL_BOOK3E) 519 /* Release secondary cpus out of their spinloops at 0x60 now that 520 * we can map physical -> logical CPU ids 521 */ 522 smp_release_cpus(); 523 #endif 524 525 pr_info("Starting Linux PPC64 %s\n", init_utsname()->version); 526 527 pr_info("-----------------------------------------------------\n"); 528 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 529 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); 530 531 if (ppc64_caches.dline_size != 0x80) 532 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); 533 if (ppc64_caches.iline_size != 0x80) 534 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); 535 536 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); 537 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); 538 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); 539 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, 540 cur_cpu_spec->cpu_user_features2); 541 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); 542 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); 543 544 #ifdef CONFIG_PPC_STD_MMU_64 545 if (htab_address) 546 pr_info("htab_address = 0x%p\n", htab_address); 547 548 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 549 #endif 550 551 if (PHYSICAL_START > 0) 552 pr_info("physical_start = 0x%llx\n", 553 (unsigned long long)PHYSICAL_START); 554 pr_info("-----------------------------------------------------\n"); 555 556 DBG(" <- setup_system()\n"); 557 } 558 559 /* This returns the limit below which memory accesses to the linear 560 * mapping are guarnateed not to cause a TLB or SLB miss. This is 561 * used to allocate interrupt or emergency stacks for which our 562 * exception entry path doesn't deal with being interrupted. 563 */ 564 static u64 safe_stack_limit(void) 565 { 566 #ifdef CONFIG_PPC_BOOK3E 567 /* Freescale BookE bolts the entire linear mapping */ 568 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 569 return linear_map_top; 570 /* Other BookE, we assume the first GB is bolted */ 571 return 1ul << 30; 572 #else 573 /* BookS, the first segment is bolted */ 574 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 575 return 1UL << SID_SHIFT_1T; 576 return 1UL << SID_SHIFT; 577 #endif 578 } 579 580 static void __init irqstack_early_init(void) 581 { 582 u64 limit = safe_stack_limit(); 583 unsigned int i; 584 585 /* 586 * Interrupt stacks must be in the first segment since we 587 * cannot afford to take SLB misses on them. 588 */ 589 for_each_possible_cpu(i) { 590 softirq_ctx[i] = (struct thread_info *) 591 __va(memblock_alloc_base(THREAD_SIZE, 592 THREAD_SIZE, limit)); 593 hardirq_ctx[i] = (struct thread_info *) 594 __va(memblock_alloc_base(THREAD_SIZE, 595 THREAD_SIZE, limit)); 596 } 597 } 598 599 #ifdef CONFIG_PPC_BOOK3E 600 static void __init exc_lvl_early_init(void) 601 { 602 unsigned int i; 603 unsigned long sp; 604 605 for_each_possible_cpu(i) { 606 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 607 critirq_ctx[i] = (struct thread_info *)__va(sp); 608 paca[i].crit_kstack = __va(sp + THREAD_SIZE); 609 610 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 611 dbgirq_ctx[i] = (struct thread_info *)__va(sp); 612 paca[i].dbg_kstack = __va(sp + THREAD_SIZE); 613 614 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 615 mcheckirq_ctx[i] = (struct thread_info *)__va(sp); 616 paca[i].mc_kstack = __va(sp + THREAD_SIZE); 617 } 618 619 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 620 patch_exception(0x040, exc_debug_debug_book3e); 621 } 622 #else 623 #define exc_lvl_early_init() 624 #endif 625 626 /* 627 * Stack space used when we detect a bad kernel stack pointer, and 628 * early in SMP boots before relocation is enabled. Exclusive emergency 629 * stack for machine checks. 630 */ 631 static void __init emergency_stack_init(void) 632 { 633 u64 limit; 634 unsigned int i; 635 636 /* 637 * Emergency stacks must be under 256MB, we cannot afford to take 638 * SLB misses on them. The ABI also requires them to be 128-byte 639 * aligned. 640 * 641 * Since we use these as temporary stacks during secondary CPU 642 * bringup, we need to get at them in real mode. This means they 643 * must also be within the RMO region. 644 */ 645 limit = min(safe_stack_limit(), ppc64_rma_size); 646 647 for_each_possible_cpu(i) { 648 unsigned long sp; 649 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 650 sp += THREAD_SIZE; 651 paca[i].emergency_sp = __va(sp); 652 653 #ifdef CONFIG_PPC_BOOK3S_64 654 /* emergency stack for machine check exception handling. */ 655 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 656 sp += THREAD_SIZE; 657 paca[i].mc_emergency_sp = __va(sp); 658 #endif 659 } 660 } 661 662 /* 663 * Called into from start_kernel this initializes memblock, which is used 664 * to manage page allocation until mem_init is called. 665 */ 666 void __init setup_arch(char **cmdline_p) 667 { 668 *cmdline_p = boot_command_line; 669 670 /* 671 * Set cache line size based on type of cpu as a default. 672 * Systems with OF can look in the properties on the cpu node(s) 673 * for a possibly more accurate value. 674 */ 675 dcache_bsize = ppc64_caches.dline_size; 676 icache_bsize = ppc64_caches.iline_size; 677 678 if (ppc_md.panic) 679 setup_panic(); 680 681 init_mm.start_code = (unsigned long)_stext; 682 init_mm.end_code = (unsigned long) _etext; 683 init_mm.end_data = (unsigned long) _edata; 684 init_mm.brk = klimit; 685 #ifdef CONFIG_PPC_64K_PAGES 686 init_mm.context.pte_frag = NULL; 687 #endif 688 irqstack_early_init(); 689 exc_lvl_early_init(); 690 emergency_stack_init(); 691 692 initmem_init(); 693 694 #ifdef CONFIG_DUMMY_CONSOLE 695 conswitchp = &dummy_con; 696 #endif 697 698 if (ppc_md.setup_arch) 699 ppc_md.setup_arch(); 700 701 paging_init(); 702 703 /* Initialize the MMU context management stuff */ 704 mmu_context_init(); 705 706 /* Interrupt code needs to be 64K-aligned */ 707 if ((unsigned long)_stext & 0xffff) 708 panic("Kernelbase not 64K-aligned (0x%lx)!\n", 709 (unsigned long)_stext); 710 } 711 712 #ifdef CONFIG_SMP 713 #define PCPU_DYN_SIZE () 714 715 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 716 { 717 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 718 __pa(MAX_DMA_ADDRESS)); 719 } 720 721 static void __init pcpu_fc_free(void *ptr, size_t size) 722 { 723 free_bootmem(__pa(ptr), size); 724 } 725 726 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 727 { 728 if (cpu_to_node(from) == cpu_to_node(to)) 729 return LOCAL_DISTANCE; 730 else 731 return REMOTE_DISTANCE; 732 } 733 734 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 735 EXPORT_SYMBOL(__per_cpu_offset); 736 737 void __init setup_per_cpu_areas(void) 738 { 739 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 740 size_t atom_size; 741 unsigned long delta; 742 unsigned int cpu; 743 int rc; 744 745 /* 746 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 747 * to group units. For larger mappings, use 1M atom which 748 * should be large enough to contain a number of units. 749 */ 750 if (mmu_linear_psize == MMU_PAGE_4K) 751 atom_size = PAGE_SIZE; 752 else 753 atom_size = 1 << 20; 754 755 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 756 pcpu_fc_alloc, pcpu_fc_free); 757 if (rc < 0) 758 panic("cannot initialize percpu area (err=%d)", rc); 759 760 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 761 for_each_possible_cpu(cpu) { 762 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 763 paca[cpu].data_offset = __per_cpu_offset[cpu]; 764 } 765 } 766 #endif 767 768 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 769 unsigned long memory_block_size_bytes(void) 770 { 771 if (ppc_md.memory_block_size) 772 return ppc_md.memory_block_size(); 773 774 return MIN_MEMORY_BLOCK_SIZE; 775 } 776 #endif 777 778 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 779 struct ppc_pci_io ppc_pci_io; 780 EXPORT_SYMBOL(ppc_pci_io); 781 #endif 782