1 /* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #define DEBUG 14 15 #include <linux/export.h> 16 #include <linux/string.h> 17 #include <linux/sched.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/reboot.h> 21 #include <linux/delay.h> 22 #include <linux/initrd.h> 23 #include <linux/seq_file.h> 24 #include <linux/ioport.h> 25 #include <linux/console.h> 26 #include <linux/utsname.h> 27 #include <linux/tty.h> 28 #include <linux/root_dev.h> 29 #include <linux/notifier.h> 30 #include <linux/cpu.h> 31 #include <linux/unistd.h> 32 #include <linux/serial.h> 33 #include <linux/serial_8250.h> 34 #include <linux/bootmem.h> 35 #include <linux/pci.h> 36 #include <linux/lockdep.h> 37 #include <linux/memblock.h> 38 #include <linux/hugetlb.h> 39 #include <linux/memory.h> 40 #include <linux/nmi.h> 41 42 #include <asm/io.h> 43 #include <asm/kdump.h> 44 #include <asm/prom.h> 45 #include <asm/processor.h> 46 #include <asm/pgtable.h> 47 #include <asm/smp.h> 48 #include <asm/elf.h> 49 #include <asm/machdep.h> 50 #include <asm/paca.h> 51 #include <asm/time.h> 52 #include <asm/cputable.h> 53 #include <asm/sections.h> 54 #include <asm/btext.h> 55 #include <asm/nvram.h> 56 #include <asm/setup.h> 57 #include <asm/rtas.h> 58 #include <asm/iommu.h> 59 #include <asm/serial.h> 60 #include <asm/cache.h> 61 #include <asm/page.h> 62 #include <asm/mmu.h> 63 #include <asm/firmware.h> 64 #include <asm/xmon.h> 65 #include <asm/udbg.h> 66 #include <asm/kexec.h> 67 #include <asm/mmu_context.h> 68 #include <asm/code-patching.h> 69 #include <asm/kvm_ppc.h> 70 #include <asm/hugetlb.h> 71 #include <asm/epapr_hcalls.h> 72 #include <asm/livepatch.h> 73 74 #ifdef DEBUG 75 #define DBG(fmt...) udbg_printf(fmt) 76 #else 77 #define DBG(fmt...) 78 #endif 79 80 int spinning_secondaries; 81 u64 ppc64_pft_size; 82 83 /* Pick defaults since we might want to patch instructions 84 * before we've read this from the device tree. 85 */ 86 struct ppc64_caches ppc64_caches = { 87 .dline_size = 0x40, 88 .log_dline_size = 6, 89 .iline_size = 0x40, 90 .log_iline_size = 6 91 }; 92 EXPORT_SYMBOL_GPL(ppc64_caches); 93 94 /* 95 * These are used in binfmt_elf.c to put aux entries on the stack 96 * for each elf executable being started. 97 */ 98 int dcache_bsize; 99 int icache_bsize; 100 int ucache_bsize; 101 102 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 103 static void setup_tlb_core_data(void) 104 { 105 int cpu; 106 107 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 108 109 for_each_possible_cpu(cpu) { 110 int first = cpu_first_thread_sibling(cpu); 111 112 /* 113 * If we boot via kdump on a non-primary thread, 114 * make sure we point at the thread that actually 115 * set up this TLB. 116 */ 117 if (cpu_first_thread_sibling(boot_cpuid) == first) 118 first = boot_cpuid; 119 120 paca[cpu].tcd_ptr = &paca[first].tcd; 121 122 /* 123 * If we have threads, we need either tlbsrx. 124 * or e6500 tablewalk mode, or else TLB handlers 125 * will be racy and could produce duplicate entries. 126 */ 127 if (smt_enabled_at_boot >= 2 && 128 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 129 book3e_htw_mode != PPC_HTW_E6500) { 130 /* Should we panic instead? */ 131 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", 132 __func__); 133 } 134 } 135 } 136 #else 137 static void setup_tlb_core_data(void) 138 { 139 } 140 #endif 141 142 #ifdef CONFIG_SMP 143 144 static char *smt_enabled_cmdline; 145 146 /* Look for ibm,smt-enabled OF option */ 147 static void check_smt_enabled(void) 148 { 149 struct device_node *dn; 150 const char *smt_option; 151 152 /* Default to enabling all threads */ 153 smt_enabled_at_boot = threads_per_core; 154 155 /* Allow the command line to overrule the OF option */ 156 if (smt_enabled_cmdline) { 157 if (!strcmp(smt_enabled_cmdline, "on")) 158 smt_enabled_at_boot = threads_per_core; 159 else if (!strcmp(smt_enabled_cmdline, "off")) 160 smt_enabled_at_boot = 0; 161 else { 162 int smt; 163 int rc; 164 165 rc = kstrtoint(smt_enabled_cmdline, 10, &smt); 166 if (!rc) 167 smt_enabled_at_boot = 168 min(threads_per_core, smt); 169 } 170 } else { 171 dn = of_find_node_by_path("/options"); 172 if (dn) { 173 smt_option = of_get_property(dn, "ibm,smt-enabled", 174 NULL); 175 176 if (smt_option) { 177 if (!strcmp(smt_option, "on")) 178 smt_enabled_at_boot = threads_per_core; 179 else if (!strcmp(smt_option, "off")) 180 smt_enabled_at_boot = 0; 181 } 182 183 of_node_put(dn); 184 } 185 } 186 } 187 188 /* Look for smt-enabled= cmdline option */ 189 static int __init early_smt_enabled(char *p) 190 { 191 smt_enabled_cmdline = p; 192 return 0; 193 } 194 early_param("smt-enabled", early_smt_enabled); 195 196 #else 197 #define check_smt_enabled() 198 #endif /* CONFIG_SMP */ 199 200 /** Fix up paca fields required for the boot cpu */ 201 static void fixup_boot_paca(void) 202 { 203 /* The boot cpu is started */ 204 get_paca()->cpu_start = 1; 205 /* Allow percpu accesses to work until we setup percpu data */ 206 get_paca()->data_offset = 0; 207 } 208 209 static void cpu_ready_for_interrupts(void) 210 { 211 /* Set IR and DR in PACA MSR */ 212 get_paca()->kernel_msr = MSR_KERNEL; 213 214 /* 215 * Enable AIL if supported, and we are in hypervisor mode. If we are 216 * not in hypervisor mode, we enable relocation-on interrupts later 217 * in pSeries_setup_arch() using the H_SET_MODE hcall. 218 */ 219 if (cpu_has_feature(CPU_FTR_HVMODE) && 220 cpu_has_feature(CPU_FTR_ARCH_207S)) { 221 unsigned long lpcr = mfspr(SPRN_LPCR); 222 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); 223 } 224 } 225 226 /* 227 * Early initialization entry point. This is called by head.S 228 * with MMU translation disabled. We rely on the "feature" of 229 * the CPU that ignores the top 2 bits of the address in real 230 * mode so we can access kernel globals normally provided we 231 * only toy with things in the RMO region. From here, we do 232 * some early parsing of the device-tree to setup out MEMBLOCK 233 * data structures, and allocate & initialize the hash table 234 * and segment tables so we can start running with translation 235 * enabled. 236 * 237 * It is this function which will call the probe() callback of 238 * the various platform types and copy the matching one to the 239 * global ppc_md structure. Your platform can eventually do 240 * some very early initializations from the probe() routine, but 241 * this is not recommended, be very careful as, for example, the 242 * device-tree is not accessible via normal means at this point. 243 */ 244 245 void __init early_setup(unsigned long dt_ptr) 246 { 247 static __initdata struct paca_struct boot_paca; 248 249 /* -------- printk is _NOT_ safe to use here ! ------- */ 250 251 /* Identify CPU type */ 252 identify_cpu(0, mfspr(SPRN_PVR)); 253 254 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 255 initialise_paca(&boot_paca, 0); 256 setup_paca(&boot_paca); 257 fixup_boot_paca(); 258 259 /* -------- printk is now safe to use ------- */ 260 261 /* Enable early debugging if any specified (see udbg.h) */ 262 udbg_early_init(); 263 264 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 265 266 /* 267 * Do early initialization using the flattened device 268 * tree, such as retrieving the physical memory map or 269 * calculating/retrieving the hash table size. 270 */ 271 early_init_devtree(__va(dt_ptr)); 272 273 epapr_paravirt_early_init(); 274 275 /* Now we know the logical id of our boot cpu, setup the paca. */ 276 setup_paca(&paca[boot_cpuid]); 277 fixup_boot_paca(); 278 279 /* Probe the machine type */ 280 probe_machine(); 281 282 setup_kdump_trampoline(); 283 284 DBG("Found, Initializing memory management...\n"); 285 286 /* Initialize the hash table or TLB handling */ 287 early_init_mmu(); 288 289 /* 290 * At this point, we can let interrupts switch to virtual mode 291 * (the MMU has been setup), so adjust the MSR in the PACA to 292 * have IR and DR set and enable AIL if it exists 293 */ 294 cpu_ready_for_interrupts(); 295 296 /* Reserve large chunks of memory for use by CMA for KVM */ 297 kvm_cma_reserve(); 298 299 /* 300 * Reserve any gigantic pages requested on the command line. 301 * memblock needs to have been initialized by the time this is 302 * called since this will reserve memory. 303 */ 304 reserve_hugetlb_gpages(); 305 306 DBG(" <- early_setup()\n"); 307 308 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 309 /* 310 * This needs to be done *last* (after the above DBG() even) 311 * 312 * Right after we return from this function, we turn on the MMU 313 * which means the real-mode access trick that btext does will 314 * no longer work, it needs to switch to using a real MMU 315 * mapping. This call will ensure that it does 316 */ 317 btext_map(); 318 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 319 } 320 321 #ifdef CONFIG_SMP 322 void early_setup_secondary(void) 323 { 324 /* Mark interrupts enabled in PACA */ 325 get_paca()->soft_enabled = 0; 326 327 /* Initialize the hash table or TLB handling */ 328 early_init_mmu_secondary(); 329 330 /* 331 * At this point, we can let interrupts switch to virtual mode 332 * (the MMU has been setup), so adjust the MSR in the PACA to 333 * have IR and DR set. 334 */ 335 cpu_ready_for_interrupts(); 336 } 337 338 #endif /* CONFIG_SMP */ 339 340 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 341 static bool use_spinloop(void) 342 { 343 if (!IS_ENABLED(CONFIG_PPC_BOOK3E)) 344 return true; 345 346 /* 347 * When book3e boots from kexec, the ePAPR spin table does 348 * not get used. 349 */ 350 return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); 351 } 352 353 void smp_release_cpus(void) 354 { 355 unsigned long *ptr; 356 int i; 357 358 if (!use_spinloop()) 359 return; 360 361 DBG(" -> smp_release_cpus()\n"); 362 363 /* All secondary cpus are spinning on a common spinloop, release them 364 * all now so they can start to spin on their individual paca 365 * spinloops. For non SMP kernels, the secondary cpus never get out 366 * of the common spinloop. 367 */ 368 369 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 370 - PHYSICAL_START); 371 *ptr = ppc_function_entry(generic_secondary_smp_init); 372 373 /* And wait a bit for them to catch up */ 374 for (i = 0; i < 100000; i++) { 375 mb(); 376 HMT_low(); 377 if (spinning_secondaries == 0) 378 break; 379 udelay(1); 380 } 381 DBG("spinning_secondaries = %d\n", spinning_secondaries); 382 383 DBG(" <- smp_release_cpus()\n"); 384 } 385 #endif /* CONFIG_SMP || CONFIG_KEXEC */ 386 387 /* 388 * Initialize some remaining members of the ppc64_caches and systemcfg 389 * structures 390 * (at least until we get rid of them completely). This is mostly some 391 * cache informations about the CPU that will be used by cache flush 392 * routines and/or provided to userland 393 */ 394 static void __init initialize_cache_info(void) 395 { 396 struct device_node *np; 397 unsigned long num_cpus = 0; 398 399 DBG(" -> initialize_cache_info()\n"); 400 401 for_each_node_by_type(np, "cpu") { 402 num_cpus += 1; 403 404 /* 405 * We're assuming *all* of the CPUs have the same 406 * d-cache and i-cache sizes... -Peter 407 */ 408 if (num_cpus == 1) { 409 const __be32 *sizep, *lsizep; 410 u32 size, lsize; 411 412 size = 0; 413 lsize = cur_cpu_spec->dcache_bsize; 414 sizep = of_get_property(np, "d-cache-size", NULL); 415 if (sizep != NULL) 416 size = be32_to_cpu(*sizep); 417 lsizep = of_get_property(np, "d-cache-block-size", 418 NULL); 419 /* fallback if block size missing */ 420 if (lsizep == NULL) 421 lsizep = of_get_property(np, 422 "d-cache-line-size", 423 NULL); 424 if (lsizep != NULL) 425 lsize = be32_to_cpu(*lsizep); 426 if (sizep == NULL || lsizep == NULL) 427 DBG("Argh, can't find dcache properties ! " 428 "sizep: %p, lsizep: %p\n", sizep, lsizep); 429 430 ppc64_caches.dsize = size; 431 ppc64_caches.dline_size = lsize; 432 ppc64_caches.log_dline_size = __ilog2(lsize); 433 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 434 435 size = 0; 436 lsize = cur_cpu_spec->icache_bsize; 437 sizep = of_get_property(np, "i-cache-size", NULL); 438 if (sizep != NULL) 439 size = be32_to_cpu(*sizep); 440 lsizep = of_get_property(np, "i-cache-block-size", 441 NULL); 442 if (lsizep == NULL) 443 lsizep = of_get_property(np, 444 "i-cache-line-size", 445 NULL); 446 if (lsizep != NULL) 447 lsize = be32_to_cpu(*lsizep); 448 if (sizep == NULL || lsizep == NULL) 449 DBG("Argh, can't find icache properties ! " 450 "sizep: %p, lsizep: %p\n", sizep, lsizep); 451 452 ppc64_caches.isize = size; 453 ppc64_caches.iline_size = lsize; 454 ppc64_caches.log_iline_size = __ilog2(lsize); 455 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 456 } 457 } 458 459 DBG(" <- initialize_cache_info()\n"); 460 } 461 462 463 /* 464 * Do some initial setup of the system. The parameters are those which 465 * were passed in from the bootloader. 466 */ 467 void __init setup_system(void) 468 { 469 DBG(" -> setup_system()\n"); 470 471 /* Apply the CPUs-specific and firmware specific fixups to kernel 472 * text (nop out sections not relevant to this CPU or this firmware) 473 */ 474 do_feature_fixups(cur_cpu_spec->cpu_features, 475 &__start___ftr_fixup, &__stop___ftr_fixup); 476 do_feature_fixups(cur_cpu_spec->mmu_features, 477 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 478 do_feature_fixups(powerpc_firmware_features, 479 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 480 do_lwsync_fixups(cur_cpu_spec->cpu_features, 481 &__start___lwsync_fixup, &__stop___lwsync_fixup); 482 do_final_fixups(); 483 484 /* 485 * Unflatten the device-tree passed by prom_init or kexec 486 */ 487 unflatten_device_tree(); 488 489 /* 490 * Fill the ppc64_caches & systemcfg structures with informations 491 * retrieved from the device-tree. 492 */ 493 initialize_cache_info(); 494 495 #ifdef CONFIG_PPC_RTAS 496 /* 497 * Initialize RTAS if available 498 */ 499 rtas_initialize(); 500 #endif /* CONFIG_PPC_RTAS */ 501 502 /* 503 * Check if we have an initrd provided via the device-tree 504 */ 505 check_for_initrd(); 506 507 /* 508 * Do some platform specific early initializations, that includes 509 * setting up the hash table pointers. It also sets up some interrupt-mapping 510 * related options that will be used by finish_device_tree() 511 */ 512 if (ppc_md.init_early) 513 ppc_md.init_early(); 514 515 /* 516 * We can discover serial ports now since the above did setup the 517 * hash table management for us, thus ioremap works. We do that early 518 * so that further code can be debugged 519 */ 520 find_legacy_serial_ports(); 521 522 /* 523 * Register early console 524 */ 525 register_early_udbg_console(); 526 527 /* 528 * Initialize xmon 529 */ 530 xmon_setup(); 531 532 smp_setup_cpu_maps(); 533 check_smt_enabled(); 534 setup_tlb_core_data(); 535 536 /* 537 * Freescale Book3e parts spin in a loop provided by firmware, 538 * so smp_release_cpus() does nothing for them 539 */ 540 #if defined(CONFIG_SMP) 541 /* Release secondary cpus out of their spinloops at 0x60 now that 542 * we can map physical -> logical CPU ids 543 */ 544 smp_release_cpus(); 545 #endif 546 547 pr_info("Starting Linux %s %s\n", init_utsname()->machine, 548 init_utsname()->version); 549 550 pr_info("-----------------------------------------------------\n"); 551 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 552 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); 553 554 if (ppc64_caches.dline_size != 0x80) 555 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); 556 if (ppc64_caches.iline_size != 0x80) 557 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); 558 559 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); 560 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); 561 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); 562 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, 563 cur_cpu_spec->cpu_user_features2); 564 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); 565 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); 566 567 #ifdef CONFIG_PPC_STD_MMU_64 568 if (htab_address) 569 pr_info("htab_address = 0x%p\n", htab_address); 570 571 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 572 #endif 573 574 if (PHYSICAL_START > 0) 575 pr_info("physical_start = 0x%llx\n", 576 (unsigned long long)PHYSICAL_START); 577 pr_info("-----------------------------------------------------\n"); 578 579 DBG(" <- setup_system()\n"); 580 } 581 582 /* This returns the limit below which memory accesses to the linear 583 * mapping are guarnateed not to cause a TLB or SLB miss. This is 584 * used to allocate interrupt or emergency stacks for which our 585 * exception entry path doesn't deal with being interrupted. 586 */ 587 static u64 safe_stack_limit(void) 588 { 589 #ifdef CONFIG_PPC_BOOK3E 590 /* Freescale BookE bolts the entire linear mapping */ 591 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 592 return linear_map_top; 593 /* Other BookE, we assume the first GB is bolted */ 594 return 1ul << 30; 595 #else 596 /* BookS, the first segment is bolted */ 597 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 598 return 1UL << SID_SHIFT_1T; 599 return 1UL << SID_SHIFT; 600 #endif 601 } 602 603 static void __init irqstack_early_init(void) 604 { 605 u64 limit = safe_stack_limit(); 606 unsigned int i; 607 608 /* 609 * Interrupt stacks must be in the first segment since we 610 * cannot afford to take SLB misses on them. 611 */ 612 for_each_possible_cpu(i) { 613 softirq_ctx[i] = (struct thread_info *) 614 __va(memblock_alloc_base(THREAD_SIZE, 615 THREAD_SIZE, limit)); 616 hardirq_ctx[i] = (struct thread_info *) 617 __va(memblock_alloc_base(THREAD_SIZE, 618 THREAD_SIZE, limit)); 619 } 620 } 621 622 #ifdef CONFIG_PPC_BOOK3E 623 static void __init exc_lvl_early_init(void) 624 { 625 unsigned int i; 626 unsigned long sp; 627 628 for_each_possible_cpu(i) { 629 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 630 critirq_ctx[i] = (struct thread_info *)__va(sp); 631 paca[i].crit_kstack = __va(sp + THREAD_SIZE); 632 633 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 634 dbgirq_ctx[i] = (struct thread_info *)__va(sp); 635 paca[i].dbg_kstack = __va(sp + THREAD_SIZE); 636 637 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 638 mcheckirq_ctx[i] = (struct thread_info *)__va(sp); 639 paca[i].mc_kstack = __va(sp + THREAD_SIZE); 640 } 641 642 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 643 patch_exception(0x040, exc_debug_debug_book3e); 644 } 645 #else 646 #define exc_lvl_early_init() 647 #endif 648 649 /* 650 * Stack space used when we detect a bad kernel stack pointer, and 651 * early in SMP boots before relocation is enabled. Exclusive emergency 652 * stack for machine checks. 653 */ 654 static void __init emergency_stack_init(void) 655 { 656 u64 limit; 657 unsigned int i; 658 659 /* 660 * Emergency stacks must be under 256MB, we cannot afford to take 661 * SLB misses on them. The ABI also requires them to be 128-byte 662 * aligned. 663 * 664 * Since we use these as temporary stacks during secondary CPU 665 * bringup, we need to get at them in real mode. This means they 666 * must also be within the RMO region. 667 */ 668 limit = min(safe_stack_limit(), ppc64_rma_size); 669 670 for_each_possible_cpu(i) { 671 struct thread_info *ti; 672 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); 673 klp_init_thread_info(ti); 674 paca[i].emergency_sp = (void *)ti + THREAD_SIZE; 675 676 #ifdef CONFIG_PPC_BOOK3S_64 677 /* emergency stack for machine check exception handling. */ 678 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); 679 klp_init_thread_info(ti); 680 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE; 681 #endif 682 } 683 } 684 685 /* 686 * Called into from start_kernel this initializes memblock, which is used 687 * to manage page allocation until mem_init is called. 688 */ 689 void __init setup_arch(char **cmdline_p) 690 { 691 *cmdline_p = boot_command_line; 692 693 /* 694 * Set cache line size based on type of cpu as a default. 695 * Systems with OF can look in the properties on the cpu node(s) 696 * for a possibly more accurate value. 697 */ 698 dcache_bsize = ppc64_caches.dline_size; 699 icache_bsize = ppc64_caches.iline_size; 700 701 if (ppc_md.panic) 702 setup_panic(); 703 704 klp_init_thread_info(&init_thread_info); 705 706 init_mm.start_code = (unsigned long)_stext; 707 init_mm.end_code = (unsigned long) _etext; 708 init_mm.end_data = (unsigned long) _edata; 709 init_mm.brk = klimit; 710 #ifdef CONFIG_PPC_64K_PAGES 711 init_mm.context.pte_frag = NULL; 712 #endif 713 #ifdef CONFIG_SPAPR_TCE_IOMMU 714 mm_iommu_init(&init_mm.context); 715 #endif 716 irqstack_early_init(); 717 exc_lvl_early_init(); 718 emergency_stack_init(); 719 720 initmem_init(); 721 722 #ifdef CONFIG_DUMMY_CONSOLE 723 conswitchp = &dummy_con; 724 #endif 725 726 if (ppc_md.setup_arch) 727 ppc_md.setup_arch(); 728 729 paging_init(); 730 731 /* Initialize the MMU context management stuff */ 732 mmu_context_init(); 733 734 /* Interrupt code needs to be 64K-aligned */ 735 if ((unsigned long)_stext & 0xffff) 736 panic("Kernelbase not 64K-aligned (0x%lx)!\n", 737 (unsigned long)_stext); 738 } 739 740 #ifdef CONFIG_SMP 741 #define PCPU_DYN_SIZE () 742 743 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 744 { 745 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 746 __pa(MAX_DMA_ADDRESS)); 747 } 748 749 static void __init pcpu_fc_free(void *ptr, size_t size) 750 { 751 free_bootmem(__pa(ptr), size); 752 } 753 754 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 755 { 756 if (cpu_to_node(from) == cpu_to_node(to)) 757 return LOCAL_DISTANCE; 758 else 759 return REMOTE_DISTANCE; 760 } 761 762 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 763 EXPORT_SYMBOL(__per_cpu_offset); 764 765 void __init setup_per_cpu_areas(void) 766 { 767 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 768 size_t atom_size; 769 unsigned long delta; 770 unsigned int cpu; 771 int rc; 772 773 /* 774 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 775 * to group units. For larger mappings, use 1M atom which 776 * should be large enough to contain a number of units. 777 */ 778 if (mmu_linear_psize == MMU_PAGE_4K) 779 atom_size = PAGE_SIZE; 780 else 781 atom_size = 1 << 20; 782 783 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 784 pcpu_fc_alloc, pcpu_fc_free); 785 if (rc < 0) 786 panic("cannot initialize percpu area (err=%d)", rc); 787 788 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 789 for_each_possible_cpu(cpu) { 790 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 791 paca[cpu].data_offset = __per_cpu_offset[cpu]; 792 } 793 } 794 #endif 795 796 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 797 unsigned long memory_block_size_bytes(void) 798 { 799 if (ppc_md.memory_block_size) 800 return ppc_md.memory_block_size(); 801 802 return MIN_MEMORY_BLOCK_SIZE; 803 } 804 #endif 805 806 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 807 struct ppc_pci_io ppc_pci_io; 808 EXPORT_SYMBOL(ppc_pci_io); 809 #endif 810 811 #ifdef CONFIG_HARDLOCKUP_DETECTOR 812 u64 hw_nmi_get_sample_period(int watchdog_thresh) 813 { 814 return ppc_proc_freq * watchdog_thresh; 815 } 816 817 /* 818 * The hardlockup detector breaks PMU event based branches and is likely 819 * to get false positives in KVM guests, so disable it by default. 820 */ 821 static int __init disable_hardlockup_detector(void) 822 { 823 hardlockup_detector_disable(); 824 825 return 0; 826 } 827 early_initcall(disable_hardlockup_detector); 828 #endif 829