1 /* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #define DEBUG 14 15 #include <linux/export.h> 16 #include <linux/string.h> 17 #include <linux/sched.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/reboot.h> 21 #include <linux/delay.h> 22 #include <linux/initrd.h> 23 #include <linux/seq_file.h> 24 #include <linux/ioport.h> 25 #include <linux/console.h> 26 #include <linux/utsname.h> 27 #include <linux/tty.h> 28 #include <linux/root_dev.h> 29 #include <linux/notifier.h> 30 #include <linux/cpu.h> 31 #include <linux/unistd.h> 32 #include <linux/serial.h> 33 #include <linux/serial_8250.h> 34 #include <linux/bootmem.h> 35 #include <linux/pci.h> 36 #include <linux/lockdep.h> 37 #include <linux/memblock.h> 38 #include <linux/hugetlb.h> 39 #include <linux/memory.h> 40 #include <linux/nmi.h> 41 42 #include <asm/io.h> 43 #include <asm/kdump.h> 44 #include <asm/prom.h> 45 #include <asm/processor.h> 46 #include <asm/pgtable.h> 47 #include <asm/smp.h> 48 #include <asm/elf.h> 49 #include <asm/machdep.h> 50 #include <asm/paca.h> 51 #include <asm/time.h> 52 #include <asm/cputable.h> 53 #include <asm/sections.h> 54 #include <asm/btext.h> 55 #include <asm/nvram.h> 56 #include <asm/setup.h> 57 #include <asm/rtas.h> 58 #include <asm/iommu.h> 59 #include <asm/serial.h> 60 #include <asm/cache.h> 61 #include <asm/page.h> 62 #include <asm/mmu.h> 63 #include <asm/firmware.h> 64 #include <asm/xmon.h> 65 #include <asm/udbg.h> 66 #include <asm/kexec.h> 67 #include <asm/mmu_context.h> 68 #include <asm/code-patching.h> 69 #include <asm/kvm_ppc.h> 70 #include <asm/hugetlb.h> 71 #include <asm/epapr_hcalls.h> 72 73 #ifdef DEBUG 74 #define DBG(fmt...) udbg_printf(fmt) 75 #else 76 #define DBG(fmt...) 77 #endif 78 79 int spinning_secondaries; 80 u64 ppc64_pft_size; 81 82 /* Pick defaults since we might want to patch instructions 83 * before we've read this from the device tree. 84 */ 85 struct ppc64_caches ppc64_caches = { 86 .dline_size = 0x40, 87 .log_dline_size = 6, 88 .iline_size = 0x40, 89 .log_iline_size = 6 90 }; 91 EXPORT_SYMBOL_GPL(ppc64_caches); 92 93 /* 94 * These are used in binfmt_elf.c to put aux entries on the stack 95 * for each elf executable being started. 96 */ 97 int dcache_bsize; 98 int icache_bsize; 99 int ucache_bsize; 100 101 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 102 static void setup_tlb_core_data(void) 103 { 104 int cpu; 105 106 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 107 108 for_each_possible_cpu(cpu) { 109 int first = cpu_first_thread_sibling(cpu); 110 111 /* 112 * If we boot via kdump on a non-primary thread, 113 * make sure we point at the thread that actually 114 * set up this TLB. 115 */ 116 if (cpu_first_thread_sibling(boot_cpuid) == first) 117 first = boot_cpuid; 118 119 paca[cpu].tcd_ptr = &paca[first].tcd; 120 121 /* 122 * If we have threads, we need either tlbsrx. 123 * or e6500 tablewalk mode, or else TLB handlers 124 * will be racy and could produce duplicate entries. 125 */ 126 if (smt_enabled_at_boot >= 2 && 127 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 128 book3e_htw_mode != PPC_HTW_E6500) { 129 /* Should we panic instead? */ 130 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", 131 __func__); 132 } 133 } 134 } 135 #else 136 static void setup_tlb_core_data(void) 137 { 138 } 139 #endif 140 141 #ifdef CONFIG_SMP 142 143 static char *smt_enabled_cmdline; 144 145 /* Look for ibm,smt-enabled OF option */ 146 static void check_smt_enabled(void) 147 { 148 struct device_node *dn; 149 const char *smt_option; 150 151 /* Default to enabling all threads */ 152 smt_enabled_at_boot = threads_per_core; 153 154 /* Allow the command line to overrule the OF option */ 155 if (smt_enabled_cmdline) { 156 if (!strcmp(smt_enabled_cmdline, "on")) 157 smt_enabled_at_boot = threads_per_core; 158 else if (!strcmp(smt_enabled_cmdline, "off")) 159 smt_enabled_at_boot = 0; 160 else { 161 int smt; 162 int rc; 163 164 rc = kstrtoint(smt_enabled_cmdline, 10, &smt); 165 if (!rc) 166 smt_enabled_at_boot = 167 min(threads_per_core, smt); 168 } 169 } else { 170 dn = of_find_node_by_path("/options"); 171 if (dn) { 172 smt_option = of_get_property(dn, "ibm,smt-enabled", 173 NULL); 174 175 if (smt_option) { 176 if (!strcmp(smt_option, "on")) 177 smt_enabled_at_boot = threads_per_core; 178 else if (!strcmp(smt_option, "off")) 179 smt_enabled_at_boot = 0; 180 } 181 182 of_node_put(dn); 183 } 184 } 185 } 186 187 /* Look for smt-enabled= cmdline option */ 188 static int __init early_smt_enabled(char *p) 189 { 190 smt_enabled_cmdline = p; 191 return 0; 192 } 193 early_param("smt-enabled", early_smt_enabled); 194 195 #else 196 #define check_smt_enabled() 197 #endif /* CONFIG_SMP */ 198 199 /** Fix up paca fields required for the boot cpu */ 200 static void fixup_boot_paca(void) 201 { 202 /* The boot cpu is started */ 203 get_paca()->cpu_start = 1; 204 /* Allow percpu accesses to work until we setup percpu data */ 205 get_paca()->data_offset = 0; 206 } 207 208 static void cpu_ready_for_interrupts(void) 209 { 210 /* Set IR and DR in PACA MSR */ 211 get_paca()->kernel_msr = MSR_KERNEL; 212 213 /* 214 * Enable AIL if supported, and we are in hypervisor mode. If we are 215 * not in hypervisor mode, we enable relocation-on interrupts later 216 * in pSeries_setup_arch() using the H_SET_MODE hcall. 217 */ 218 if (cpu_has_feature(CPU_FTR_HVMODE) && 219 cpu_has_feature(CPU_FTR_ARCH_207S)) { 220 unsigned long lpcr = mfspr(SPRN_LPCR); 221 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); 222 } 223 } 224 225 /* 226 * Early initialization entry point. This is called by head.S 227 * with MMU translation disabled. We rely on the "feature" of 228 * the CPU that ignores the top 2 bits of the address in real 229 * mode so we can access kernel globals normally provided we 230 * only toy with things in the RMO region. From here, we do 231 * some early parsing of the device-tree to setup out MEMBLOCK 232 * data structures, and allocate & initialize the hash table 233 * and segment tables so we can start running with translation 234 * enabled. 235 * 236 * It is this function which will call the probe() callback of 237 * the various platform types and copy the matching one to the 238 * global ppc_md structure. Your platform can eventually do 239 * some very early initializations from the probe() routine, but 240 * this is not recommended, be very careful as, for example, the 241 * device-tree is not accessible via normal means at this point. 242 */ 243 244 void __init early_setup(unsigned long dt_ptr) 245 { 246 static __initdata struct paca_struct boot_paca; 247 248 /* -------- printk is _NOT_ safe to use here ! ------- */ 249 250 /* Identify CPU type */ 251 identify_cpu(0, mfspr(SPRN_PVR)); 252 253 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 254 initialise_paca(&boot_paca, 0); 255 setup_paca(&boot_paca); 256 fixup_boot_paca(); 257 258 /* -------- printk is now safe to use ------- */ 259 260 /* Enable early debugging if any specified (see udbg.h) */ 261 udbg_early_init(); 262 263 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 264 265 /* 266 * Do early initialization using the flattened device 267 * tree, such as retrieving the physical memory map or 268 * calculating/retrieving the hash table size. 269 */ 270 early_init_devtree(__va(dt_ptr)); 271 272 epapr_paravirt_early_init(); 273 274 /* Now we know the logical id of our boot cpu, setup the paca. */ 275 setup_paca(&paca[boot_cpuid]); 276 fixup_boot_paca(); 277 278 /* Probe the machine type */ 279 probe_machine(); 280 281 setup_kdump_trampoline(); 282 283 DBG("Found, Initializing memory management...\n"); 284 285 /* Initialize the hash table or TLB handling */ 286 early_init_mmu(); 287 288 /* 289 * At this point, we can let interrupts switch to virtual mode 290 * (the MMU has been setup), so adjust the MSR in the PACA to 291 * have IR and DR set and enable AIL if it exists 292 */ 293 cpu_ready_for_interrupts(); 294 295 /* Reserve large chunks of memory for use by CMA for KVM */ 296 kvm_cma_reserve(); 297 298 /* 299 * Reserve any gigantic pages requested on the command line. 300 * memblock needs to have been initialized by the time this is 301 * called since this will reserve memory. 302 */ 303 reserve_hugetlb_gpages(); 304 305 DBG(" <- early_setup()\n"); 306 307 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 308 /* 309 * This needs to be done *last* (after the above DBG() even) 310 * 311 * Right after we return from this function, we turn on the MMU 312 * which means the real-mode access trick that btext does will 313 * no longer work, it needs to switch to using a real MMU 314 * mapping. This call will ensure that it does 315 */ 316 btext_map(); 317 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 318 } 319 320 #ifdef CONFIG_SMP 321 void early_setup_secondary(void) 322 { 323 /* Mark interrupts enabled in PACA */ 324 get_paca()->soft_enabled = 0; 325 326 /* Initialize the hash table or TLB handling */ 327 early_init_mmu_secondary(); 328 329 /* 330 * At this point, we can let interrupts switch to virtual mode 331 * (the MMU has been setup), so adjust the MSR in the PACA to 332 * have IR and DR set. 333 */ 334 cpu_ready_for_interrupts(); 335 } 336 337 #endif /* CONFIG_SMP */ 338 339 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 340 static bool use_spinloop(void) 341 { 342 if (!IS_ENABLED(CONFIG_PPC_BOOK3E)) 343 return true; 344 345 /* 346 * When book3e boots from kexec, the ePAPR spin table does 347 * not get used. 348 */ 349 return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); 350 } 351 352 void smp_release_cpus(void) 353 { 354 unsigned long *ptr; 355 int i; 356 357 if (!use_spinloop()) 358 return; 359 360 DBG(" -> smp_release_cpus()\n"); 361 362 /* All secondary cpus are spinning on a common spinloop, release them 363 * all now so they can start to spin on their individual paca 364 * spinloops. For non SMP kernels, the secondary cpus never get out 365 * of the common spinloop. 366 */ 367 368 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 369 - PHYSICAL_START); 370 *ptr = ppc_function_entry(generic_secondary_smp_init); 371 372 /* And wait a bit for them to catch up */ 373 for (i = 0; i < 100000; i++) { 374 mb(); 375 HMT_low(); 376 if (spinning_secondaries == 0) 377 break; 378 udelay(1); 379 } 380 DBG("spinning_secondaries = %d\n", spinning_secondaries); 381 382 DBG(" <- smp_release_cpus()\n"); 383 } 384 #endif /* CONFIG_SMP || CONFIG_KEXEC */ 385 386 /* 387 * Initialize some remaining members of the ppc64_caches and systemcfg 388 * structures 389 * (at least until we get rid of them completely). This is mostly some 390 * cache informations about the CPU that will be used by cache flush 391 * routines and/or provided to userland 392 */ 393 static void __init initialize_cache_info(void) 394 { 395 struct device_node *np; 396 unsigned long num_cpus = 0; 397 398 DBG(" -> initialize_cache_info()\n"); 399 400 for_each_node_by_type(np, "cpu") { 401 num_cpus += 1; 402 403 /* 404 * We're assuming *all* of the CPUs have the same 405 * d-cache and i-cache sizes... -Peter 406 */ 407 if (num_cpus == 1) { 408 const __be32 *sizep, *lsizep; 409 u32 size, lsize; 410 411 size = 0; 412 lsize = cur_cpu_spec->dcache_bsize; 413 sizep = of_get_property(np, "d-cache-size", NULL); 414 if (sizep != NULL) 415 size = be32_to_cpu(*sizep); 416 lsizep = of_get_property(np, "d-cache-block-size", 417 NULL); 418 /* fallback if block size missing */ 419 if (lsizep == NULL) 420 lsizep = of_get_property(np, 421 "d-cache-line-size", 422 NULL); 423 if (lsizep != NULL) 424 lsize = be32_to_cpu(*lsizep); 425 if (sizep == NULL || lsizep == NULL) 426 DBG("Argh, can't find dcache properties ! " 427 "sizep: %p, lsizep: %p\n", sizep, lsizep); 428 429 ppc64_caches.dsize = size; 430 ppc64_caches.dline_size = lsize; 431 ppc64_caches.log_dline_size = __ilog2(lsize); 432 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 433 434 size = 0; 435 lsize = cur_cpu_spec->icache_bsize; 436 sizep = of_get_property(np, "i-cache-size", NULL); 437 if (sizep != NULL) 438 size = be32_to_cpu(*sizep); 439 lsizep = of_get_property(np, "i-cache-block-size", 440 NULL); 441 if (lsizep == NULL) 442 lsizep = of_get_property(np, 443 "i-cache-line-size", 444 NULL); 445 if (lsizep != NULL) 446 lsize = be32_to_cpu(*lsizep); 447 if (sizep == NULL || lsizep == NULL) 448 DBG("Argh, can't find icache properties ! " 449 "sizep: %p, lsizep: %p\n", sizep, lsizep); 450 451 ppc64_caches.isize = size; 452 ppc64_caches.iline_size = lsize; 453 ppc64_caches.log_iline_size = __ilog2(lsize); 454 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 455 } 456 } 457 458 DBG(" <- initialize_cache_info()\n"); 459 } 460 461 462 /* 463 * Do some initial setup of the system. The parameters are those which 464 * were passed in from the bootloader. 465 */ 466 void __init setup_system(void) 467 { 468 DBG(" -> setup_system()\n"); 469 470 /* Apply the CPUs-specific and firmware specific fixups to kernel 471 * text (nop out sections not relevant to this CPU or this firmware) 472 */ 473 do_feature_fixups(cur_cpu_spec->cpu_features, 474 &__start___ftr_fixup, &__stop___ftr_fixup); 475 do_feature_fixups(cur_cpu_spec->mmu_features, 476 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 477 do_feature_fixups(powerpc_firmware_features, 478 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 479 do_lwsync_fixups(cur_cpu_spec->cpu_features, 480 &__start___lwsync_fixup, &__stop___lwsync_fixup); 481 do_final_fixups(); 482 483 /* 484 * Unflatten the device-tree passed by prom_init or kexec 485 */ 486 unflatten_device_tree(); 487 488 /* 489 * Fill the ppc64_caches & systemcfg structures with informations 490 * retrieved from the device-tree. 491 */ 492 initialize_cache_info(); 493 494 #ifdef CONFIG_PPC_RTAS 495 /* 496 * Initialize RTAS if available 497 */ 498 rtas_initialize(); 499 #endif /* CONFIG_PPC_RTAS */ 500 501 /* 502 * Check if we have an initrd provided via the device-tree 503 */ 504 check_for_initrd(); 505 506 /* 507 * Do some platform specific early initializations, that includes 508 * setting up the hash table pointers. It also sets up some interrupt-mapping 509 * related options that will be used by finish_device_tree() 510 */ 511 if (ppc_md.init_early) 512 ppc_md.init_early(); 513 514 /* 515 * We can discover serial ports now since the above did setup the 516 * hash table management for us, thus ioremap works. We do that early 517 * so that further code can be debugged 518 */ 519 find_legacy_serial_ports(); 520 521 /* 522 * Register early console 523 */ 524 register_early_udbg_console(); 525 526 /* 527 * Initialize xmon 528 */ 529 xmon_setup(); 530 531 smp_setup_cpu_maps(); 532 check_smt_enabled(); 533 setup_tlb_core_data(); 534 535 /* 536 * Freescale Book3e parts spin in a loop provided by firmware, 537 * so smp_release_cpus() does nothing for them 538 */ 539 #if defined(CONFIG_SMP) 540 /* Release secondary cpus out of their spinloops at 0x60 now that 541 * we can map physical -> logical CPU ids 542 */ 543 smp_release_cpus(); 544 #endif 545 546 pr_info("Starting Linux %s %s\n", init_utsname()->machine, 547 init_utsname()->version); 548 549 pr_info("-----------------------------------------------------\n"); 550 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 551 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); 552 553 if (ppc64_caches.dline_size != 0x80) 554 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); 555 if (ppc64_caches.iline_size != 0x80) 556 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); 557 558 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); 559 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); 560 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); 561 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, 562 cur_cpu_spec->cpu_user_features2); 563 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); 564 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); 565 566 #ifdef CONFIG_PPC_STD_MMU_64 567 if (htab_address) 568 pr_info("htab_address = 0x%p\n", htab_address); 569 570 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 571 #endif 572 573 if (PHYSICAL_START > 0) 574 pr_info("physical_start = 0x%llx\n", 575 (unsigned long long)PHYSICAL_START); 576 pr_info("-----------------------------------------------------\n"); 577 578 DBG(" <- setup_system()\n"); 579 } 580 581 /* This returns the limit below which memory accesses to the linear 582 * mapping are guarnateed not to cause a TLB or SLB miss. This is 583 * used to allocate interrupt or emergency stacks for which our 584 * exception entry path doesn't deal with being interrupted. 585 */ 586 static u64 safe_stack_limit(void) 587 { 588 #ifdef CONFIG_PPC_BOOK3E 589 /* Freescale BookE bolts the entire linear mapping */ 590 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 591 return linear_map_top; 592 /* Other BookE, we assume the first GB is bolted */ 593 return 1ul << 30; 594 #else 595 /* BookS, the first segment is bolted */ 596 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 597 return 1UL << SID_SHIFT_1T; 598 return 1UL << SID_SHIFT; 599 #endif 600 } 601 602 static void __init irqstack_early_init(void) 603 { 604 u64 limit = safe_stack_limit(); 605 unsigned int i; 606 607 /* 608 * Interrupt stacks must be in the first segment since we 609 * cannot afford to take SLB misses on them. 610 */ 611 for_each_possible_cpu(i) { 612 softirq_ctx[i] = (struct thread_info *) 613 __va(memblock_alloc_base(THREAD_SIZE, 614 THREAD_SIZE, limit)); 615 hardirq_ctx[i] = (struct thread_info *) 616 __va(memblock_alloc_base(THREAD_SIZE, 617 THREAD_SIZE, limit)); 618 } 619 } 620 621 #ifdef CONFIG_PPC_BOOK3E 622 static void __init exc_lvl_early_init(void) 623 { 624 unsigned int i; 625 unsigned long sp; 626 627 for_each_possible_cpu(i) { 628 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 629 critirq_ctx[i] = (struct thread_info *)__va(sp); 630 paca[i].crit_kstack = __va(sp + THREAD_SIZE); 631 632 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 633 dbgirq_ctx[i] = (struct thread_info *)__va(sp); 634 paca[i].dbg_kstack = __va(sp + THREAD_SIZE); 635 636 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 637 mcheckirq_ctx[i] = (struct thread_info *)__va(sp); 638 paca[i].mc_kstack = __va(sp + THREAD_SIZE); 639 } 640 641 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 642 patch_exception(0x040, exc_debug_debug_book3e); 643 } 644 #else 645 #define exc_lvl_early_init() 646 #endif 647 648 /* 649 * Stack space used when we detect a bad kernel stack pointer, and 650 * early in SMP boots before relocation is enabled. Exclusive emergency 651 * stack for machine checks. 652 */ 653 static void __init emergency_stack_init(void) 654 { 655 u64 limit; 656 unsigned int i; 657 658 /* 659 * Emergency stacks must be under 256MB, we cannot afford to take 660 * SLB misses on them. The ABI also requires them to be 128-byte 661 * aligned. 662 * 663 * Since we use these as temporary stacks during secondary CPU 664 * bringup, we need to get at them in real mode. This means they 665 * must also be within the RMO region. 666 */ 667 limit = min(safe_stack_limit(), ppc64_rma_size); 668 669 for_each_possible_cpu(i) { 670 unsigned long sp; 671 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 672 sp += THREAD_SIZE; 673 paca[i].emergency_sp = __va(sp); 674 675 #ifdef CONFIG_PPC_BOOK3S_64 676 /* emergency stack for machine check exception handling. */ 677 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 678 sp += THREAD_SIZE; 679 paca[i].mc_emergency_sp = __va(sp); 680 #endif 681 } 682 } 683 684 /* 685 * Called into from start_kernel this initializes memblock, which is used 686 * to manage page allocation until mem_init is called. 687 */ 688 void __init setup_arch(char **cmdline_p) 689 { 690 *cmdline_p = boot_command_line; 691 692 /* 693 * Set cache line size based on type of cpu as a default. 694 * Systems with OF can look in the properties on the cpu node(s) 695 * for a possibly more accurate value. 696 */ 697 dcache_bsize = ppc64_caches.dline_size; 698 icache_bsize = ppc64_caches.iline_size; 699 700 if (ppc_md.panic) 701 setup_panic(); 702 703 init_mm.start_code = (unsigned long)_stext; 704 init_mm.end_code = (unsigned long) _etext; 705 init_mm.end_data = (unsigned long) _edata; 706 init_mm.brk = klimit; 707 #ifdef CONFIG_PPC_64K_PAGES 708 init_mm.context.pte_frag = NULL; 709 #endif 710 #ifdef CONFIG_SPAPR_TCE_IOMMU 711 mm_iommu_init(&init_mm.context); 712 #endif 713 irqstack_early_init(); 714 exc_lvl_early_init(); 715 emergency_stack_init(); 716 717 initmem_init(); 718 719 #ifdef CONFIG_DUMMY_CONSOLE 720 conswitchp = &dummy_con; 721 #endif 722 723 if (ppc_md.setup_arch) 724 ppc_md.setup_arch(); 725 726 paging_init(); 727 728 /* Initialize the MMU context management stuff */ 729 mmu_context_init(); 730 731 /* Interrupt code needs to be 64K-aligned */ 732 if ((unsigned long)_stext & 0xffff) 733 panic("Kernelbase not 64K-aligned (0x%lx)!\n", 734 (unsigned long)_stext); 735 } 736 737 #ifdef CONFIG_SMP 738 #define PCPU_DYN_SIZE () 739 740 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 741 { 742 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 743 __pa(MAX_DMA_ADDRESS)); 744 } 745 746 static void __init pcpu_fc_free(void *ptr, size_t size) 747 { 748 free_bootmem(__pa(ptr), size); 749 } 750 751 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 752 { 753 if (cpu_to_node(from) == cpu_to_node(to)) 754 return LOCAL_DISTANCE; 755 else 756 return REMOTE_DISTANCE; 757 } 758 759 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 760 EXPORT_SYMBOL(__per_cpu_offset); 761 762 void __init setup_per_cpu_areas(void) 763 { 764 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 765 size_t atom_size; 766 unsigned long delta; 767 unsigned int cpu; 768 int rc; 769 770 /* 771 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 772 * to group units. For larger mappings, use 1M atom which 773 * should be large enough to contain a number of units. 774 */ 775 if (mmu_linear_psize == MMU_PAGE_4K) 776 atom_size = PAGE_SIZE; 777 else 778 atom_size = 1 << 20; 779 780 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 781 pcpu_fc_alloc, pcpu_fc_free); 782 if (rc < 0) 783 panic("cannot initialize percpu area (err=%d)", rc); 784 785 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 786 for_each_possible_cpu(cpu) { 787 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 788 paca[cpu].data_offset = __per_cpu_offset[cpu]; 789 } 790 } 791 #endif 792 793 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 794 unsigned long memory_block_size_bytes(void) 795 { 796 if (ppc_md.memory_block_size) 797 return ppc_md.memory_block_size(); 798 799 return MIN_MEMORY_BLOCK_SIZE; 800 } 801 #endif 802 803 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 804 struct ppc_pci_io ppc_pci_io; 805 EXPORT_SYMBOL(ppc_pci_io); 806 #endif 807 808 #ifdef CONFIG_HARDLOCKUP_DETECTOR 809 u64 hw_nmi_get_sample_period(int watchdog_thresh) 810 { 811 return ppc_proc_freq * watchdog_thresh; 812 } 813 814 /* 815 * The hardlockup detector breaks PMU event based branches and is likely 816 * to get false positives in KVM guests, so disable it by default. 817 */ 818 static int __init disable_hardlockup_detector(void) 819 { 820 hardlockup_detector_disable(); 821 822 return 0; 823 } 824 early_initcall(disable_hardlockup_detector); 825 #endif 826