1 /* 2 * Common prep/pmac/chrp boot and setup code. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/string.h> 7 #include <linux/sched.h> 8 #include <linux/init.h> 9 #include <linux/kernel.h> 10 #include <linux/reboot.h> 11 #include <linux/delay.h> 12 #include <linux/initrd.h> 13 #include <linux/tty.h> 14 #include <linux/seq_file.h> 15 #include <linux/root_dev.h> 16 #include <linux/cpu.h> 17 #include <linux/console.h> 18 #include <linux/memblock.h> 19 #include <linux/export.h> 20 21 #include <asm/io.h> 22 #include <asm/prom.h> 23 #include <asm/processor.h> 24 #include <asm/pgtable.h> 25 #include <asm/setup.h> 26 #include <asm/smp.h> 27 #include <asm/elf.h> 28 #include <asm/cputable.h> 29 #include <asm/bootx.h> 30 #include <asm/btext.h> 31 #include <asm/machdep.h> 32 #include <asm/uaccess.h> 33 #include <asm/pmac_feature.h> 34 #include <asm/sections.h> 35 #include <asm/nvram.h> 36 #include <asm/xmon.h> 37 #include <asm/time.h> 38 #include <asm/serial.h> 39 #include <asm/udbg.h> 40 #include <asm/code-patching.h> 41 #include <asm/cpu_has_feature.h> 42 43 #define DBG(fmt...) 44 45 extern void bootx_init(unsigned long r4, unsigned long phys); 46 47 int boot_cpuid_phys; 48 EXPORT_SYMBOL_GPL(boot_cpuid_phys); 49 50 int smp_hw_index[NR_CPUS]; 51 EXPORT_SYMBOL(smp_hw_index); 52 53 unsigned long ISA_DMA_THRESHOLD; 54 unsigned int DMA_MODE_READ; 55 unsigned int DMA_MODE_WRITE; 56 57 EXPORT_SYMBOL(ISA_DMA_THRESHOLD); 58 EXPORT_SYMBOL(DMA_MODE_READ); 59 EXPORT_SYMBOL(DMA_MODE_WRITE); 60 61 /* 62 * These are used in binfmt_elf.c to put aux entries on the stack 63 * for each elf executable being started. 64 */ 65 int dcache_bsize; 66 int icache_bsize; 67 int ucache_bsize; 68 69 /* 70 * We're called here very early in the boot. 71 * 72 * Note that the kernel may be running at an address which is different 73 * from the address that it was linked at, so we must use RELOC/PTRRELOC 74 * to access static data (including strings). -- paulus 75 */ 76 notrace unsigned long __init early_init(unsigned long dt_ptr) 77 { 78 unsigned long offset = reloc_offset(); 79 80 /* First zero the BSS -- use memset_io, some platforms don't have 81 * caches on yet */ 82 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, 83 __bss_stop - __bss_start); 84 85 /* 86 * Identify the CPU type and fix up code sections 87 * that depend on which cpu we have. 88 */ 89 identify_cpu(offset, mfspr(SPRN_PVR)); 90 91 apply_feature_fixups(); 92 93 return KERNELBASE + offset; 94 } 95 96 97 /* 98 * This is run before start_kernel(), the kernel has been relocated 99 * and we are running with enough of the MMU enabled to have our 100 * proper kernel virtual addresses 101 * 102 * We do the initial parsing of the flat device-tree and prepares 103 * for the MMU to be fully initialized. 104 */ 105 extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */ 106 107 notrace void __init machine_init(u64 dt_ptr) 108 { 109 /* Configure static keys first, now that we're relocated. */ 110 setup_feature_keys(); 111 112 /* Enable early debugging if any specified (see udbg.h) */ 113 udbg_early_init(); 114 115 patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP); 116 patch_instruction(&memset_nocache_branch, PPC_INST_NOP); 117 118 /* Do some early initialization based on the flat device tree */ 119 early_init_devtree(__va(dt_ptr)); 120 121 early_init_mmu(); 122 123 setup_kdump_trampoline(); 124 } 125 126 /* Checks "l2cr=xxxx" command-line option */ 127 int __init ppc_setup_l2cr(char *str) 128 { 129 if (cpu_has_feature(CPU_FTR_L2CR)) { 130 unsigned long val = simple_strtoul(str, NULL, 0); 131 printk(KERN_INFO "l2cr set to %lx\n", val); 132 _set_L2CR(0); /* force invalidate by disable cache */ 133 _set_L2CR(val); /* and enable it */ 134 } 135 return 1; 136 } 137 __setup("l2cr=", ppc_setup_l2cr); 138 139 /* Checks "l3cr=xxxx" command-line option */ 140 int __init ppc_setup_l3cr(char *str) 141 { 142 if (cpu_has_feature(CPU_FTR_L3CR)) { 143 unsigned long val = simple_strtoul(str, NULL, 0); 144 printk(KERN_INFO "l3cr set to %lx\n", val); 145 _set_L3CR(val); /* and enable it */ 146 } 147 return 1; 148 } 149 __setup("l3cr=", ppc_setup_l3cr); 150 151 #ifdef CONFIG_GENERIC_NVRAM 152 153 /* Generic nvram hooks used by drivers/char/gen_nvram.c */ 154 unsigned char nvram_read_byte(int addr) 155 { 156 if (ppc_md.nvram_read_val) 157 return ppc_md.nvram_read_val(addr); 158 return 0xff; 159 } 160 EXPORT_SYMBOL(nvram_read_byte); 161 162 void nvram_write_byte(unsigned char val, int addr) 163 { 164 if (ppc_md.nvram_write_val) 165 ppc_md.nvram_write_val(addr, val); 166 } 167 EXPORT_SYMBOL(nvram_write_byte); 168 169 ssize_t nvram_get_size(void) 170 { 171 if (ppc_md.nvram_size) 172 return ppc_md.nvram_size(); 173 return -1; 174 } 175 EXPORT_SYMBOL(nvram_get_size); 176 177 void nvram_sync(void) 178 { 179 if (ppc_md.nvram_sync) 180 ppc_md.nvram_sync(); 181 } 182 EXPORT_SYMBOL(nvram_sync); 183 184 #endif /* CONFIG_NVRAM */ 185 186 int __init ppc_init(void) 187 { 188 /* clear the progress line */ 189 if (ppc_md.progress) 190 ppc_md.progress(" ", 0xffff); 191 192 /* call platform init */ 193 if (ppc_md.init != NULL) { 194 ppc_md.init(); 195 } 196 return 0; 197 } 198 199 arch_initcall(ppc_init); 200 201 void __init irqstack_early_init(void) 202 { 203 unsigned int i; 204 205 /* interrupt stacks must be in lowmem, we get that for free on ppc32 206 * as the memblock is limited to lowmem by default */ 207 for_each_possible_cpu(i) { 208 softirq_ctx[i] = (struct thread_info *) 209 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 210 hardirq_ctx[i] = (struct thread_info *) 211 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 212 } 213 } 214 215 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 216 void __init exc_lvl_early_init(void) 217 { 218 unsigned int i, hw_cpu; 219 220 /* interrupt stacks must be in lowmem, we get that for free on ppc32 221 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ 222 for_each_possible_cpu(i) { 223 #ifdef CONFIG_SMP 224 hw_cpu = get_hard_smp_processor_id(i); 225 #else 226 hw_cpu = 0; 227 #endif 228 229 critirq_ctx[hw_cpu] = (struct thread_info *) 230 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 231 #ifdef CONFIG_BOOKE 232 dbgirq_ctx[hw_cpu] = (struct thread_info *) 233 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 234 mcheckirq_ctx[hw_cpu] = (struct thread_info *) 235 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 236 #endif 237 } 238 } 239 #endif 240 241 void __init setup_power_save(void) 242 { 243 #ifdef CONFIG_6xx 244 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 245 cpu_has_feature(CPU_FTR_CAN_NAP)) 246 ppc_md.power_save = ppc6xx_idle; 247 #endif 248 249 #ifdef CONFIG_E500 250 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 251 cpu_has_feature(CPU_FTR_CAN_NAP)) 252 ppc_md.power_save = e500_idle; 253 #endif 254 } 255 256 __init void initialize_cache_info(void) 257 { 258 /* 259 * Set cache line size based on type of cpu as a default. 260 * Systems with OF can look in the properties on the cpu node(s) 261 * for a possibly more accurate value. 262 */ 263 dcache_bsize = cur_cpu_spec->dcache_bsize; 264 icache_bsize = cur_cpu_spec->icache_bsize; 265 ucache_bsize = 0; 266 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) 267 ucache_bsize = icache_bsize = dcache_bsize; 268 } 269