1 /* 2 * Common prep/pmac/chrp boot and setup code. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/string.h> 7 #include <linux/sched.h> 8 #include <linux/init.h> 9 #include <linux/kernel.h> 10 #include <linux/reboot.h> 11 #include <linux/delay.h> 12 #include <linux/initrd.h> 13 #include <linux/tty.h> 14 #include <linux/seq_file.h> 15 #include <linux/root_dev.h> 16 #include <linux/cpu.h> 17 #include <linux/console.h> 18 #include <linux/memblock.h> 19 #include <linux/export.h> 20 21 #include <asm/io.h> 22 #include <asm/prom.h> 23 #include <asm/processor.h> 24 #include <asm/pgtable.h> 25 #include <asm/setup.h> 26 #include <asm/smp.h> 27 #include <asm/elf.h> 28 #include <asm/cputable.h> 29 #include <asm/bootx.h> 30 #include <asm/btext.h> 31 #include <asm/machdep.h> 32 #include <linux/uaccess.h> 33 #include <asm/pmac_feature.h> 34 #include <asm/sections.h> 35 #include <asm/nvram.h> 36 #include <asm/xmon.h> 37 #include <asm/time.h> 38 #include <asm/serial.h> 39 #include <asm/udbg.h> 40 #include <asm/code-patching.h> 41 #include <asm/cpu_has_feature.h> 42 #include <asm/asm-prototypes.h> 43 #include <asm/kdump.h> 44 #include <asm/feature-fixups.h> 45 46 #include "setup.h" 47 48 #define DBG(fmt...) 49 50 extern void bootx_init(unsigned long r4, unsigned long phys); 51 52 int boot_cpuid_phys; 53 EXPORT_SYMBOL_GPL(boot_cpuid_phys); 54 55 int smp_hw_index[NR_CPUS]; 56 EXPORT_SYMBOL(smp_hw_index); 57 58 unsigned long ISA_DMA_THRESHOLD; 59 unsigned int DMA_MODE_READ; 60 unsigned int DMA_MODE_WRITE; 61 62 EXPORT_SYMBOL(DMA_MODE_READ); 63 EXPORT_SYMBOL(DMA_MODE_WRITE); 64 65 /* 66 * We're called here very early in the boot. 67 * 68 * Note that the kernel may be running at an address which is different 69 * from the address that it was linked at, so we must use RELOC/PTRRELOC 70 * to access static data (including strings). -- paulus 71 */ 72 notrace unsigned long __init early_init(unsigned long dt_ptr) 73 { 74 unsigned long offset = reloc_offset(); 75 76 /* First zero the BSS -- use memset_io, some platforms don't have 77 * caches on yet */ 78 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, 79 __bss_stop - __bss_start); 80 81 /* 82 * Identify the CPU type and fix up code sections 83 * that depend on which cpu we have. 84 */ 85 identify_cpu(offset, mfspr(SPRN_PVR)); 86 87 apply_feature_fixups(); 88 89 return KERNELBASE + offset; 90 } 91 92 93 /* 94 * This is run before start_kernel(), the kernel has been relocated 95 * and we are running with enough of the MMU enabled to have our 96 * proper kernel virtual addresses 97 * 98 * We do the initial parsing of the flat device-tree and prepares 99 * for the MMU to be fully initialized. 100 */ 101 notrace void __init machine_init(u64 dt_ptr) 102 { 103 unsigned int *addr = (unsigned int *)patch_site_addr(&patch__memset_nocache); 104 unsigned long insn; 105 106 /* Configure static keys first, now that we're relocated. */ 107 setup_feature_keys(); 108 109 /* Enable early debugging if any specified (see udbg.h) */ 110 udbg_early_init(); 111 112 patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP); 113 114 insn = create_cond_branch(addr, branch_target(addr), 0x820000); 115 patch_instruction(addr, insn); /* replace b by bne cr0 */ 116 117 /* Do some early initialization based on the flat device tree */ 118 early_init_devtree(__va(dt_ptr)); 119 120 early_init_mmu(); 121 122 setup_kdump_trampoline(); 123 } 124 125 /* Checks "l2cr=xxxx" command-line option */ 126 static int __init ppc_setup_l2cr(char *str) 127 { 128 if (cpu_has_feature(CPU_FTR_L2CR)) { 129 unsigned long val = simple_strtoul(str, NULL, 0); 130 printk(KERN_INFO "l2cr set to %lx\n", val); 131 _set_L2CR(0); /* force invalidate by disable cache */ 132 _set_L2CR(val); /* and enable it */ 133 } 134 return 1; 135 } 136 __setup("l2cr=", ppc_setup_l2cr); 137 138 /* Checks "l3cr=xxxx" command-line option */ 139 static int __init ppc_setup_l3cr(char *str) 140 { 141 if (cpu_has_feature(CPU_FTR_L3CR)) { 142 unsigned long val = simple_strtoul(str, NULL, 0); 143 printk(KERN_INFO "l3cr set to %lx\n", val); 144 _set_L3CR(val); /* and enable it */ 145 } 146 return 1; 147 } 148 __setup("l3cr=", ppc_setup_l3cr); 149 150 #ifdef CONFIG_GENERIC_NVRAM 151 152 /* Generic nvram hooks used by drivers/char/gen_nvram.c */ 153 unsigned char nvram_read_byte(int addr) 154 { 155 if (ppc_md.nvram_read_val) 156 return ppc_md.nvram_read_val(addr); 157 return 0xff; 158 } 159 EXPORT_SYMBOL(nvram_read_byte); 160 161 void nvram_write_byte(unsigned char val, int addr) 162 { 163 if (ppc_md.nvram_write_val) 164 ppc_md.nvram_write_val(addr, val); 165 } 166 EXPORT_SYMBOL(nvram_write_byte); 167 168 ssize_t nvram_get_size(void) 169 { 170 if (ppc_md.nvram_size) 171 return ppc_md.nvram_size(); 172 return -1; 173 } 174 EXPORT_SYMBOL(nvram_get_size); 175 176 void nvram_sync(void) 177 { 178 if (ppc_md.nvram_sync) 179 ppc_md.nvram_sync(); 180 } 181 EXPORT_SYMBOL(nvram_sync); 182 183 #endif /* CONFIG_NVRAM */ 184 185 static int __init ppc_init(void) 186 { 187 /* clear the progress line */ 188 if (ppc_md.progress) 189 ppc_md.progress(" ", 0xffff); 190 191 /* call platform init */ 192 if (ppc_md.init != NULL) { 193 ppc_md.init(); 194 } 195 return 0; 196 } 197 arch_initcall(ppc_init); 198 199 void __init irqstack_early_init(void) 200 { 201 unsigned int i; 202 203 /* interrupt stacks must be in lowmem, we get that for free on ppc32 204 * as the memblock is limited to lowmem by default */ 205 for_each_possible_cpu(i) { 206 softirq_ctx[i] = (struct thread_info *) 207 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 208 hardirq_ctx[i] = (struct thread_info *) 209 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 210 } 211 } 212 213 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 214 void __init exc_lvl_early_init(void) 215 { 216 unsigned int i, hw_cpu; 217 218 /* interrupt stacks must be in lowmem, we get that for free on ppc32 219 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ 220 for_each_possible_cpu(i) { 221 #ifdef CONFIG_SMP 222 hw_cpu = get_hard_smp_processor_id(i); 223 #else 224 hw_cpu = 0; 225 #endif 226 227 critirq_ctx[hw_cpu] = (struct thread_info *) 228 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 229 #ifdef CONFIG_BOOKE 230 dbgirq_ctx[hw_cpu] = (struct thread_info *) 231 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 232 mcheckirq_ctx[hw_cpu] = (struct thread_info *) 233 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 234 #endif 235 } 236 } 237 #endif 238 239 void __init setup_power_save(void) 240 { 241 #ifdef CONFIG_PPC_BOOK3S_32 242 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 243 cpu_has_feature(CPU_FTR_CAN_NAP)) 244 ppc_md.power_save = ppc6xx_idle; 245 #endif 246 247 #ifdef CONFIG_E500 248 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 249 cpu_has_feature(CPU_FTR_CAN_NAP)) 250 ppc_md.power_save = e500_idle; 251 #endif 252 } 253 254 __init void initialize_cache_info(void) 255 { 256 /* 257 * Set cache line size based on type of cpu as a default. 258 * Systems with OF can look in the properties on the cpu node(s) 259 * for a possibly more accurate value. 260 */ 261 dcache_bsize = cur_cpu_spec->dcache_bsize; 262 icache_bsize = cur_cpu_spec->icache_bsize; 263 ucache_bsize = 0; 264 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) 265 ucache_bsize = icache_bsize = dcache_bsize; 266 } 267