1 /* 2 * Common prep/pmac/chrp boot and setup code. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/string.h> 7 #include <linux/sched.h> 8 #include <linux/init.h> 9 #include <linux/kernel.h> 10 #include <linux/reboot.h> 11 #include <linux/delay.h> 12 #include <linux/initrd.h> 13 #include <linux/tty.h> 14 #include <linux/seq_file.h> 15 #include <linux/root_dev.h> 16 #include <linux/cpu.h> 17 #include <linux/console.h> 18 #include <linux/memblock.h> 19 #include <linux/export.h> 20 #include <linux/nvram.h> 21 22 #include <asm/io.h> 23 #include <asm/prom.h> 24 #include <asm/processor.h> 25 #include <asm/pgtable.h> 26 #include <asm/setup.h> 27 #include <asm/smp.h> 28 #include <asm/elf.h> 29 #include <asm/cputable.h> 30 #include <asm/bootx.h> 31 #include <asm/btext.h> 32 #include <asm/machdep.h> 33 #include <linux/uaccess.h> 34 #include <asm/pmac_feature.h> 35 #include <asm/sections.h> 36 #include <asm/nvram.h> 37 #include <asm/xmon.h> 38 #include <asm/time.h> 39 #include <asm/serial.h> 40 #include <asm/udbg.h> 41 #include <asm/code-patching.h> 42 #include <asm/cpu_has_feature.h> 43 #include <asm/asm-prototypes.h> 44 #include <asm/kdump.h> 45 #include <asm/feature-fixups.h> 46 47 #include "setup.h" 48 49 #define DBG(fmt...) 50 51 extern void bootx_init(unsigned long r4, unsigned long phys); 52 53 int boot_cpuid_phys; 54 EXPORT_SYMBOL_GPL(boot_cpuid_phys); 55 56 int smp_hw_index[NR_CPUS]; 57 EXPORT_SYMBOL(smp_hw_index); 58 59 unsigned long ISA_DMA_THRESHOLD; 60 unsigned int DMA_MODE_READ; 61 unsigned int DMA_MODE_WRITE; 62 63 EXPORT_SYMBOL(DMA_MODE_READ); 64 EXPORT_SYMBOL(DMA_MODE_WRITE); 65 66 /* 67 * We're called here very early in the boot. 68 * 69 * Note that the kernel may be running at an address which is different 70 * from the address that it was linked at, so we must use RELOC/PTRRELOC 71 * to access static data (including strings). -- paulus 72 */ 73 notrace unsigned long __init early_init(unsigned long dt_ptr) 74 { 75 unsigned long offset = reloc_offset(); 76 77 /* First zero the BSS -- use memset_io, some platforms don't have 78 * caches on yet */ 79 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, 80 __bss_stop - __bss_start); 81 82 /* 83 * Identify the CPU type and fix up code sections 84 * that depend on which cpu we have. 85 */ 86 identify_cpu(offset, mfspr(SPRN_PVR)); 87 88 apply_feature_fixups(); 89 90 return KERNELBASE + offset; 91 } 92 93 94 /* 95 * This is run before start_kernel(), the kernel has been relocated 96 * and we are running with enough of the MMU enabled to have our 97 * proper kernel virtual addresses 98 * 99 * We do the initial parsing of the flat device-tree and prepares 100 * for the MMU to be fully initialized. 101 */ 102 notrace void __init machine_init(u64 dt_ptr) 103 { 104 unsigned int *addr = (unsigned int *)patch_site_addr(&patch__memset_nocache); 105 unsigned long insn; 106 107 /* Configure static keys first, now that we're relocated. */ 108 setup_feature_keys(); 109 110 /* Enable early debugging if any specified (see udbg.h) */ 111 udbg_early_init(); 112 113 patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP); 114 115 insn = create_cond_branch(addr, branch_target(addr), 0x820000); 116 patch_instruction(addr, insn); /* replace b by bne cr0 */ 117 118 /* Do some early initialization based on the flat device tree */ 119 early_init_devtree(__va(dt_ptr)); 120 121 early_init_mmu(); 122 123 setup_kdump_trampoline(); 124 } 125 126 /* Checks "l2cr=xxxx" command-line option */ 127 static int __init ppc_setup_l2cr(char *str) 128 { 129 if (cpu_has_feature(CPU_FTR_L2CR)) { 130 unsigned long val = simple_strtoul(str, NULL, 0); 131 printk(KERN_INFO "l2cr set to %lx\n", val); 132 _set_L2CR(0); /* force invalidate by disable cache */ 133 _set_L2CR(val); /* and enable it */ 134 } 135 return 1; 136 } 137 __setup("l2cr=", ppc_setup_l2cr); 138 139 /* Checks "l3cr=xxxx" command-line option */ 140 static int __init ppc_setup_l3cr(char *str) 141 { 142 if (cpu_has_feature(CPU_FTR_L3CR)) { 143 unsigned long val = simple_strtoul(str, NULL, 0); 144 printk(KERN_INFO "l3cr set to %lx\n", val); 145 _set_L3CR(val); /* and enable it */ 146 } 147 return 1; 148 } 149 __setup("l3cr=", ppc_setup_l3cr); 150 151 static int __init ppc_init(void) 152 { 153 /* clear the progress line */ 154 if (ppc_md.progress) 155 ppc_md.progress(" ", 0xffff); 156 157 /* call platform init */ 158 if (ppc_md.init != NULL) { 159 ppc_md.init(); 160 } 161 return 0; 162 } 163 arch_initcall(ppc_init); 164 165 void __init irqstack_early_init(void) 166 { 167 unsigned int i; 168 169 /* interrupt stacks must be in lowmem, we get that for free on ppc32 170 * as the memblock is limited to lowmem by default */ 171 for_each_possible_cpu(i) { 172 softirq_ctx[i] = (struct thread_info *) 173 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 174 hardirq_ctx[i] = (struct thread_info *) 175 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 176 } 177 } 178 179 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 180 void __init exc_lvl_early_init(void) 181 { 182 unsigned int i, hw_cpu; 183 184 /* interrupt stacks must be in lowmem, we get that for free on ppc32 185 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ 186 for_each_possible_cpu(i) { 187 #ifdef CONFIG_SMP 188 hw_cpu = get_hard_smp_processor_id(i); 189 #else 190 hw_cpu = 0; 191 #endif 192 193 critirq_ctx[hw_cpu] = (struct thread_info *) 194 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 195 #ifdef CONFIG_BOOKE 196 dbgirq_ctx[hw_cpu] = (struct thread_info *) 197 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 198 mcheckirq_ctx[hw_cpu] = (struct thread_info *) 199 __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); 200 #endif 201 } 202 } 203 #endif 204 205 void __init setup_power_save(void) 206 { 207 #ifdef CONFIG_PPC_BOOK3S_32 208 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 209 cpu_has_feature(CPU_FTR_CAN_NAP)) 210 ppc_md.power_save = ppc6xx_idle; 211 #endif 212 213 #ifdef CONFIG_E500 214 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 215 cpu_has_feature(CPU_FTR_CAN_NAP)) 216 ppc_md.power_save = e500_idle; 217 #endif 218 } 219 220 __init void initialize_cache_info(void) 221 { 222 /* 223 * Set cache line size based on type of cpu as a default. 224 * Systems with OF can look in the properties on the cpu node(s) 225 * for a possibly more accurate value. 226 */ 227 dcache_bsize = cur_cpu_spec->dcache_bsize; 228 icache_bsize = cur_cpu_spec->icache_bsize; 229 ucache_bsize = 0; 230 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) 231 ucache_bsize = icache_bsize = dcache_bsize; 232 } 233