1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/sched/debug.h> 20 #include <linux/sched/task.h> 21 #include <linux/sched/task_stack.h> 22 #include <linux/kernel.h> 23 #include <linux/mm.h> 24 #include <linux/smp.h> 25 #include <linux/stddef.h> 26 #include <linux/unistd.h> 27 #include <linux/ptrace.h> 28 #include <linux/slab.h> 29 #include <linux/user.h> 30 #include <linux/elf.h> 31 #include <linux/prctl.h> 32 #include <linux/init_task.h> 33 #include <linux/export.h> 34 #include <linux/kallsyms.h> 35 #include <linux/mqueue.h> 36 #include <linux/hardirq.h> 37 #include <linux/utsname.h> 38 #include <linux/ftrace.h> 39 #include <linux/kernel_stat.h> 40 #include <linux/personality.h> 41 #include <linux/random.h> 42 #include <linux/hw_breakpoint.h> 43 #include <linux/uaccess.h> 44 #include <linux/elf-randomize.h> 45 #include <linux/pkeys.h> 46 47 #include <asm/pgtable.h> 48 #include <asm/io.h> 49 #include <asm/processor.h> 50 #include <asm/mmu.h> 51 #include <asm/prom.h> 52 #include <asm/machdep.h> 53 #include <asm/time.h> 54 #include <asm/runlatch.h> 55 #include <asm/syscalls.h> 56 #include <asm/switch_to.h> 57 #include <asm/tm.h> 58 #include <asm/debug.h> 59 #ifdef CONFIG_PPC64 60 #include <asm/firmware.h> 61 #include <asm/hw_irq.h> 62 #endif 63 #include <asm/code-patching.h> 64 #include <asm/exec.h> 65 #include <asm/livepatch.h> 66 #include <asm/cpu_has_feature.h> 67 #include <asm/asm-prototypes.h> 68 69 #include <linux/kprobes.h> 70 #include <linux/kdebug.h> 71 72 /* Transactional Memory debug */ 73 #ifdef TM_DEBUG_SW 74 #define TM_DEBUG(x...) printk(KERN_INFO x) 75 #else 76 #define TM_DEBUG(x...) do { } while(0) 77 #endif 78 79 extern unsigned long _get_SP(void); 80 81 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 82 /* 83 * Are we running in "Suspend disabled" mode? If so we have to block any 84 * sigreturn that would get us into suspended state, and we also warn in some 85 * other paths that we should never reach with suspend disabled. 86 */ 87 bool tm_suspend_disabled __ro_after_init = false; 88 89 static void check_if_tm_restore_required(struct task_struct *tsk) 90 { 91 /* 92 * If we are saving the current thread's registers, and the 93 * thread is in a transactional state, set the TIF_RESTORE_TM 94 * bit so that we know to restore the registers before 95 * returning to userspace. 96 */ 97 if (tsk == current && tsk->thread.regs && 98 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 99 !test_thread_flag(TIF_RESTORE_TM)) { 100 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 101 set_thread_flag(TIF_RESTORE_TM); 102 } 103 } 104 105 static inline bool msr_tm_active(unsigned long msr) 106 { 107 return MSR_TM_ACTIVE(msr); 108 } 109 110 static bool tm_active_with_fp(struct task_struct *tsk) 111 { 112 return msr_tm_active(tsk->thread.regs->msr) && 113 (tsk->thread.ckpt_regs.msr & MSR_FP); 114 } 115 116 static bool tm_active_with_altivec(struct task_struct *tsk) 117 { 118 return msr_tm_active(tsk->thread.regs->msr) && 119 (tsk->thread.ckpt_regs.msr & MSR_VEC); 120 } 121 #else 122 static inline bool msr_tm_active(unsigned long msr) { return false; } 123 static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 124 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; } 125 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; } 126 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 127 128 bool strict_msr_control; 129 EXPORT_SYMBOL(strict_msr_control); 130 131 static int __init enable_strict_msr_control(char *str) 132 { 133 strict_msr_control = true; 134 pr_info("Enabling strict facility control\n"); 135 136 return 0; 137 } 138 early_param("ppc_strict_facility_enable", enable_strict_msr_control); 139 140 unsigned long msr_check_and_set(unsigned long bits) 141 { 142 unsigned long oldmsr = mfmsr(); 143 unsigned long newmsr; 144 145 newmsr = oldmsr | bits; 146 147 #ifdef CONFIG_VSX 148 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 149 newmsr |= MSR_VSX; 150 #endif 151 152 if (oldmsr != newmsr) 153 mtmsr_isync(newmsr); 154 155 return newmsr; 156 } 157 EXPORT_SYMBOL_GPL(msr_check_and_set); 158 159 void __msr_check_and_clear(unsigned long bits) 160 { 161 unsigned long oldmsr = mfmsr(); 162 unsigned long newmsr; 163 164 newmsr = oldmsr & ~bits; 165 166 #ifdef CONFIG_VSX 167 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 168 newmsr &= ~MSR_VSX; 169 #endif 170 171 if (oldmsr != newmsr) 172 mtmsr_isync(newmsr); 173 } 174 EXPORT_SYMBOL(__msr_check_and_clear); 175 176 #ifdef CONFIG_PPC_FPU 177 static void __giveup_fpu(struct task_struct *tsk) 178 { 179 unsigned long msr; 180 181 save_fpu(tsk); 182 msr = tsk->thread.regs->msr; 183 msr &= ~MSR_FP; 184 #ifdef CONFIG_VSX 185 if (cpu_has_feature(CPU_FTR_VSX)) 186 msr &= ~MSR_VSX; 187 #endif 188 tsk->thread.regs->msr = msr; 189 } 190 191 void giveup_fpu(struct task_struct *tsk) 192 { 193 check_if_tm_restore_required(tsk); 194 195 msr_check_and_set(MSR_FP); 196 __giveup_fpu(tsk); 197 msr_check_and_clear(MSR_FP); 198 } 199 EXPORT_SYMBOL(giveup_fpu); 200 201 /* 202 * Make sure the floating-point register state in the 203 * the thread_struct is up to date for task tsk. 204 */ 205 void flush_fp_to_thread(struct task_struct *tsk) 206 { 207 if (tsk->thread.regs) { 208 /* 209 * We need to disable preemption here because if we didn't, 210 * another process could get scheduled after the regs->msr 211 * test but before we have finished saving the FP registers 212 * to the thread_struct. That process could take over the 213 * FPU, and then when we get scheduled again we would store 214 * bogus values for the remaining FP registers. 215 */ 216 preempt_disable(); 217 if (tsk->thread.regs->msr & MSR_FP) { 218 /* 219 * This should only ever be called for current or 220 * for a stopped child process. Since we save away 221 * the FP register state on context switch, 222 * there is something wrong if a stopped child appears 223 * to still have its FP state in the CPU registers. 224 */ 225 BUG_ON(tsk != current); 226 giveup_fpu(tsk); 227 } 228 preempt_enable(); 229 } 230 } 231 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 232 233 void enable_kernel_fp(void) 234 { 235 unsigned long cpumsr; 236 237 WARN_ON(preemptible()); 238 239 cpumsr = msr_check_and_set(MSR_FP); 240 241 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 242 check_if_tm_restore_required(current); 243 /* 244 * If a thread has already been reclaimed then the 245 * checkpointed registers are on the CPU but have definitely 246 * been saved by the reclaim code. Don't need to and *cannot* 247 * giveup as this would save to the 'live' structure not the 248 * checkpointed structure. 249 */ 250 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 251 return; 252 __giveup_fpu(current); 253 } 254 } 255 EXPORT_SYMBOL(enable_kernel_fp); 256 257 static int restore_fp(struct task_struct *tsk) 258 { 259 if (tsk->thread.load_fp || tm_active_with_fp(tsk)) { 260 load_fp_state(¤t->thread.fp_state); 261 current->thread.load_fp++; 262 return 1; 263 } 264 return 0; 265 } 266 #else 267 static int restore_fp(struct task_struct *tsk) { return 0; } 268 #endif /* CONFIG_PPC_FPU */ 269 270 #ifdef CONFIG_ALTIVEC 271 #define loadvec(thr) ((thr).load_vec) 272 273 static void __giveup_altivec(struct task_struct *tsk) 274 { 275 unsigned long msr; 276 277 save_altivec(tsk); 278 msr = tsk->thread.regs->msr; 279 msr &= ~MSR_VEC; 280 #ifdef CONFIG_VSX 281 if (cpu_has_feature(CPU_FTR_VSX)) 282 msr &= ~MSR_VSX; 283 #endif 284 tsk->thread.regs->msr = msr; 285 } 286 287 void giveup_altivec(struct task_struct *tsk) 288 { 289 check_if_tm_restore_required(tsk); 290 291 msr_check_and_set(MSR_VEC); 292 __giveup_altivec(tsk); 293 msr_check_and_clear(MSR_VEC); 294 } 295 EXPORT_SYMBOL(giveup_altivec); 296 297 void enable_kernel_altivec(void) 298 { 299 unsigned long cpumsr; 300 301 WARN_ON(preemptible()); 302 303 cpumsr = msr_check_and_set(MSR_VEC); 304 305 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 306 check_if_tm_restore_required(current); 307 /* 308 * If a thread has already been reclaimed then the 309 * checkpointed registers are on the CPU but have definitely 310 * been saved by the reclaim code. Don't need to and *cannot* 311 * giveup as this would save to the 'live' structure not the 312 * checkpointed structure. 313 */ 314 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 315 return; 316 __giveup_altivec(current); 317 } 318 } 319 EXPORT_SYMBOL(enable_kernel_altivec); 320 321 /* 322 * Make sure the VMX/Altivec register state in the 323 * the thread_struct is up to date for task tsk. 324 */ 325 void flush_altivec_to_thread(struct task_struct *tsk) 326 { 327 if (tsk->thread.regs) { 328 preempt_disable(); 329 if (tsk->thread.regs->msr & MSR_VEC) { 330 BUG_ON(tsk != current); 331 giveup_altivec(tsk); 332 } 333 preempt_enable(); 334 } 335 } 336 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 337 338 static int restore_altivec(struct task_struct *tsk) 339 { 340 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 341 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) { 342 load_vr_state(&tsk->thread.vr_state); 343 tsk->thread.used_vr = 1; 344 tsk->thread.load_vec++; 345 346 return 1; 347 } 348 return 0; 349 } 350 #else 351 #define loadvec(thr) 0 352 static inline int restore_altivec(struct task_struct *tsk) { return 0; } 353 #endif /* CONFIG_ALTIVEC */ 354 355 #ifdef CONFIG_VSX 356 static void __giveup_vsx(struct task_struct *tsk) 357 { 358 unsigned long msr = tsk->thread.regs->msr; 359 360 /* 361 * We should never be ssetting MSR_VSX without also setting 362 * MSR_FP and MSR_VEC 363 */ 364 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 365 366 /* __giveup_fpu will clear MSR_VSX */ 367 if (msr & MSR_FP) 368 __giveup_fpu(tsk); 369 if (msr & MSR_VEC) 370 __giveup_altivec(tsk); 371 } 372 373 static void giveup_vsx(struct task_struct *tsk) 374 { 375 check_if_tm_restore_required(tsk); 376 377 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 378 __giveup_vsx(tsk); 379 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 380 } 381 382 void enable_kernel_vsx(void) 383 { 384 unsigned long cpumsr; 385 386 WARN_ON(preemptible()); 387 388 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 389 390 if (current->thread.regs && 391 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { 392 check_if_tm_restore_required(current); 393 /* 394 * If a thread has already been reclaimed then the 395 * checkpointed registers are on the CPU but have definitely 396 * been saved by the reclaim code. Don't need to and *cannot* 397 * giveup as this would save to the 'live' structure not the 398 * checkpointed structure. 399 */ 400 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 401 return; 402 __giveup_vsx(current); 403 } 404 } 405 EXPORT_SYMBOL(enable_kernel_vsx); 406 407 void flush_vsx_to_thread(struct task_struct *tsk) 408 { 409 if (tsk->thread.regs) { 410 preempt_disable(); 411 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { 412 BUG_ON(tsk != current); 413 giveup_vsx(tsk); 414 } 415 preempt_enable(); 416 } 417 } 418 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 419 420 static int restore_vsx(struct task_struct *tsk) 421 { 422 if (cpu_has_feature(CPU_FTR_VSX)) { 423 tsk->thread.used_vsr = 1; 424 return 1; 425 } 426 427 return 0; 428 } 429 #else 430 static inline int restore_vsx(struct task_struct *tsk) { return 0; } 431 #endif /* CONFIG_VSX */ 432 433 #ifdef CONFIG_SPE 434 void giveup_spe(struct task_struct *tsk) 435 { 436 check_if_tm_restore_required(tsk); 437 438 msr_check_and_set(MSR_SPE); 439 __giveup_spe(tsk); 440 msr_check_and_clear(MSR_SPE); 441 } 442 EXPORT_SYMBOL(giveup_spe); 443 444 void enable_kernel_spe(void) 445 { 446 WARN_ON(preemptible()); 447 448 msr_check_and_set(MSR_SPE); 449 450 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 451 check_if_tm_restore_required(current); 452 __giveup_spe(current); 453 } 454 } 455 EXPORT_SYMBOL(enable_kernel_spe); 456 457 void flush_spe_to_thread(struct task_struct *tsk) 458 { 459 if (tsk->thread.regs) { 460 preempt_disable(); 461 if (tsk->thread.regs->msr & MSR_SPE) { 462 BUG_ON(tsk != current); 463 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 464 giveup_spe(tsk); 465 } 466 preempt_enable(); 467 } 468 } 469 #endif /* CONFIG_SPE */ 470 471 static unsigned long msr_all_available; 472 473 static int __init init_msr_all_available(void) 474 { 475 #ifdef CONFIG_PPC_FPU 476 msr_all_available |= MSR_FP; 477 #endif 478 #ifdef CONFIG_ALTIVEC 479 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 480 msr_all_available |= MSR_VEC; 481 #endif 482 #ifdef CONFIG_VSX 483 if (cpu_has_feature(CPU_FTR_VSX)) 484 msr_all_available |= MSR_VSX; 485 #endif 486 #ifdef CONFIG_SPE 487 if (cpu_has_feature(CPU_FTR_SPE)) 488 msr_all_available |= MSR_SPE; 489 #endif 490 491 return 0; 492 } 493 early_initcall(init_msr_all_available); 494 495 void giveup_all(struct task_struct *tsk) 496 { 497 unsigned long usermsr; 498 499 if (!tsk->thread.regs) 500 return; 501 502 usermsr = tsk->thread.regs->msr; 503 504 if ((usermsr & msr_all_available) == 0) 505 return; 506 507 msr_check_and_set(msr_all_available); 508 check_if_tm_restore_required(tsk); 509 510 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 511 512 #ifdef CONFIG_PPC_FPU 513 if (usermsr & MSR_FP) 514 __giveup_fpu(tsk); 515 #endif 516 #ifdef CONFIG_ALTIVEC 517 if (usermsr & MSR_VEC) 518 __giveup_altivec(tsk); 519 #endif 520 #ifdef CONFIG_SPE 521 if (usermsr & MSR_SPE) 522 __giveup_spe(tsk); 523 #endif 524 525 msr_check_and_clear(msr_all_available); 526 } 527 EXPORT_SYMBOL(giveup_all); 528 529 void restore_math(struct pt_regs *regs) 530 { 531 unsigned long msr; 532 533 if (!msr_tm_active(regs->msr) && 534 !current->thread.load_fp && !loadvec(current->thread)) 535 return; 536 537 msr = regs->msr; 538 msr_check_and_set(msr_all_available); 539 540 /* 541 * Only reload if the bit is not set in the user MSR, the bit BEING set 542 * indicates that the registers are hot 543 */ 544 if ((!(msr & MSR_FP)) && restore_fp(current)) 545 msr |= MSR_FP | current->thread.fpexc_mode; 546 547 if ((!(msr & MSR_VEC)) && restore_altivec(current)) 548 msr |= MSR_VEC; 549 550 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && 551 restore_vsx(current)) { 552 msr |= MSR_VSX; 553 } 554 555 msr_check_and_clear(msr_all_available); 556 557 regs->msr = msr; 558 } 559 560 static void save_all(struct task_struct *tsk) 561 { 562 unsigned long usermsr; 563 564 if (!tsk->thread.regs) 565 return; 566 567 usermsr = tsk->thread.regs->msr; 568 569 if ((usermsr & msr_all_available) == 0) 570 return; 571 572 msr_check_and_set(msr_all_available); 573 574 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 575 576 if (usermsr & MSR_FP) 577 save_fpu(tsk); 578 579 if (usermsr & MSR_VEC) 580 save_altivec(tsk); 581 582 if (usermsr & MSR_SPE) 583 __giveup_spe(tsk); 584 585 msr_check_and_clear(msr_all_available); 586 } 587 588 void flush_all_to_thread(struct task_struct *tsk) 589 { 590 if (tsk->thread.regs) { 591 preempt_disable(); 592 BUG_ON(tsk != current); 593 save_all(tsk); 594 595 #ifdef CONFIG_SPE 596 if (tsk->thread.regs->msr & MSR_SPE) 597 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 598 #endif 599 600 preempt_enable(); 601 } 602 } 603 EXPORT_SYMBOL(flush_all_to_thread); 604 605 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 606 void do_send_trap(struct pt_regs *regs, unsigned long address, 607 unsigned long error_code, int breakpt) 608 { 609 current->thread.trap_nr = TRAP_HWBKPT; 610 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 611 11, SIGSEGV) == NOTIFY_STOP) 612 return; 613 614 /* Deliver the signal to userspace */ 615 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ 616 (void __user *)address); 617 } 618 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 619 void do_break (struct pt_regs *regs, unsigned long address, 620 unsigned long error_code) 621 { 622 siginfo_t info; 623 624 current->thread.trap_nr = TRAP_HWBKPT; 625 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 626 11, SIGSEGV) == NOTIFY_STOP) 627 return; 628 629 if (debugger_break_match(regs)) 630 return; 631 632 /* Clear the breakpoint */ 633 hw_breakpoint_disable(); 634 635 /* Deliver the signal to userspace */ 636 clear_siginfo(&info); 637 info.si_signo = SIGTRAP; 638 info.si_errno = 0; 639 info.si_code = TRAP_HWBKPT; 640 info.si_addr = (void __user *)address; 641 force_sig_info(SIGTRAP, &info, current); 642 } 643 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 644 645 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 646 647 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 648 /* 649 * Set the debug registers back to their default "safe" values. 650 */ 651 static void set_debug_reg_defaults(struct thread_struct *thread) 652 { 653 thread->debug.iac1 = thread->debug.iac2 = 0; 654 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 655 thread->debug.iac3 = thread->debug.iac4 = 0; 656 #endif 657 thread->debug.dac1 = thread->debug.dac2 = 0; 658 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 659 thread->debug.dvc1 = thread->debug.dvc2 = 0; 660 #endif 661 thread->debug.dbcr0 = 0; 662 #ifdef CONFIG_BOOKE 663 /* 664 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 665 */ 666 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 667 DBCR1_IAC3US | DBCR1_IAC4US; 668 /* 669 * Force Data Address Compare User/Supervisor bits to be User-only 670 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 671 */ 672 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 673 #else 674 thread->debug.dbcr1 = 0; 675 #endif 676 } 677 678 static void prime_debug_regs(struct debug_reg *debug) 679 { 680 /* 681 * We could have inherited MSR_DE from userspace, since 682 * it doesn't get cleared on exception entry. Make sure 683 * MSR_DE is clear before we enable any debug events. 684 */ 685 mtmsr(mfmsr() & ~MSR_DE); 686 687 mtspr(SPRN_IAC1, debug->iac1); 688 mtspr(SPRN_IAC2, debug->iac2); 689 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 690 mtspr(SPRN_IAC3, debug->iac3); 691 mtspr(SPRN_IAC4, debug->iac4); 692 #endif 693 mtspr(SPRN_DAC1, debug->dac1); 694 mtspr(SPRN_DAC2, debug->dac2); 695 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 696 mtspr(SPRN_DVC1, debug->dvc1); 697 mtspr(SPRN_DVC2, debug->dvc2); 698 #endif 699 mtspr(SPRN_DBCR0, debug->dbcr0); 700 mtspr(SPRN_DBCR1, debug->dbcr1); 701 #ifdef CONFIG_BOOKE 702 mtspr(SPRN_DBCR2, debug->dbcr2); 703 #endif 704 } 705 /* 706 * Unless neither the old or new thread are making use of the 707 * debug registers, set the debug registers from the values 708 * stored in the new thread. 709 */ 710 void switch_booke_debug_regs(struct debug_reg *new_debug) 711 { 712 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 713 || (new_debug->dbcr0 & DBCR0_IDM)) 714 prime_debug_regs(new_debug); 715 } 716 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 717 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 718 #ifndef CONFIG_HAVE_HW_BREAKPOINT 719 static void set_debug_reg_defaults(struct thread_struct *thread) 720 { 721 thread->hw_brk.address = 0; 722 thread->hw_brk.type = 0; 723 if (ppc_breakpoint_available()) 724 set_breakpoint(&thread->hw_brk); 725 } 726 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 727 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 728 729 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 730 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 731 { 732 mtspr(SPRN_DAC1, dabr); 733 #ifdef CONFIG_PPC_47x 734 isync(); 735 #endif 736 return 0; 737 } 738 #elif defined(CONFIG_PPC_BOOK3S) 739 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 740 { 741 mtspr(SPRN_DABR, dabr); 742 if (cpu_has_feature(CPU_FTR_DABRX)) 743 mtspr(SPRN_DABRX, dabrx); 744 return 0; 745 } 746 #elif defined(CONFIG_PPC_8xx) 747 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 748 { 749 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR; 750 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */ 751 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */ 752 753 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 754 lctrl1 |= 0xa0000; 755 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 756 lctrl1 |= 0xf0000; 757 else if ((dabr & HW_BRK_TYPE_RDWR) == 0) 758 lctrl2 = 0; 759 760 mtspr(SPRN_LCTRL2, 0); 761 mtspr(SPRN_CMPE, addr); 762 mtspr(SPRN_CMPF, addr + 4); 763 mtspr(SPRN_LCTRL1, lctrl1); 764 mtspr(SPRN_LCTRL2, lctrl2); 765 766 return 0; 767 } 768 #else 769 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 770 { 771 return -EINVAL; 772 } 773 #endif 774 775 static inline int set_dabr(struct arch_hw_breakpoint *brk) 776 { 777 unsigned long dabr, dabrx; 778 779 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 780 dabrx = ((brk->type >> 3) & 0x7); 781 782 if (ppc_md.set_dabr) 783 return ppc_md.set_dabr(dabr, dabrx); 784 785 return __set_dabr(dabr, dabrx); 786 } 787 788 static inline int set_dawr(struct arch_hw_breakpoint *brk) 789 { 790 unsigned long dawr, dawrx, mrd; 791 792 dawr = brk->address; 793 794 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 795 << (63 - 58); //* read/write bits */ 796 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 797 << (63 - 59); //* translate */ 798 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 799 >> 3; //* PRIM bits */ 800 /* dawr length is stored in field MDR bits 48:53. Matches range in 801 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 802 0b111111=64DW. 803 brk->len is in bytes. 804 This aligns up to double word size, shifts and does the bias. 805 */ 806 mrd = ((brk->len + 7) >> 3) - 1; 807 dawrx |= (mrd & 0x3f) << (63 - 53); 808 809 if (ppc_md.set_dawr) 810 return ppc_md.set_dawr(dawr, dawrx); 811 mtspr(SPRN_DAWR, dawr); 812 mtspr(SPRN_DAWRX, dawrx); 813 return 0; 814 } 815 816 void __set_breakpoint(struct arch_hw_breakpoint *brk) 817 { 818 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); 819 820 if (cpu_has_feature(CPU_FTR_DAWR)) 821 // Power8 or later 822 set_dawr(brk); 823 else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) 824 // Power7 or earlier 825 set_dabr(brk); 826 else 827 // Shouldn't happen due to higher level checks 828 WARN_ON_ONCE(1); 829 } 830 831 void set_breakpoint(struct arch_hw_breakpoint *brk) 832 { 833 preempt_disable(); 834 __set_breakpoint(brk); 835 preempt_enable(); 836 } 837 838 /* Check if we have DAWR or DABR hardware */ 839 bool ppc_breakpoint_available(void) 840 { 841 if (cpu_has_feature(CPU_FTR_DAWR)) 842 return true; /* POWER8 DAWR */ 843 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 844 return false; /* POWER9 with DAWR disabled */ 845 /* DABR: Everything but POWER8 and POWER9 */ 846 return true; 847 } 848 EXPORT_SYMBOL_GPL(ppc_breakpoint_available); 849 850 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 851 struct arch_hw_breakpoint *b) 852 { 853 if (a->address != b->address) 854 return false; 855 if (a->type != b->type) 856 return false; 857 if (a->len != b->len) 858 return false; 859 return true; 860 } 861 862 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 863 864 static inline bool tm_enabled(struct task_struct *tsk) 865 { 866 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 867 } 868 869 static void tm_reclaim_thread(struct thread_struct *thr, 870 struct thread_info *ti, uint8_t cause) 871 { 872 /* 873 * Use the current MSR TM suspended bit to track if we have 874 * checkpointed state outstanding. 875 * On signal delivery, we'd normally reclaim the checkpointed 876 * state to obtain stack pointer (see:get_tm_stackpointer()). 877 * This will then directly return to userspace without going 878 * through __switch_to(). However, if the stack frame is bad, 879 * we need to exit this thread which calls __switch_to() which 880 * will again attempt to reclaim the already saved tm state. 881 * Hence we need to check that we've not already reclaimed 882 * this state. 883 * We do this using the current MSR, rather tracking it in 884 * some specific thread_struct bit, as it has the additional 885 * benefit of checking for a potential TM bad thing exception. 886 */ 887 if (!MSR_TM_SUSPENDED(mfmsr())) 888 return; 889 890 giveup_all(container_of(thr, struct task_struct, thread)); 891 892 tm_reclaim(thr, cause); 893 894 /* 895 * If we are in a transaction and FP is off then we can't have 896 * used FP inside that transaction. Hence the checkpointed 897 * state is the same as the live state. We need to copy the 898 * live state to the checkpointed state so that when the 899 * transaction is restored, the checkpointed state is correct 900 * and the aborted transaction sees the correct state. We use 901 * ckpt_regs.msr here as that's what tm_reclaim will use to 902 * determine if it's going to write the checkpointed state or 903 * not. So either this will write the checkpointed registers, 904 * or reclaim will. Similarly for VMX. 905 */ 906 if ((thr->ckpt_regs.msr & MSR_FP) == 0) 907 memcpy(&thr->ckfp_state, &thr->fp_state, 908 sizeof(struct thread_fp_state)); 909 if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 910 memcpy(&thr->ckvr_state, &thr->vr_state, 911 sizeof(struct thread_vr_state)); 912 } 913 914 void tm_reclaim_current(uint8_t cause) 915 { 916 tm_enable(); 917 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 918 } 919 920 static inline void tm_reclaim_task(struct task_struct *tsk) 921 { 922 /* We have to work out if we're switching from/to a task that's in the 923 * middle of a transaction. 924 * 925 * In switching we need to maintain a 2nd register state as 926 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 927 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 928 * ckvr_state 929 * 930 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 931 */ 932 struct thread_struct *thr = &tsk->thread; 933 934 if (!thr->regs) 935 return; 936 937 if (!MSR_TM_ACTIVE(thr->regs->msr)) 938 goto out_and_saveregs; 939 940 WARN_ON(tm_suspend_disabled); 941 942 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 943 "ccr=%lx, msr=%lx, trap=%lx)\n", 944 tsk->pid, thr->regs->nip, 945 thr->regs->ccr, thr->regs->msr, 946 thr->regs->trap); 947 948 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 949 950 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 951 tsk->pid); 952 953 out_and_saveregs: 954 /* Always save the regs here, even if a transaction's not active. 955 * This context-switches a thread's TM info SPRs. We do it here to 956 * be consistent with the restore path (in recheckpoint) which 957 * cannot happen later in _switch(). 958 */ 959 tm_save_sprs(thr); 960 } 961 962 extern void __tm_recheckpoint(struct thread_struct *thread); 963 964 void tm_recheckpoint(struct thread_struct *thread) 965 { 966 unsigned long flags; 967 968 if (!(thread->regs->msr & MSR_TM)) 969 return; 970 971 /* We really can't be interrupted here as the TEXASR registers can't 972 * change and later in the trecheckpoint code, we have a userspace R1. 973 * So let's hard disable over this region. 974 */ 975 local_irq_save(flags); 976 hard_irq_disable(); 977 978 /* The TM SPRs are restored here, so that TEXASR.FS can be set 979 * before the trecheckpoint and no explosion occurs. 980 */ 981 tm_restore_sprs(thread); 982 983 __tm_recheckpoint(thread); 984 985 local_irq_restore(flags); 986 } 987 988 static inline void tm_recheckpoint_new_task(struct task_struct *new) 989 { 990 if (!cpu_has_feature(CPU_FTR_TM)) 991 return; 992 993 /* Recheckpoint the registers of the thread we're about to switch to. 994 * 995 * If the task was using FP, we non-lazily reload both the original and 996 * the speculative FP register states. This is because the kernel 997 * doesn't see if/when a TM rollback occurs, so if we take an FP 998 * unavailable later, we are unable to determine which set of FP regs 999 * need to be restored. 1000 */ 1001 if (!tm_enabled(new)) 1002 return; 1003 1004 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 1005 tm_restore_sprs(&new->thread); 1006 return; 1007 } 1008 /* Recheckpoint to restore original checkpointed register state. */ 1009 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", 1010 new->pid, new->thread.regs->msr); 1011 1012 tm_recheckpoint(&new->thread); 1013 1014 /* 1015 * The checkpointed state has been restored but the live state has 1016 * not, ensure all the math functionality is turned off to trigger 1017 * restore_math() to reload. 1018 */ 1019 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1020 1021 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1022 "(kernel msr 0x%lx)\n", 1023 new->pid, mfmsr()); 1024 } 1025 1026 static inline void __switch_to_tm(struct task_struct *prev, 1027 struct task_struct *new) 1028 { 1029 if (cpu_has_feature(CPU_FTR_TM)) { 1030 if (tm_enabled(prev) || tm_enabled(new)) 1031 tm_enable(); 1032 1033 if (tm_enabled(prev)) { 1034 prev->thread.load_tm++; 1035 tm_reclaim_task(prev); 1036 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 1037 prev->thread.regs->msr &= ~MSR_TM; 1038 } 1039 1040 tm_recheckpoint_new_task(new); 1041 } 1042 } 1043 1044 /* 1045 * This is called if we are on the way out to userspace and the 1046 * TIF_RESTORE_TM flag is set. It checks if we need to reload 1047 * FP and/or vector state and does so if necessary. 1048 * If userspace is inside a transaction (whether active or 1049 * suspended) and FP/VMX/VSX instructions have ever been enabled 1050 * inside that transaction, then we have to keep them enabled 1051 * and keep the FP/VMX/VSX state loaded while ever the transaction 1052 * continues. The reason is that if we didn't, and subsequently 1053 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1054 * we don't know whether it's the same transaction, and thus we 1055 * don't know which of the checkpointed state and the transactional 1056 * state to use. 1057 */ 1058 void restore_tm_state(struct pt_regs *regs) 1059 { 1060 unsigned long msr_diff; 1061 1062 /* 1063 * This is the only moment we should clear TIF_RESTORE_TM as 1064 * it is here that ckpt_regs.msr and pt_regs.msr become the same 1065 * again, anything else could lead to an incorrect ckpt_msr being 1066 * saved and therefore incorrect signal contexts. 1067 */ 1068 clear_thread_flag(TIF_RESTORE_TM); 1069 if (!MSR_TM_ACTIVE(regs->msr)) 1070 return; 1071 1072 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1073 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 1074 1075 /* Ensure that restore_math() will restore */ 1076 if (msr_diff & MSR_FP) 1077 current->thread.load_fp = 1; 1078 #ifdef CONFIG_ALTIVEC 1079 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1080 current->thread.load_vec = 1; 1081 #endif 1082 restore_math(regs); 1083 1084 regs->msr |= msr_diff; 1085 } 1086 1087 #else 1088 #define tm_recheckpoint_new_task(new) 1089 #define __switch_to_tm(prev, new) 1090 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1091 1092 static inline void save_sprs(struct thread_struct *t) 1093 { 1094 #ifdef CONFIG_ALTIVEC 1095 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1096 t->vrsave = mfspr(SPRN_VRSAVE); 1097 #endif 1098 #ifdef CONFIG_PPC_BOOK3S_64 1099 if (cpu_has_feature(CPU_FTR_DSCR)) 1100 t->dscr = mfspr(SPRN_DSCR); 1101 1102 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1103 t->bescr = mfspr(SPRN_BESCR); 1104 t->ebbhr = mfspr(SPRN_EBBHR); 1105 t->ebbrr = mfspr(SPRN_EBBRR); 1106 1107 t->fscr = mfspr(SPRN_FSCR); 1108 1109 /* 1110 * Note that the TAR is not available for use in the kernel. 1111 * (To provide this, the TAR should be backed up/restored on 1112 * exception entry/exit instead, and be in pt_regs. FIXME, 1113 * this should be in pt_regs anyway (for debug).) 1114 */ 1115 t->tar = mfspr(SPRN_TAR); 1116 } 1117 #endif 1118 1119 thread_pkey_regs_save(t); 1120 } 1121 1122 static inline void restore_sprs(struct thread_struct *old_thread, 1123 struct thread_struct *new_thread) 1124 { 1125 #ifdef CONFIG_ALTIVEC 1126 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1127 old_thread->vrsave != new_thread->vrsave) 1128 mtspr(SPRN_VRSAVE, new_thread->vrsave); 1129 #endif 1130 #ifdef CONFIG_PPC_BOOK3S_64 1131 if (cpu_has_feature(CPU_FTR_DSCR)) { 1132 u64 dscr = get_paca()->dscr_default; 1133 if (new_thread->dscr_inherit) 1134 dscr = new_thread->dscr; 1135 1136 if (old_thread->dscr != dscr) 1137 mtspr(SPRN_DSCR, dscr); 1138 } 1139 1140 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1141 if (old_thread->bescr != new_thread->bescr) 1142 mtspr(SPRN_BESCR, new_thread->bescr); 1143 if (old_thread->ebbhr != new_thread->ebbhr) 1144 mtspr(SPRN_EBBHR, new_thread->ebbhr); 1145 if (old_thread->ebbrr != new_thread->ebbrr) 1146 mtspr(SPRN_EBBRR, new_thread->ebbrr); 1147 1148 if (old_thread->fscr != new_thread->fscr) 1149 mtspr(SPRN_FSCR, new_thread->fscr); 1150 1151 if (old_thread->tar != new_thread->tar) 1152 mtspr(SPRN_TAR, new_thread->tar); 1153 } 1154 1155 if (cpu_has_feature(CPU_FTR_P9_TIDR) && 1156 old_thread->tidr != new_thread->tidr) 1157 mtspr(SPRN_TIDR, new_thread->tidr); 1158 #endif 1159 1160 thread_pkey_regs_restore(new_thread, old_thread); 1161 } 1162 1163 #ifdef CONFIG_PPC_BOOK3S_64 1164 #define CP_SIZE 128 1165 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE))); 1166 #endif 1167 1168 struct task_struct *__switch_to(struct task_struct *prev, 1169 struct task_struct *new) 1170 { 1171 struct thread_struct *new_thread, *old_thread; 1172 struct task_struct *last; 1173 #ifdef CONFIG_PPC_BOOK3S_64 1174 struct ppc64_tlb_batch *batch; 1175 #endif 1176 1177 new_thread = &new->thread; 1178 old_thread = ¤t->thread; 1179 1180 WARN_ON(!irqs_disabled()); 1181 1182 #ifdef CONFIG_PPC_BOOK3S_64 1183 batch = this_cpu_ptr(&ppc64_tlb_batch); 1184 if (batch->active) { 1185 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1186 if (batch->index) 1187 __flush_tlb_pending(batch); 1188 batch->active = 0; 1189 } 1190 #endif /* CONFIG_PPC_BOOK3S_64 */ 1191 1192 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1193 switch_booke_debug_regs(&new->thread.debug); 1194 #else 1195 /* 1196 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1197 * schedule DABR 1198 */ 1199 #ifndef CONFIG_HAVE_HW_BREAKPOINT 1200 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) 1201 __set_breakpoint(&new->thread.hw_brk); 1202 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1203 #endif 1204 1205 /* 1206 * We need to save SPRs before treclaim/trecheckpoint as these will 1207 * change a number of them. 1208 */ 1209 save_sprs(&prev->thread); 1210 1211 /* Save FPU, Altivec, VSX and SPE state */ 1212 giveup_all(prev); 1213 1214 __switch_to_tm(prev, new); 1215 1216 if (!radix_enabled()) { 1217 /* 1218 * We can't take a PMU exception inside _switch() since there 1219 * is a window where the kernel stack SLB and the kernel stack 1220 * are out of sync. Hard disable here. 1221 */ 1222 hard_irq_disable(); 1223 } 1224 1225 /* 1226 * Call restore_sprs() before calling _switch(). If we move it after 1227 * _switch() then we miss out on calling it for new tasks. The reason 1228 * for this is we manually create a stack frame for new tasks that 1229 * directly returns through ret_from_fork() or 1230 * ret_from_kernel_thread(). See copy_thread() for details. 1231 */ 1232 restore_sprs(old_thread, new_thread); 1233 1234 last = _switch(old_thread, new_thread); 1235 1236 #ifdef CONFIG_PPC_BOOK3S_64 1237 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1238 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 1239 batch = this_cpu_ptr(&ppc64_tlb_batch); 1240 batch->active = 1; 1241 } 1242 1243 if (current_thread_info()->task->thread.regs) { 1244 restore_math(current_thread_info()->task->thread.regs); 1245 1246 /* 1247 * The copy-paste buffer can only store into foreign real 1248 * addresses, so unprivileged processes can not see the 1249 * data or use it in any way unless they have foreign real 1250 * mappings. If the new process has the foreign real address 1251 * mappings, we must issue a cp_abort to clear any state and 1252 * prevent snooping, corruption or a covert channel. 1253 * 1254 * DD1 allows paste into normal system memory so we do an 1255 * unpaired copy, rather than cp_abort, to clear the buffer, 1256 * since cp_abort is quite expensive. 1257 */ 1258 if (current_thread_info()->task->thread.used_vas) { 1259 asm volatile(PPC_CP_ABORT); 1260 } else if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 1261 asm volatile(PPC_COPY(%0, %1) 1262 : : "r"(dummy_copy_buffer), "r"(0)); 1263 } 1264 } 1265 #endif /* CONFIG_PPC_BOOK3S_64 */ 1266 1267 return last; 1268 } 1269 1270 static int instructions_to_print = 16; 1271 1272 static void show_instructions(struct pt_regs *regs) 1273 { 1274 int i; 1275 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 1276 sizeof(int)); 1277 1278 printk("Instruction dump:"); 1279 1280 for (i = 0; i < instructions_to_print; i++) { 1281 int instr; 1282 1283 if (!(i % 8)) 1284 pr_cont("\n"); 1285 1286 #if !defined(CONFIG_BOOKE) 1287 /* If executing with the IMMU off, adjust pc rather 1288 * than print XXXXXXXX. 1289 */ 1290 if (!(regs->msr & MSR_IR)) 1291 pc = (unsigned long)phys_to_virt(pc); 1292 #endif 1293 1294 if (!__kernel_text_address(pc) || 1295 probe_kernel_address((unsigned int __user *)pc, instr)) { 1296 pr_cont("XXXXXXXX "); 1297 } else { 1298 if (regs->nip == pc) 1299 pr_cont("<%08x> ", instr); 1300 else 1301 pr_cont("%08x ", instr); 1302 } 1303 1304 pc += sizeof(int); 1305 } 1306 1307 pr_cont("\n"); 1308 } 1309 1310 struct regbit { 1311 unsigned long bit; 1312 const char *name; 1313 }; 1314 1315 static struct regbit msr_bits[] = { 1316 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 1317 {MSR_SF, "SF"}, 1318 {MSR_HV, "HV"}, 1319 #endif 1320 {MSR_VEC, "VEC"}, 1321 {MSR_VSX, "VSX"}, 1322 #ifdef CONFIG_BOOKE 1323 {MSR_CE, "CE"}, 1324 #endif 1325 {MSR_EE, "EE"}, 1326 {MSR_PR, "PR"}, 1327 {MSR_FP, "FP"}, 1328 {MSR_ME, "ME"}, 1329 #ifdef CONFIG_BOOKE 1330 {MSR_DE, "DE"}, 1331 #else 1332 {MSR_SE, "SE"}, 1333 {MSR_BE, "BE"}, 1334 #endif 1335 {MSR_IR, "IR"}, 1336 {MSR_DR, "DR"}, 1337 {MSR_PMM, "PMM"}, 1338 #ifndef CONFIG_BOOKE 1339 {MSR_RI, "RI"}, 1340 {MSR_LE, "LE"}, 1341 #endif 1342 {0, NULL} 1343 }; 1344 1345 static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 1346 { 1347 const char *s = ""; 1348 1349 for (; bits->bit; ++bits) 1350 if (val & bits->bit) { 1351 pr_cont("%s%s", s, bits->name); 1352 s = sep; 1353 } 1354 } 1355 1356 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1357 static struct regbit msr_tm_bits[] = { 1358 {MSR_TS_T, "T"}, 1359 {MSR_TS_S, "S"}, 1360 {MSR_TM, "E"}, 1361 {0, NULL} 1362 }; 1363 1364 static void print_tm_bits(unsigned long val) 1365 { 1366 /* 1367 * This only prints something if at least one of the TM bit is set. 1368 * Inside the TM[], the output means: 1369 * E: Enabled (bit 32) 1370 * S: Suspended (bit 33) 1371 * T: Transactional (bit 34) 1372 */ 1373 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1374 pr_cont(",TM["); 1375 print_bits(val, msr_tm_bits, ""); 1376 pr_cont("]"); 1377 } 1378 } 1379 #else 1380 static void print_tm_bits(unsigned long val) {} 1381 #endif 1382 1383 static void print_msr_bits(unsigned long val) 1384 { 1385 pr_cont("<"); 1386 print_bits(val, msr_bits, ","); 1387 print_tm_bits(val); 1388 pr_cont(">"); 1389 } 1390 1391 #ifdef CONFIG_PPC64 1392 #define REG "%016lx" 1393 #define REGS_PER_LINE 4 1394 #define LAST_VOLATILE 13 1395 #else 1396 #define REG "%08lx" 1397 #define REGS_PER_LINE 8 1398 #define LAST_VOLATILE 12 1399 #endif 1400 1401 void show_regs(struct pt_regs * regs) 1402 { 1403 int i, trap; 1404 1405 show_regs_print_info(KERN_DEFAULT); 1406 1407 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 1408 regs->nip, regs->link, regs->ctr); 1409 printk("REGS: %px TRAP: %04lx %s (%s)\n", 1410 regs, regs->trap, print_tainted(), init_utsname()->release); 1411 printk("MSR: "REG" ", regs->msr); 1412 print_msr_bits(regs->msr); 1413 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1414 trap = TRAP(regs); 1415 if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1416 pr_cont("CFAR: "REG" ", regs->orig_gpr3); 1417 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1418 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1419 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1420 #else 1421 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1422 #endif 1423 #ifdef CONFIG_PPC64 1424 pr_cont("IRQMASK: %lx ", regs->softe); 1425 #endif 1426 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1427 if (MSR_TM_ACTIVE(regs->msr)) 1428 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1429 #endif 1430 1431 for (i = 0; i < 32; i++) { 1432 if ((i % REGS_PER_LINE) == 0) 1433 pr_cont("\nGPR%02d: ", i); 1434 pr_cont(REG " ", regs->gpr[i]); 1435 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1436 break; 1437 } 1438 pr_cont("\n"); 1439 #ifdef CONFIG_KALLSYMS 1440 /* 1441 * Lookup NIP late so we have the best change of getting the 1442 * above info out without failing 1443 */ 1444 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1445 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1446 #endif 1447 show_stack(current, (unsigned long *) regs->gpr[1]); 1448 if (!user_mode(regs)) 1449 show_instructions(regs); 1450 } 1451 1452 void flush_thread(void) 1453 { 1454 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1455 flush_ptrace_hw_breakpoint(current); 1456 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1457 set_debug_reg_defaults(¤t->thread); 1458 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1459 } 1460 1461 int set_thread_uses_vas(void) 1462 { 1463 #ifdef CONFIG_PPC_BOOK3S_64 1464 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1465 return -EINVAL; 1466 1467 current->thread.used_vas = 1; 1468 1469 /* 1470 * Even a process that has no foreign real address mapping can use 1471 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT 1472 * to clear any pending COPY and prevent a covert channel. 1473 * 1474 * __switch_to() will issue CP_ABORT on future context switches. 1475 */ 1476 asm volatile(PPC_CP_ABORT); 1477 1478 #endif /* CONFIG_PPC_BOOK3S_64 */ 1479 return 0; 1480 } 1481 1482 #ifdef CONFIG_PPC64 1483 /** 1484 * Assign a TIDR (thread ID) for task @t and set it in the thread 1485 * structure. For now, we only support setting TIDR for 'current' task. 1486 * 1487 * Since the TID value is a truncated form of it PID, it is possible 1488 * (but unlikely) for 2 threads to have the same TID. In the unlikely event 1489 * that 2 threads share the same TID and are waiting, one of the following 1490 * cases will happen: 1491 * 1492 * 1. The correct thread is running, the wrong thread is not 1493 * In this situation, the correct thread is woken and proceeds to pass it's 1494 * condition check. 1495 * 1496 * 2. Neither threads are running 1497 * In this situation, neither thread will be woken. When scheduled, the waiting 1498 * threads will execute either a wait, which will return immediately, followed 1499 * by a condition check, which will pass for the correct thread and fail 1500 * for the wrong thread, or they will execute the condition check immediately. 1501 * 1502 * 3. The wrong thread is running, the correct thread is not 1503 * The wrong thread will be woken, but will fail it's condition check and 1504 * re-execute wait. The correct thread, when scheduled, will execute either 1505 * it's condition check (which will pass), or wait, which returns immediately 1506 * when called the first time after the thread is scheduled, followed by it's 1507 * condition check (which will pass). 1508 * 1509 * 4. Both threads are running 1510 * Both threads will be woken. The wrong thread will fail it's condition check 1511 * and execute another wait, while the correct thread will pass it's condition 1512 * check. 1513 * 1514 * @t: the task to set the thread ID for 1515 */ 1516 int set_thread_tidr(struct task_struct *t) 1517 { 1518 if (!cpu_has_feature(CPU_FTR_P9_TIDR)) 1519 return -EINVAL; 1520 1521 if (t != current) 1522 return -EINVAL; 1523 1524 if (t->thread.tidr) 1525 return 0; 1526 1527 t->thread.tidr = (u16)task_pid_nr(t); 1528 mtspr(SPRN_TIDR, t->thread.tidr); 1529 1530 return 0; 1531 } 1532 EXPORT_SYMBOL_GPL(set_thread_tidr); 1533 1534 #endif /* CONFIG_PPC64 */ 1535 1536 void 1537 release_thread(struct task_struct *t) 1538 { 1539 } 1540 1541 /* 1542 * this gets called so that we can store coprocessor state into memory and 1543 * copy the current task into the new thread. 1544 */ 1545 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1546 { 1547 flush_all_to_thread(src); 1548 /* 1549 * Flush TM state out so we can copy it. __switch_to_tm() does this 1550 * flush but it removes the checkpointed state from the current CPU and 1551 * transitions the CPU out of TM mode. Hence we need to call 1552 * tm_recheckpoint_new_task() (on the same task) to restore the 1553 * checkpointed state back and the TM mode. 1554 * 1555 * Can't pass dst because it isn't ready. Doesn't matter, passing 1556 * dst is only important for __switch_to() 1557 */ 1558 __switch_to_tm(src, src); 1559 1560 *dst = *src; 1561 1562 clear_task_ebb(dst); 1563 1564 return 0; 1565 } 1566 1567 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1568 { 1569 #ifdef CONFIG_PPC_BOOK3S_64 1570 unsigned long sp_vsid; 1571 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1572 1573 if (radix_enabled()) 1574 return; 1575 1576 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1577 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1578 << SLB_VSID_SHIFT_1T; 1579 else 1580 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1581 << SLB_VSID_SHIFT; 1582 sp_vsid |= SLB_VSID_KERNEL | llp; 1583 p->thread.ksp_vsid = sp_vsid; 1584 #endif 1585 } 1586 1587 /* 1588 * Copy a thread.. 1589 */ 1590 1591 /* 1592 * Copy architecture-specific thread state 1593 */ 1594 int copy_thread(unsigned long clone_flags, unsigned long usp, 1595 unsigned long kthread_arg, struct task_struct *p) 1596 { 1597 struct pt_regs *childregs, *kregs; 1598 extern void ret_from_fork(void); 1599 extern void ret_from_kernel_thread(void); 1600 void (*f)(void); 1601 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1602 struct thread_info *ti = task_thread_info(p); 1603 1604 klp_init_thread_info(ti); 1605 1606 /* Copy registers */ 1607 sp -= sizeof(struct pt_regs); 1608 childregs = (struct pt_regs *) sp; 1609 if (unlikely(p->flags & PF_KTHREAD)) { 1610 /* kernel thread */ 1611 memset(childregs, 0, sizeof(struct pt_regs)); 1612 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1613 /* function */ 1614 if (usp) 1615 childregs->gpr[14] = ppc_function_entry((void *)usp); 1616 #ifdef CONFIG_PPC64 1617 clear_tsk_thread_flag(p, TIF_32BIT); 1618 childregs->softe = IRQS_ENABLED; 1619 #endif 1620 childregs->gpr[15] = kthread_arg; 1621 p->thread.regs = NULL; /* no user register state */ 1622 ti->flags |= _TIF_RESTOREALL; 1623 f = ret_from_kernel_thread; 1624 } else { 1625 /* user thread */ 1626 struct pt_regs *regs = current_pt_regs(); 1627 CHECK_FULL_REGS(regs); 1628 *childregs = *regs; 1629 if (usp) 1630 childregs->gpr[1] = usp; 1631 p->thread.regs = childregs; 1632 childregs->gpr[3] = 0; /* Result from fork() */ 1633 if (clone_flags & CLONE_SETTLS) { 1634 #ifdef CONFIG_PPC64 1635 if (!is_32bit_task()) 1636 childregs->gpr[13] = childregs->gpr[6]; 1637 else 1638 #endif 1639 childregs->gpr[2] = childregs->gpr[6]; 1640 } 1641 1642 f = ret_from_fork; 1643 } 1644 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 1645 sp -= STACK_FRAME_OVERHEAD; 1646 1647 /* 1648 * The way this works is that at some point in the future 1649 * some task will call _switch to switch to the new task. 1650 * That will pop off the stack frame created below and start 1651 * the new task running at ret_from_fork. The new task will 1652 * do some house keeping and then return from the fork or clone 1653 * system call, using the stack frame created above. 1654 */ 1655 ((unsigned long *)sp)[0] = 0; 1656 sp -= sizeof(struct pt_regs); 1657 kregs = (struct pt_regs *) sp; 1658 sp -= STACK_FRAME_OVERHEAD; 1659 p->thread.ksp = sp; 1660 #ifdef CONFIG_PPC32 1661 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1662 _ALIGN_UP(sizeof(struct thread_info), 16); 1663 #endif 1664 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1665 p->thread.ptrace_bps[0] = NULL; 1666 #endif 1667 1668 p->thread.fp_save_area = NULL; 1669 #ifdef CONFIG_ALTIVEC 1670 p->thread.vr_save_area = NULL; 1671 #endif 1672 1673 setup_ksp_vsid(p, sp); 1674 1675 #ifdef CONFIG_PPC64 1676 if (cpu_has_feature(CPU_FTR_DSCR)) { 1677 p->thread.dscr_inherit = current->thread.dscr_inherit; 1678 p->thread.dscr = mfspr(SPRN_DSCR); 1679 } 1680 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1681 p->thread.ppr = INIT_PPR; 1682 1683 p->thread.tidr = 0; 1684 #endif 1685 kregs->nip = ppc_function_entry(f); 1686 return 0; 1687 } 1688 1689 /* 1690 * Set up a thread for executing a new program 1691 */ 1692 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1693 { 1694 #ifdef CONFIG_PPC64 1695 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1696 #endif 1697 1698 /* 1699 * If we exec out of a kernel thread then thread.regs will not be 1700 * set. Do it now. 1701 */ 1702 if (!current->thread.regs) { 1703 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1704 current->thread.regs = regs - 1; 1705 } 1706 1707 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1708 /* 1709 * Clear any transactional state, we're exec()ing. The cause is 1710 * not important as there will never be a recheckpoint so it's not 1711 * user visible. 1712 */ 1713 if (MSR_TM_SUSPENDED(mfmsr())) 1714 tm_reclaim_current(0); 1715 #endif 1716 1717 memset(regs->gpr, 0, sizeof(regs->gpr)); 1718 regs->ctr = 0; 1719 regs->link = 0; 1720 regs->xer = 0; 1721 regs->ccr = 0; 1722 regs->gpr[1] = sp; 1723 1724 /* 1725 * We have just cleared all the nonvolatile GPRs, so make 1726 * FULL_REGS(regs) return true. This is necessary to allow 1727 * ptrace to examine the thread immediately after exec. 1728 */ 1729 regs->trap &= ~1UL; 1730 1731 #ifdef CONFIG_PPC32 1732 regs->mq = 0; 1733 regs->nip = start; 1734 regs->msr = MSR_USER; 1735 #else 1736 if (!is_32bit_task()) { 1737 unsigned long entry; 1738 1739 if (is_elf2_task()) { 1740 /* Look ma, no function descriptors! */ 1741 entry = start; 1742 1743 /* 1744 * Ulrich says: 1745 * The latest iteration of the ABI requires that when 1746 * calling a function (at its global entry point), 1747 * the caller must ensure r12 holds the entry point 1748 * address (so that the function can quickly 1749 * establish addressability). 1750 */ 1751 regs->gpr[12] = start; 1752 /* Make sure that's restored on entry to userspace. */ 1753 set_thread_flag(TIF_RESTOREALL); 1754 } else { 1755 unsigned long toc; 1756 1757 /* start is a relocated pointer to the function 1758 * descriptor for the elf _start routine. The first 1759 * entry in the function descriptor is the entry 1760 * address of _start and the second entry is the TOC 1761 * value we need to use. 1762 */ 1763 __get_user(entry, (unsigned long __user *)start); 1764 __get_user(toc, (unsigned long __user *)start+1); 1765 1766 /* Check whether the e_entry function descriptor entries 1767 * need to be relocated before we can use them. 1768 */ 1769 if (load_addr != 0) { 1770 entry += load_addr; 1771 toc += load_addr; 1772 } 1773 regs->gpr[2] = toc; 1774 } 1775 regs->nip = entry; 1776 regs->msr = MSR_USER64; 1777 } else { 1778 regs->nip = start; 1779 regs->gpr[2] = 0; 1780 regs->msr = MSR_USER32; 1781 } 1782 #endif 1783 #ifdef CONFIG_VSX 1784 current->thread.used_vsr = 0; 1785 #endif 1786 current->thread.load_fp = 0; 1787 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1788 current->thread.fp_save_area = NULL; 1789 #ifdef CONFIG_ALTIVEC 1790 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1791 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1792 current->thread.vr_save_area = NULL; 1793 current->thread.vrsave = 0; 1794 current->thread.used_vr = 0; 1795 current->thread.load_vec = 0; 1796 #endif /* CONFIG_ALTIVEC */ 1797 #ifdef CONFIG_SPE 1798 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1799 current->thread.acc = 0; 1800 current->thread.spefscr = 0; 1801 current->thread.used_spe = 0; 1802 #endif /* CONFIG_SPE */ 1803 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1804 current->thread.tm_tfhar = 0; 1805 current->thread.tm_texasr = 0; 1806 current->thread.tm_tfiar = 0; 1807 current->thread.load_tm = 0; 1808 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1809 1810 thread_pkey_regs_init(¤t->thread); 1811 } 1812 EXPORT_SYMBOL(start_thread); 1813 1814 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1815 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1816 1817 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1818 { 1819 struct pt_regs *regs = tsk->thread.regs; 1820 1821 /* This is a bit hairy. If we are an SPE enabled processor 1822 * (have embedded fp) we store the IEEE exception enable flags in 1823 * fpexc_mode. fpexc_mode is also used for setting FP exception 1824 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1825 if (val & PR_FP_EXC_SW_ENABLE) { 1826 #ifdef CONFIG_SPE 1827 if (cpu_has_feature(CPU_FTR_SPE)) { 1828 /* 1829 * When the sticky exception bits are set 1830 * directly by userspace, it must call prctl 1831 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1832 * in the existing prctl settings) or 1833 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1834 * the bits being set). <fenv.h> functions 1835 * saving and restoring the whole 1836 * floating-point environment need to do so 1837 * anyway to restore the prctl settings from 1838 * the saved environment. 1839 */ 1840 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1841 tsk->thread.fpexc_mode = val & 1842 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1843 return 0; 1844 } else { 1845 return -EINVAL; 1846 } 1847 #else 1848 return -EINVAL; 1849 #endif 1850 } 1851 1852 /* on a CONFIG_SPE this does not hurt us. The bits that 1853 * __pack_fe01 use do not overlap with bits used for 1854 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1855 * on CONFIG_SPE implementations are reserved so writing to 1856 * them does not change anything */ 1857 if (val > PR_FP_EXC_PRECISE) 1858 return -EINVAL; 1859 tsk->thread.fpexc_mode = __pack_fe01(val); 1860 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1861 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1862 | tsk->thread.fpexc_mode; 1863 return 0; 1864 } 1865 1866 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1867 { 1868 unsigned int val; 1869 1870 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1871 #ifdef CONFIG_SPE 1872 if (cpu_has_feature(CPU_FTR_SPE)) { 1873 /* 1874 * When the sticky exception bits are set 1875 * directly by userspace, it must call prctl 1876 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1877 * in the existing prctl settings) or 1878 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1879 * the bits being set). <fenv.h> functions 1880 * saving and restoring the whole 1881 * floating-point environment need to do so 1882 * anyway to restore the prctl settings from 1883 * the saved environment. 1884 */ 1885 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1886 val = tsk->thread.fpexc_mode; 1887 } else 1888 return -EINVAL; 1889 #else 1890 return -EINVAL; 1891 #endif 1892 else 1893 val = __unpack_fe01(tsk->thread.fpexc_mode); 1894 return put_user(val, (unsigned int __user *) adr); 1895 } 1896 1897 int set_endian(struct task_struct *tsk, unsigned int val) 1898 { 1899 struct pt_regs *regs = tsk->thread.regs; 1900 1901 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1902 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1903 return -EINVAL; 1904 1905 if (regs == NULL) 1906 return -EINVAL; 1907 1908 if (val == PR_ENDIAN_BIG) 1909 regs->msr &= ~MSR_LE; 1910 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1911 regs->msr |= MSR_LE; 1912 else 1913 return -EINVAL; 1914 1915 return 0; 1916 } 1917 1918 int get_endian(struct task_struct *tsk, unsigned long adr) 1919 { 1920 struct pt_regs *regs = tsk->thread.regs; 1921 unsigned int val; 1922 1923 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1924 !cpu_has_feature(CPU_FTR_REAL_LE)) 1925 return -EINVAL; 1926 1927 if (regs == NULL) 1928 return -EINVAL; 1929 1930 if (regs->msr & MSR_LE) { 1931 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1932 val = PR_ENDIAN_LITTLE; 1933 else 1934 val = PR_ENDIAN_PPC_LITTLE; 1935 } else 1936 val = PR_ENDIAN_BIG; 1937 1938 return put_user(val, (unsigned int __user *)adr); 1939 } 1940 1941 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1942 { 1943 tsk->thread.align_ctl = val; 1944 return 0; 1945 } 1946 1947 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1948 { 1949 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1950 } 1951 1952 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1953 unsigned long nbytes) 1954 { 1955 unsigned long stack_page; 1956 unsigned long cpu = task_cpu(p); 1957 1958 /* 1959 * Avoid crashing if the stack has overflowed and corrupted 1960 * task_cpu(p), which is in the thread_info struct. 1961 */ 1962 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1963 stack_page = (unsigned long) hardirq_ctx[cpu]; 1964 if (sp >= stack_page + sizeof(struct thread_struct) 1965 && sp <= stack_page + THREAD_SIZE - nbytes) 1966 return 1; 1967 1968 stack_page = (unsigned long) softirq_ctx[cpu]; 1969 if (sp >= stack_page + sizeof(struct thread_struct) 1970 && sp <= stack_page + THREAD_SIZE - nbytes) 1971 return 1; 1972 } 1973 return 0; 1974 } 1975 1976 int validate_sp(unsigned long sp, struct task_struct *p, 1977 unsigned long nbytes) 1978 { 1979 unsigned long stack_page = (unsigned long)task_stack_page(p); 1980 1981 if (sp >= stack_page + sizeof(struct thread_struct) 1982 && sp <= stack_page + THREAD_SIZE - nbytes) 1983 return 1; 1984 1985 return valid_irq_stack(sp, p, nbytes); 1986 } 1987 1988 EXPORT_SYMBOL(validate_sp); 1989 1990 unsigned long get_wchan(struct task_struct *p) 1991 { 1992 unsigned long ip, sp; 1993 int count = 0; 1994 1995 if (!p || p == current || p->state == TASK_RUNNING) 1996 return 0; 1997 1998 sp = p->thread.ksp; 1999 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 2000 return 0; 2001 2002 do { 2003 sp = *(unsigned long *)sp; 2004 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || 2005 p->state == TASK_RUNNING) 2006 return 0; 2007 if (count > 0) { 2008 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 2009 if (!in_sched_functions(ip)) 2010 return ip; 2011 } 2012 } while (count++ < 16); 2013 return 0; 2014 } 2015 2016 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 2017 2018 void show_stack(struct task_struct *tsk, unsigned long *stack) 2019 { 2020 unsigned long sp, ip, lr, newsp; 2021 int count = 0; 2022 int firstframe = 1; 2023 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 2024 int curr_frame = current->curr_ret_stack; 2025 extern void return_to_handler(void); 2026 unsigned long rth = (unsigned long)return_to_handler; 2027 #endif 2028 2029 sp = (unsigned long) stack; 2030 if (tsk == NULL) 2031 tsk = current; 2032 if (sp == 0) { 2033 if (tsk == current) 2034 sp = current_stack_pointer(); 2035 else 2036 sp = tsk->thread.ksp; 2037 } 2038 2039 lr = 0; 2040 printk("Call Trace:\n"); 2041 do { 2042 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 2043 return; 2044 2045 stack = (unsigned long *) sp; 2046 newsp = stack[0]; 2047 ip = stack[STACK_FRAME_LR_SAVE]; 2048 if (!firstframe || ip != lr) { 2049 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 2050 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 2051 if ((ip == rth) && curr_frame >= 0) { 2052 pr_cont(" (%pS)", 2053 (void *)current->ret_stack[curr_frame].ret); 2054 curr_frame--; 2055 } 2056 #endif 2057 if (firstframe) 2058 pr_cont(" (unreliable)"); 2059 pr_cont("\n"); 2060 } 2061 firstframe = 0; 2062 2063 /* 2064 * See if this is an exception frame. 2065 * We look for the "regshere" marker in the current frame. 2066 */ 2067 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 2068 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 2069 struct pt_regs *regs = (struct pt_regs *) 2070 (sp + STACK_FRAME_OVERHEAD); 2071 lr = regs->link; 2072 printk("--- interrupt: %lx at %pS\n LR = %pS\n", 2073 regs->trap, (void *)regs->nip, (void *)lr); 2074 firstframe = 1; 2075 } 2076 2077 sp = newsp; 2078 } while (count++ < kstack_depth_to_print); 2079 } 2080 2081 #ifdef CONFIG_PPC64 2082 /* Called with hard IRQs off */ 2083 void notrace __ppc64_runlatch_on(void) 2084 { 2085 struct thread_info *ti = current_thread_info(); 2086 2087 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2088 /* 2089 * Least significant bit (RUN) is the only writable bit of 2090 * the CTRL register, so we can avoid mfspr. 2.06 is not the 2091 * earliest ISA where this is the case, but it's convenient. 2092 */ 2093 mtspr(SPRN_CTRLT, CTRL_RUNLATCH); 2094 } else { 2095 unsigned long ctrl; 2096 2097 /* 2098 * Some architectures (e.g., Cell) have writable fields other 2099 * than RUN, so do the read-modify-write. 2100 */ 2101 ctrl = mfspr(SPRN_CTRLF); 2102 ctrl |= CTRL_RUNLATCH; 2103 mtspr(SPRN_CTRLT, ctrl); 2104 } 2105 2106 ti->local_flags |= _TLF_RUNLATCH; 2107 } 2108 2109 /* Called with hard IRQs off */ 2110 void notrace __ppc64_runlatch_off(void) 2111 { 2112 struct thread_info *ti = current_thread_info(); 2113 2114 ti->local_flags &= ~_TLF_RUNLATCH; 2115 2116 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2117 mtspr(SPRN_CTRLT, 0); 2118 } else { 2119 unsigned long ctrl; 2120 2121 ctrl = mfspr(SPRN_CTRLF); 2122 ctrl &= ~CTRL_RUNLATCH; 2123 mtspr(SPRN_CTRLT, ctrl); 2124 } 2125 } 2126 #endif /* CONFIG_PPC64 */ 2127 2128 unsigned long arch_align_stack(unsigned long sp) 2129 { 2130 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2131 sp -= get_random_int() & ~PAGE_MASK; 2132 return sp & ~0xf; 2133 } 2134 2135 static inline unsigned long brk_rnd(void) 2136 { 2137 unsigned long rnd = 0; 2138 2139 /* 8MB for 32bit, 1GB for 64bit */ 2140 if (is_32bit_task()) 2141 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2142 else 2143 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2144 2145 return rnd << PAGE_SHIFT; 2146 } 2147 2148 unsigned long arch_randomize_brk(struct mm_struct *mm) 2149 { 2150 unsigned long base = mm->brk; 2151 unsigned long ret; 2152 2153 #ifdef CONFIG_PPC_BOOK3S_64 2154 /* 2155 * If we are using 1TB segments and we are allowed to randomise 2156 * the heap, we can put it above 1TB so it is backed by a 1TB 2157 * segment. Otherwise the heap will be in the bottom 1TB 2158 * which always uses 256MB segments and this may result in a 2159 * performance penalty. We don't need to worry about radix. For 2160 * radix, mmu_highuser_ssize remains unchanged from 256MB. 2161 */ 2162 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 2163 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 2164 #endif 2165 2166 ret = PAGE_ALIGN(base + brk_rnd()); 2167 2168 if (ret < mm->brk) 2169 return mm->brk; 2170 2171 return ret; 2172 } 2173 2174