1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/init.h> 29 #include <linux/prctl.h> 30 #include <linux/init_task.h> 31 #include <linux/export.h> 32 #include <linux/kallsyms.h> 33 #include <linux/mqueue.h> 34 #include <linux/hardirq.h> 35 #include <linux/utsname.h> 36 #include <linux/ftrace.h> 37 #include <linux/kernel_stat.h> 38 #include <linux/personality.h> 39 #include <linux/random.h> 40 #include <linux/hw_breakpoint.h> 41 42 #include <asm/pgtable.h> 43 #include <asm/uaccess.h> 44 #include <asm/io.h> 45 #include <asm/processor.h> 46 #include <asm/mmu.h> 47 #include <asm/prom.h> 48 #include <asm/machdep.h> 49 #include <asm/time.h> 50 #include <asm/runlatch.h> 51 #include <asm/syscalls.h> 52 #include <asm/switch_to.h> 53 #include <asm/tm.h> 54 #include <asm/debug.h> 55 #ifdef CONFIG_PPC64 56 #include <asm/firmware.h> 57 #endif 58 #include <linux/kprobes.h> 59 #include <linux/kdebug.h> 60 61 /* Transactional Memory debug */ 62 #ifdef TM_DEBUG_SW 63 #define TM_DEBUG(x...) printk(KERN_INFO x) 64 #else 65 #define TM_DEBUG(x...) do { } while(0) 66 #endif 67 68 extern unsigned long _get_SP(void); 69 70 #ifndef CONFIG_SMP 71 struct task_struct *last_task_used_math = NULL; 72 struct task_struct *last_task_used_altivec = NULL; 73 struct task_struct *last_task_used_vsx = NULL; 74 struct task_struct *last_task_used_spe = NULL; 75 #endif 76 77 /* 78 * Make sure the floating-point register state in the 79 * the thread_struct is up to date for task tsk. 80 */ 81 void flush_fp_to_thread(struct task_struct *tsk) 82 { 83 if (tsk->thread.regs) { 84 /* 85 * We need to disable preemption here because if we didn't, 86 * another process could get scheduled after the regs->msr 87 * test but before we have finished saving the FP registers 88 * to the thread_struct. That process could take over the 89 * FPU, and then when we get scheduled again we would store 90 * bogus values for the remaining FP registers. 91 */ 92 preempt_disable(); 93 if (tsk->thread.regs->msr & MSR_FP) { 94 #ifdef CONFIG_SMP 95 /* 96 * This should only ever be called for current or 97 * for a stopped child process. Since we save away 98 * the FP register state on context switch on SMP, 99 * there is something wrong if a stopped child appears 100 * to still have its FP state in the CPU registers. 101 */ 102 BUG_ON(tsk != current); 103 #endif 104 giveup_fpu(tsk); 105 } 106 preempt_enable(); 107 } 108 } 109 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 110 111 void enable_kernel_fp(void) 112 { 113 WARN_ON(preemptible()); 114 115 #ifdef CONFIG_SMP 116 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) 117 giveup_fpu(current); 118 else 119 giveup_fpu(NULL); /* just enables FP for kernel */ 120 #else 121 giveup_fpu(last_task_used_math); 122 #endif /* CONFIG_SMP */ 123 } 124 EXPORT_SYMBOL(enable_kernel_fp); 125 126 #ifdef CONFIG_ALTIVEC 127 void enable_kernel_altivec(void) 128 { 129 WARN_ON(preemptible()); 130 131 #ifdef CONFIG_SMP 132 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) 133 giveup_altivec(current); 134 else 135 giveup_altivec_notask(); 136 #else 137 giveup_altivec(last_task_used_altivec); 138 #endif /* CONFIG_SMP */ 139 } 140 EXPORT_SYMBOL(enable_kernel_altivec); 141 142 /* 143 * Make sure the VMX/Altivec register state in the 144 * the thread_struct is up to date for task tsk. 145 */ 146 void flush_altivec_to_thread(struct task_struct *tsk) 147 { 148 if (tsk->thread.regs) { 149 preempt_disable(); 150 if (tsk->thread.regs->msr & MSR_VEC) { 151 #ifdef CONFIG_SMP 152 BUG_ON(tsk != current); 153 #endif 154 giveup_altivec(tsk); 155 } 156 preempt_enable(); 157 } 158 } 159 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 160 #endif /* CONFIG_ALTIVEC */ 161 162 #ifdef CONFIG_VSX 163 #if 0 164 /* not currently used, but some crazy RAID module might want to later */ 165 void enable_kernel_vsx(void) 166 { 167 WARN_ON(preemptible()); 168 169 #ifdef CONFIG_SMP 170 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) 171 giveup_vsx(current); 172 else 173 giveup_vsx(NULL); /* just enable vsx for kernel - force */ 174 #else 175 giveup_vsx(last_task_used_vsx); 176 #endif /* CONFIG_SMP */ 177 } 178 EXPORT_SYMBOL(enable_kernel_vsx); 179 #endif 180 181 void giveup_vsx(struct task_struct *tsk) 182 { 183 giveup_fpu(tsk); 184 giveup_altivec(tsk); 185 __giveup_vsx(tsk); 186 } 187 188 void flush_vsx_to_thread(struct task_struct *tsk) 189 { 190 if (tsk->thread.regs) { 191 preempt_disable(); 192 if (tsk->thread.regs->msr & MSR_VSX) { 193 #ifdef CONFIG_SMP 194 BUG_ON(tsk != current); 195 #endif 196 giveup_vsx(tsk); 197 } 198 preempt_enable(); 199 } 200 } 201 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 202 #endif /* CONFIG_VSX */ 203 204 #ifdef CONFIG_SPE 205 206 void enable_kernel_spe(void) 207 { 208 WARN_ON(preemptible()); 209 210 #ifdef CONFIG_SMP 211 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) 212 giveup_spe(current); 213 else 214 giveup_spe(NULL); /* just enable SPE for kernel - force */ 215 #else 216 giveup_spe(last_task_used_spe); 217 #endif /* __SMP __ */ 218 } 219 EXPORT_SYMBOL(enable_kernel_spe); 220 221 void flush_spe_to_thread(struct task_struct *tsk) 222 { 223 if (tsk->thread.regs) { 224 preempt_disable(); 225 if (tsk->thread.regs->msr & MSR_SPE) { 226 #ifdef CONFIG_SMP 227 BUG_ON(tsk != current); 228 #endif 229 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 230 giveup_spe(tsk); 231 } 232 preempt_enable(); 233 } 234 } 235 #endif /* CONFIG_SPE */ 236 237 #ifndef CONFIG_SMP 238 /* 239 * If we are doing lazy switching of CPU state (FP, altivec or SPE), 240 * and the current task has some state, discard it. 241 */ 242 void discard_lazy_cpu_state(void) 243 { 244 preempt_disable(); 245 if (last_task_used_math == current) 246 last_task_used_math = NULL; 247 #ifdef CONFIG_ALTIVEC 248 if (last_task_used_altivec == current) 249 last_task_used_altivec = NULL; 250 #endif /* CONFIG_ALTIVEC */ 251 #ifdef CONFIG_VSX 252 if (last_task_used_vsx == current) 253 last_task_used_vsx = NULL; 254 #endif /* CONFIG_VSX */ 255 #ifdef CONFIG_SPE 256 if (last_task_used_spe == current) 257 last_task_used_spe = NULL; 258 #endif 259 preempt_enable(); 260 } 261 #endif /* CONFIG_SMP */ 262 263 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 264 void do_send_trap(struct pt_regs *regs, unsigned long address, 265 unsigned long error_code, int signal_code, int breakpt) 266 { 267 siginfo_t info; 268 269 current->thread.trap_nr = signal_code; 270 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 271 11, SIGSEGV) == NOTIFY_STOP) 272 return; 273 274 /* Deliver the signal to userspace */ 275 info.si_signo = SIGTRAP; 276 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 277 info.si_code = signal_code; 278 info.si_addr = (void __user *)address; 279 force_sig_info(SIGTRAP, &info, current); 280 } 281 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 282 void do_break (struct pt_regs *regs, unsigned long address, 283 unsigned long error_code) 284 { 285 siginfo_t info; 286 287 current->thread.trap_nr = TRAP_HWBKPT; 288 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 289 11, SIGSEGV) == NOTIFY_STOP) 290 return; 291 292 if (debugger_break_match(regs)) 293 return; 294 295 /* Clear the breakpoint */ 296 hw_breakpoint_disable(); 297 298 /* Deliver the signal to userspace */ 299 info.si_signo = SIGTRAP; 300 info.si_errno = 0; 301 info.si_code = TRAP_HWBKPT; 302 info.si_addr = (void __user *)address; 303 force_sig_info(SIGTRAP, &info, current); 304 } 305 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 306 307 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 308 309 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 310 /* 311 * Set the debug registers back to their default "safe" values. 312 */ 313 static void set_debug_reg_defaults(struct thread_struct *thread) 314 { 315 thread->iac1 = thread->iac2 = 0; 316 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 317 thread->iac3 = thread->iac4 = 0; 318 #endif 319 thread->dac1 = thread->dac2 = 0; 320 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 321 thread->dvc1 = thread->dvc2 = 0; 322 #endif 323 thread->dbcr0 = 0; 324 #ifdef CONFIG_BOOKE 325 /* 326 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 327 */ 328 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \ 329 DBCR1_IAC3US | DBCR1_IAC4US; 330 /* 331 * Force Data Address Compare User/Supervisor bits to be User-only 332 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 333 */ 334 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 335 #else 336 thread->dbcr1 = 0; 337 #endif 338 } 339 340 static void prime_debug_regs(struct thread_struct *thread) 341 { 342 /* 343 * We could have inherited MSR_DE from userspace, since 344 * it doesn't get cleared on exception entry. Make sure 345 * MSR_DE is clear before we enable any debug events. 346 */ 347 mtmsr(mfmsr() & ~MSR_DE); 348 349 mtspr(SPRN_IAC1, thread->iac1); 350 mtspr(SPRN_IAC2, thread->iac2); 351 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 352 mtspr(SPRN_IAC3, thread->iac3); 353 mtspr(SPRN_IAC4, thread->iac4); 354 #endif 355 mtspr(SPRN_DAC1, thread->dac1); 356 mtspr(SPRN_DAC2, thread->dac2); 357 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 358 mtspr(SPRN_DVC1, thread->dvc1); 359 mtspr(SPRN_DVC2, thread->dvc2); 360 #endif 361 mtspr(SPRN_DBCR0, thread->dbcr0); 362 mtspr(SPRN_DBCR1, thread->dbcr1); 363 #ifdef CONFIG_BOOKE 364 mtspr(SPRN_DBCR2, thread->dbcr2); 365 #endif 366 } 367 /* 368 * Unless neither the old or new thread are making use of the 369 * debug registers, set the debug registers from the values 370 * stored in the new thread. 371 */ 372 static void switch_booke_debug_regs(struct thread_struct *new_thread) 373 { 374 if ((current->thread.dbcr0 & DBCR0_IDM) 375 || (new_thread->dbcr0 & DBCR0_IDM)) 376 prime_debug_regs(new_thread); 377 } 378 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 379 #ifndef CONFIG_HAVE_HW_BREAKPOINT 380 static void set_debug_reg_defaults(struct thread_struct *thread) 381 { 382 thread->hw_brk.address = 0; 383 thread->hw_brk.type = 0; 384 set_breakpoint(&thread->hw_brk); 385 } 386 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 387 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 388 389 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 390 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 391 { 392 mtspr(SPRN_DAC1, dabr); 393 #ifdef CONFIG_PPC_47x 394 isync(); 395 #endif 396 return 0; 397 } 398 #elif defined(CONFIG_PPC_BOOK3S) 399 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 400 { 401 mtspr(SPRN_DABR, dabr); 402 mtspr(SPRN_DABRX, dabrx); 403 return 0; 404 } 405 #else 406 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 407 { 408 return -EINVAL; 409 } 410 #endif 411 412 static inline int set_dabr(struct arch_hw_breakpoint *brk) 413 { 414 unsigned long dabr, dabrx; 415 416 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 417 dabrx = ((brk->type >> 3) & 0x7); 418 419 if (ppc_md.set_dabr) 420 return ppc_md.set_dabr(dabr, dabrx); 421 422 return __set_dabr(dabr, dabrx); 423 } 424 425 static inline int set_dawr(struct arch_hw_breakpoint *brk) 426 { 427 unsigned long dawr, dawrx, mrd; 428 429 dawr = brk->address; 430 431 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 432 << (63 - 58); //* read/write bits */ 433 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 434 << (63 - 59); //* translate */ 435 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 436 >> 3; //* PRIM bits */ 437 /* dawr length is stored in field MDR bits 48:53. Matches range in 438 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 439 0b111111=64DW. 440 brk->len is in bytes. 441 This aligns up to double word size, shifts and does the bias. 442 */ 443 mrd = ((brk->len + 7) >> 3) - 1; 444 dawrx |= (mrd & 0x3f) << (63 - 53); 445 446 if (ppc_md.set_dawr) 447 return ppc_md.set_dawr(dawr, dawrx); 448 mtspr(SPRN_DAWR, dawr); 449 mtspr(SPRN_DAWRX, dawrx); 450 return 0; 451 } 452 453 int set_breakpoint(struct arch_hw_breakpoint *brk) 454 { 455 __get_cpu_var(current_brk) = *brk; 456 457 if (cpu_has_feature(CPU_FTR_DAWR)) 458 return set_dawr(brk); 459 460 return set_dabr(brk); 461 } 462 463 #ifdef CONFIG_PPC64 464 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 465 #endif 466 467 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 468 struct arch_hw_breakpoint *b) 469 { 470 if (a->address != b->address) 471 return false; 472 if (a->type != b->type) 473 return false; 474 if (a->len != b->len) 475 return false; 476 return true; 477 } 478 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 479 static inline void tm_reclaim_task(struct task_struct *tsk) 480 { 481 /* We have to work out if we're switching from/to a task that's in the 482 * middle of a transaction. 483 * 484 * In switching we need to maintain a 2nd register state as 485 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 486 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 487 * (current) FPRs into oldtask->thread.transact_fpr[]. 488 * 489 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 490 */ 491 struct thread_struct *thr = &tsk->thread; 492 493 if (!thr->regs) 494 return; 495 496 if (!MSR_TM_ACTIVE(thr->regs->msr)) 497 goto out_and_saveregs; 498 499 /* Stash the original thread MSR, as giveup_fpu et al will 500 * modify it. We hold onto it to see whether the task used 501 * FP & vector regs. 502 */ 503 thr->tm_orig_msr = thr->regs->msr; 504 505 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 506 "ccr=%lx, msr=%lx, trap=%lx)\n", 507 tsk->pid, thr->regs->nip, 508 thr->regs->ccr, thr->regs->msr, 509 thr->regs->trap); 510 511 tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED); 512 513 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 514 tsk->pid); 515 516 out_and_saveregs: 517 /* Always save the regs here, even if a transaction's not active. 518 * This context-switches a thread's TM info SPRs. We do it here to 519 * be consistent with the restore path (in recheckpoint) which 520 * cannot happen later in _switch(). 521 */ 522 tm_save_sprs(thr); 523 } 524 525 static inline void tm_recheckpoint_new_task(struct task_struct *new) 526 { 527 unsigned long msr; 528 529 if (!cpu_has_feature(CPU_FTR_TM)) 530 return; 531 532 /* Recheckpoint the registers of the thread we're about to switch to. 533 * 534 * If the task was using FP, we non-lazily reload both the original and 535 * the speculative FP register states. This is because the kernel 536 * doesn't see if/when a TM rollback occurs, so if we take an FP 537 * unavoidable later, we are unable to determine which set of FP regs 538 * need to be restored. 539 */ 540 if (!new->thread.regs) 541 return; 542 543 /* The TM SPRs are restored here, so that TEXASR.FS can be set 544 * before the trecheckpoint and no explosion occurs. 545 */ 546 tm_restore_sprs(&new->thread); 547 548 if (!MSR_TM_ACTIVE(new->thread.regs->msr)) 549 return; 550 msr = new->thread.tm_orig_msr; 551 /* Recheckpoint to restore original checkpointed register state. */ 552 TM_DEBUG("*** tm_recheckpoint of pid %d " 553 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 554 new->pid, new->thread.regs->msr, msr); 555 556 /* This loads the checkpointed FP/VEC state, if used */ 557 tm_recheckpoint(&new->thread, msr); 558 559 /* This loads the speculative FP/VEC state, if used */ 560 if (msr & MSR_FP) { 561 do_load_up_transact_fpu(&new->thread); 562 new->thread.regs->msr |= 563 (MSR_FP | new->thread.fpexc_mode); 564 } 565 #ifdef CONFIG_ALTIVEC 566 if (msr & MSR_VEC) { 567 do_load_up_transact_altivec(&new->thread); 568 new->thread.regs->msr |= MSR_VEC; 569 } 570 #endif 571 /* We may as well turn on VSX too since all the state is restored now */ 572 if (msr & MSR_VSX) 573 new->thread.regs->msr |= MSR_VSX; 574 575 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 576 "(kernel msr 0x%lx)\n", 577 new->pid, mfmsr()); 578 } 579 580 static inline void __switch_to_tm(struct task_struct *prev) 581 { 582 if (cpu_has_feature(CPU_FTR_TM)) { 583 tm_enable(); 584 tm_reclaim_task(prev); 585 } 586 } 587 #else 588 #define tm_recheckpoint_new_task(new) 589 #define __switch_to_tm(prev) 590 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 591 592 struct task_struct *__switch_to(struct task_struct *prev, 593 struct task_struct *new) 594 { 595 struct thread_struct *new_thread, *old_thread; 596 unsigned long flags; 597 struct task_struct *last; 598 #ifdef CONFIG_PPC_BOOK3S_64 599 struct ppc64_tlb_batch *batch; 600 #endif 601 602 __switch_to_tm(prev); 603 604 #ifdef CONFIG_SMP 605 /* avoid complexity of lazy save/restore of fpu 606 * by just saving it every time we switch out if 607 * this task used the fpu during the last quantum. 608 * 609 * If it tries to use the fpu again, it'll trap and 610 * reload its fp regs. So we don't have to do a restore 611 * every switch, just a save. 612 * -- Cort 613 */ 614 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) 615 giveup_fpu(prev); 616 #ifdef CONFIG_ALTIVEC 617 /* 618 * If the previous thread used altivec in the last quantum 619 * (thus changing altivec regs) then save them. 620 * We used to check the VRSAVE register but not all apps 621 * set it, so we don't rely on it now (and in fact we need 622 * to save & restore VSCR even if VRSAVE == 0). -- paulus 623 * 624 * On SMP we always save/restore altivec regs just to avoid the 625 * complexity of changing processors. 626 * -- Cort 627 */ 628 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) 629 giveup_altivec(prev); 630 #endif /* CONFIG_ALTIVEC */ 631 #ifdef CONFIG_VSX 632 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) 633 /* VMX and FPU registers are already save here */ 634 __giveup_vsx(prev); 635 #endif /* CONFIG_VSX */ 636 #ifdef CONFIG_SPE 637 /* 638 * If the previous thread used spe in the last quantum 639 * (thus changing spe regs) then save them. 640 * 641 * On SMP we always save/restore spe regs just to avoid the 642 * complexity of changing processors. 643 */ 644 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) 645 giveup_spe(prev); 646 #endif /* CONFIG_SPE */ 647 648 #else /* CONFIG_SMP */ 649 #ifdef CONFIG_ALTIVEC 650 /* Avoid the trap. On smp this this never happens since 651 * we don't set last_task_used_altivec -- Cort 652 */ 653 if (new->thread.regs && last_task_used_altivec == new) 654 new->thread.regs->msr |= MSR_VEC; 655 #endif /* CONFIG_ALTIVEC */ 656 #ifdef CONFIG_VSX 657 if (new->thread.regs && last_task_used_vsx == new) 658 new->thread.regs->msr |= MSR_VSX; 659 #endif /* CONFIG_VSX */ 660 #ifdef CONFIG_SPE 661 /* Avoid the trap. On smp this this never happens since 662 * we don't set last_task_used_spe 663 */ 664 if (new->thread.regs && last_task_used_spe == new) 665 new->thread.regs->msr |= MSR_SPE; 666 #endif /* CONFIG_SPE */ 667 668 #endif /* CONFIG_SMP */ 669 670 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 671 switch_booke_debug_regs(&new->thread); 672 #else 673 /* 674 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 675 * schedule DABR 676 */ 677 #ifndef CONFIG_HAVE_HW_BREAKPOINT 678 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) 679 set_breakpoint(&new->thread.hw_brk); 680 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 681 #endif 682 683 684 new_thread = &new->thread; 685 old_thread = ¤t->thread; 686 687 #ifdef CONFIG_PPC64 688 /* 689 * Collect processor utilization data per process 690 */ 691 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 692 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); 693 long unsigned start_tb, current_tb; 694 start_tb = old_thread->start_tb; 695 cu->current_tb = current_tb = mfspr(SPRN_PURR); 696 old_thread->accum_tb += (current_tb - start_tb); 697 new_thread->start_tb = current_tb; 698 } 699 #endif /* CONFIG_PPC64 */ 700 701 #ifdef CONFIG_PPC_BOOK3S_64 702 batch = &__get_cpu_var(ppc64_tlb_batch); 703 if (batch->active) { 704 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 705 if (batch->index) 706 __flush_tlb_pending(batch); 707 batch->active = 0; 708 } 709 #endif /* CONFIG_PPC_BOOK3S_64 */ 710 711 local_irq_save(flags); 712 713 /* 714 * We can't take a PMU exception inside _switch() since there is a 715 * window where the kernel stack SLB and the kernel stack are out 716 * of sync. Hard disable here. 717 */ 718 hard_irq_disable(); 719 720 tm_recheckpoint_new_task(new); 721 722 last = _switch(old_thread, new_thread); 723 724 #ifdef CONFIG_PPC_BOOK3S_64 725 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 726 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 727 batch = &__get_cpu_var(ppc64_tlb_batch); 728 batch->active = 1; 729 } 730 #endif /* CONFIG_PPC_BOOK3S_64 */ 731 732 local_irq_restore(flags); 733 734 return last; 735 } 736 737 static int instructions_to_print = 16; 738 739 static void show_instructions(struct pt_regs *regs) 740 { 741 int i; 742 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 743 sizeof(int)); 744 745 printk("Instruction dump:"); 746 747 for (i = 0; i < instructions_to_print; i++) { 748 int instr; 749 750 if (!(i % 8)) 751 printk("\n"); 752 753 #if !defined(CONFIG_BOOKE) 754 /* If executing with the IMMU off, adjust pc rather 755 * than print XXXXXXXX. 756 */ 757 if (!(regs->msr & MSR_IR)) 758 pc = (unsigned long)phys_to_virt(pc); 759 #endif 760 761 /* We use __get_user here *only* to avoid an OOPS on a 762 * bad address because the pc *should* only be a 763 * kernel address. 764 */ 765 if (!__kernel_text_address(pc) || 766 __get_user(instr, (unsigned int __user *)pc)) { 767 printk(KERN_CONT "XXXXXXXX "); 768 } else { 769 if (regs->nip == pc) 770 printk(KERN_CONT "<%08x> ", instr); 771 else 772 printk(KERN_CONT "%08x ", instr); 773 } 774 775 pc += sizeof(int); 776 } 777 778 printk("\n"); 779 } 780 781 static struct regbit { 782 unsigned long bit; 783 const char *name; 784 } msr_bits[] = { 785 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 786 {MSR_SF, "SF"}, 787 {MSR_HV, "HV"}, 788 #endif 789 {MSR_VEC, "VEC"}, 790 {MSR_VSX, "VSX"}, 791 #ifdef CONFIG_BOOKE 792 {MSR_CE, "CE"}, 793 #endif 794 {MSR_EE, "EE"}, 795 {MSR_PR, "PR"}, 796 {MSR_FP, "FP"}, 797 {MSR_ME, "ME"}, 798 #ifdef CONFIG_BOOKE 799 {MSR_DE, "DE"}, 800 #else 801 {MSR_SE, "SE"}, 802 {MSR_BE, "BE"}, 803 #endif 804 {MSR_IR, "IR"}, 805 {MSR_DR, "DR"}, 806 {MSR_PMM, "PMM"}, 807 #ifndef CONFIG_BOOKE 808 {MSR_RI, "RI"}, 809 {MSR_LE, "LE"}, 810 #endif 811 {0, NULL} 812 }; 813 814 static void printbits(unsigned long val, struct regbit *bits) 815 { 816 const char *sep = ""; 817 818 printk("<"); 819 for (; bits->bit; ++bits) 820 if (val & bits->bit) { 821 printk("%s%s", sep, bits->name); 822 sep = ","; 823 } 824 printk(">"); 825 } 826 827 #ifdef CONFIG_PPC64 828 #define REG "%016lx" 829 #define REGS_PER_LINE 4 830 #define LAST_VOLATILE 13 831 #else 832 #define REG "%08lx" 833 #define REGS_PER_LINE 8 834 #define LAST_VOLATILE 12 835 #endif 836 837 void show_regs(struct pt_regs * regs) 838 { 839 int i, trap; 840 841 show_regs_print_info(KERN_DEFAULT); 842 843 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 844 regs->nip, regs->link, regs->ctr); 845 printk("REGS: %p TRAP: %04lx %s (%s)\n", 846 regs, regs->trap, print_tainted(), init_utsname()->release); 847 printk("MSR: "REG" ", regs->msr); 848 printbits(regs->msr, msr_bits); 849 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 850 #ifdef CONFIG_PPC64 851 printk("SOFTE: %ld\n", regs->softe); 852 #endif 853 trap = TRAP(regs); 854 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 855 printk("CFAR: "REG"\n", regs->orig_gpr3); 856 if (trap == 0x300 || trap == 0x600) 857 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 858 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr); 859 #else 860 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr); 861 #endif 862 863 for (i = 0; i < 32; i++) { 864 if ((i % REGS_PER_LINE) == 0) 865 printk("\nGPR%02d: ", i); 866 printk(REG " ", regs->gpr[i]); 867 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 868 break; 869 } 870 printk("\n"); 871 #ifdef CONFIG_KALLSYMS 872 /* 873 * Lookup NIP late so we have the best change of getting the 874 * above info out without failing 875 */ 876 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 877 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 878 #endif 879 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 880 printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch); 881 #endif 882 show_stack(current, (unsigned long *) regs->gpr[1]); 883 if (!user_mode(regs)) 884 show_instructions(regs); 885 } 886 887 void exit_thread(void) 888 { 889 discard_lazy_cpu_state(); 890 } 891 892 void flush_thread(void) 893 { 894 discard_lazy_cpu_state(); 895 896 #ifdef CONFIG_HAVE_HW_BREAKPOINT 897 flush_ptrace_hw_breakpoint(current); 898 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 899 set_debug_reg_defaults(¤t->thread); 900 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 901 } 902 903 void 904 release_thread(struct task_struct *t) 905 { 906 } 907 908 /* 909 * this gets called so that we can store coprocessor state into memory and 910 * copy the current task into the new thread. 911 */ 912 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 913 { 914 flush_fp_to_thread(src); 915 flush_altivec_to_thread(src); 916 flush_vsx_to_thread(src); 917 flush_spe_to_thread(src); 918 *dst = *src; 919 return 0; 920 } 921 922 /* 923 * Copy a thread.. 924 */ 925 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */ 926 927 int copy_thread(unsigned long clone_flags, unsigned long usp, 928 unsigned long arg, struct task_struct *p) 929 { 930 struct pt_regs *childregs, *kregs; 931 extern void ret_from_fork(void); 932 extern void ret_from_kernel_thread(void); 933 void (*f)(void); 934 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 935 936 /* Copy registers */ 937 sp -= sizeof(struct pt_regs); 938 childregs = (struct pt_regs *) sp; 939 if (unlikely(p->flags & PF_KTHREAD)) { 940 struct thread_info *ti = (void *)task_stack_page(p); 941 memset(childregs, 0, sizeof(struct pt_regs)); 942 childregs->gpr[1] = sp + sizeof(struct pt_regs); 943 childregs->gpr[14] = usp; /* function */ 944 #ifdef CONFIG_PPC64 945 clear_tsk_thread_flag(p, TIF_32BIT); 946 childregs->softe = 1; 947 #endif 948 childregs->gpr[15] = arg; 949 p->thread.regs = NULL; /* no user register state */ 950 ti->flags |= _TIF_RESTOREALL; 951 f = ret_from_kernel_thread; 952 } else { 953 struct pt_regs *regs = current_pt_regs(); 954 CHECK_FULL_REGS(regs); 955 *childregs = *regs; 956 if (usp) 957 childregs->gpr[1] = usp; 958 p->thread.regs = childregs; 959 childregs->gpr[3] = 0; /* Result from fork() */ 960 if (clone_flags & CLONE_SETTLS) { 961 #ifdef CONFIG_PPC64 962 if (!is_32bit_task()) 963 childregs->gpr[13] = childregs->gpr[6]; 964 else 965 #endif 966 childregs->gpr[2] = childregs->gpr[6]; 967 } 968 969 f = ret_from_fork; 970 } 971 sp -= STACK_FRAME_OVERHEAD; 972 973 /* 974 * The way this works is that at some point in the future 975 * some task will call _switch to switch to the new task. 976 * That will pop off the stack frame created below and start 977 * the new task running at ret_from_fork. The new task will 978 * do some house keeping and then return from the fork or clone 979 * system call, using the stack frame created above. 980 */ 981 ((unsigned long *)sp)[0] = 0; 982 sp -= sizeof(struct pt_regs); 983 kregs = (struct pt_regs *) sp; 984 sp -= STACK_FRAME_OVERHEAD; 985 p->thread.ksp = sp; 986 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 987 _ALIGN_UP(sizeof(struct thread_info), 16); 988 989 #ifdef CONFIG_HAVE_HW_BREAKPOINT 990 p->thread.ptrace_bps[0] = NULL; 991 #endif 992 993 #ifdef CONFIG_PPC_STD_MMU_64 994 if (mmu_has_feature(MMU_FTR_SLB)) { 995 unsigned long sp_vsid; 996 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 997 998 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 999 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1000 << SLB_VSID_SHIFT_1T; 1001 else 1002 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1003 << SLB_VSID_SHIFT; 1004 sp_vsid |= SLB_VSID_KERNEL | llp; 1005 p->thread.ksp_vsid = sp_vsid; 1006 } 1007 #endif /* CONFIG_PPC_STD_MMU_64 */ 1008 #ifdef CONFIG_PPC64 1009 if (cpu_has_feature(CPU_FTR_DSCR)) { 1010 p->thread.dscr_inherit = current->thread.dscr_inherit; 1011 p->thread.dscr = current->thread.dscr; 1012 } 1013 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1014 p->thread.ppr = INIT_PPR; 1015 #endif 1016 /* 1017 * The PPC64 ABI makes use of a TOC to contain function 1018 * pointers. The function (ret_from_except) is actually a pointer 1019 * to the TOC entry. The first entry is a pointer to the actual 1020 * function. 1021 */ 1022 #ifdef CONFIG_PPC64 1023 kregs->nip = *((unsigned long *)f); 1024 #else 1025 kregs->nip = (unsigned long)f; 1026 #endif 1027 return 0; 1028 } 1029 1030 /* 1031 * Set up a thread for executing a new program 1032 */ 1033 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1034 { 1035 #ifdef CONFIG_PPC64 1036 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1037 #endif 1038 1039 /* 1040 * If we exec out of a kernel thread then thread.regs will not be 1041 * set. Do it now. 1042 */ 1043 if (!current->thread.regs) { 1044 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1045 current->thread.regs = regs - 1; 1046 } 1047 1048 memset(regs->gpr, 0, sizeof(regs->gpr)); 1049 regs->ctr = 0; 1050 regs->link = 0; 1051 regs->xer = 0; 1052 regs->ccr = 0; 1053 regs->gpr[1] = sp; 1054 1055 /* 1056 * We have just cleared all the nonvolatile GPRs, so make 1057 * FULL_REGS(regs) return true. This is necessary to allow 1058 * ptrace to examine the thread immediately after exec. 1059 */ 1060 regs->trap &= ~1UL; 1061 1062 #ifdef CONFIG_PPC32 1063 regs->mq = 0; 1064 regs->nip = start; 1065 regs->msr = MSR_USER; 1066 #else 1067 if (!is_32bit_task()) { 1068 unsigned long entry, toc; 1069 1070 /* start is a relocated pointer to the function descriptor for 1071 * the elf _start routine. The first entry in the function 1072 * descriptor is the entry address of _start and the second 1073 * entry is the TOC value we need to use. 1074 */ 1075 __get_user(entry, (unsigned long __user *)start); 1076 __get_user(toc, (unsigned long __user *)start+1); 1077 1078 /* Check whether the e_entry function descriptor entries 1079 * need to be relocated before we can use them. 1080 */ 1081 if (load_addr != 0) { 1082 entry += load_addr; 1083 toc += load_addr; 1084 } 1085 regs->nip = entry; 1086 regs->gpr[2] = toc; 1087 regs->msr = MSR_USER64; 1088 } else { 1089 regs->nip = start; 1090 regs->gpr[2] = 0; 1091 regs->msr = MSR_USER32; 1092 } 1093 #endif 1094 discard_lazy_cpu_state(); 1095 #ifdef CONFIG_VSX 1096 current->thread.used_vsr = 0; 1097 #endif 1098 memset(current->thread.fpr, 0, sizeof(current->thread.fpr)); 1099 current->thread.fpscr.val = 0; 1100 #ifdef CONFIG_ALTIVEC 1101 memset(current->thread.vr, 0, sizeof(current->thread.vr)); 1102 memset(¤t->thread.vscr, 0, sizeof(current->thread.vscr)); 1103 current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1104 current->thread.vrsave = 0; 1105 current->thread.used_vr = 0; 1106 #endif /* CONFIG_ALTIVEC */ 1107 #ifdef CONFIG_SPE 1108 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1109 current->thread.acc = 0; 1110 current->thread.spefscr = 0; 1111 current->thread.used_spe = 0; 1112 #endif /* CONFIG_SPE */ 1113 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1114 if (cpu_has_feature(CPU_FTR_TM)) 1115 regs->msr |= MSR_TM; 1116 current->thread.tm_tfhar = 0; 1117 current->thread.tm_texasr = 0; 1118 current->thread.tm_tfiar = 0; 1119 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1120 } 1121 1122 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1123 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1124 1125 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1126 { 1127 struct pt_regs *regs = tsk->thread.regs; 1128 1129 /* This is a bit hairy. If we are an SPE enabled processor 1130 * (have embedded fp) we store the IEEE exception enable flags in 1131 * fpexc_mode. fpexc_mode is also used for setting FP exception 1132 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1133 if (val & PR_FP_EXC_SW_ENABLE) { 1134 #ifdef CONFIG_SPE 1135 if (cpu_has_feature(CPU_FTR_SPE)) { 1136 tsk->thread.fpexc_mode = val & 1137 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1138 return 0; 1139 } else { 1140 return -EINVAL; 1141 } 1142 #else 1143 return -EINVAL; 1144 #endif 1145 } 1146 1147 /* on a CONFIG_SPE this does not hurt us. The bits that 1148 * __pack_fe01 use do not overlap with bits used for 1149 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1150 * on CONFIG_SPE implementations are reserved so writing to 1151 * them does not change anything */ 1152 if (val > PR_FP_EXC_PRECISE) 1153 return -EINVAL; 1154 tsk->thread.fpexc_mode = __pack_fe01(val); 1155 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1156 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1157 | tsk->thread.fpexc_mode; 1158 return 0; 1159 } 1160 1161 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1162 { 1163 unsigned int val; 1164 1165 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1166 #ifdef CONFIG_SPE 1167 if (cpu_has_feature(CPU_FTR_SPE)) 1168 val = tsk->thread.fpexc_mode; 1169 else 1170 return -EINVAL; 1171 #else 1172 return -EINVAL; 1173 #endif 1174 else 1175 val = __unpack_fe01(tsk->thread.fpexc_mode); 1176 return put_user(val, (unsigned int __user *) adr); 1177 } 1178 1179 int set_endian(struct task_struct *tsk, unsigned int val) 1180 { 1181 struct pt_regs *regs = tsk->thread.regs; 1182 1183 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1184 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1185 return -EINVAL; 1186 1187 if (regs == NULL) 1188 return -EINVAL; 1189 1190 if (val == PR_ENDIAN_BIG) 1191 regs->msr &= ~MSR_LE; 1192 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1193 regs->msr |= MSR_LE; 1194 else 1195 return -EINVAL; 1196 1197 return 0; 1198 } 1199 1200 int get_endian(struct task_struct *tsk, unsigned long adr) 1201 { 1202 struct pt_regs *regs = tsk->thread.regs; 1203 unsigned int val; 1204 1205 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1206 !cpu_has_feature(CPU_FTR_REAL_LE)) 1207 return -EINVAL; 1208 1209 if (regs == NULL) 1210 return -EINVAL; 1211 1212 if (regs->msr & MSR_LE) { 1213 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1214 val = PR_ENDIAN_LITTLE; 1215 else 1216 val = PR_ENDIAN_PPC_LITTLE; 1217 } else 1218 val = PR_ENDIAN_BIG; 1219 1220 return put_user(val, (unsigned int __user *)adr); 1221 } 1222 1223 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1224 { 1225 tsk->thread.align_ctl = val; 1226 return 0; 1227 } 1228 1229 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1230 { 1231 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1232 } 1233 1234 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1235 unsigned long nbytes) 1236 { 1237 unsigned long stack_page; 1238 unsigned long cpu = task_cpu(p); 1239 1240 /* 1241 * Avoid crashing if the stack has overflowed and corrupted 1242 * task_cpu(p), which is in the thread_info struct. 1243 */ 1244 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1245 stack_page = (unsigned long) hardirq_ctx[cpu]; 1246 if (sp >= stack_page + sizeof(struct thread_struct) 1247 && sp <= stack_page + THREAD_SIZE - nbytes) 1248 return 1; 1249 1250 stack_page = (unsigned long) softirq_ctx[cpu]; 1251 if (sp >= stack_page + sizeof(struct thread_struct) 1252 && sp <= stack_page + THREAD_SIZE - nbytes) 1253 return 1; 1254 } 1255 return 0; 1256 } 1257 1258 int validate_sp(unsigned long sp, struct task_struct *p, 1259 unsigned long nbytes) 1260 { 1261 unsigned long stack_page = (unsigned long)task_stack_page(p); 1262 1263 if (sp >= stack_page + sizeof(struct thread_struct) 1264 && sp <= stack_page + THREAD_SIZE - nbytes) 1265 return 1; 1266 1267 return valid_irq_stack(sp, p, nbytes); 1268 } 1269 1270 EXPORT_SYMBOL(validate_sp); 1271 1272 unsigned long get_wchan(struct task_struct *p) 1273 { 1274 unsigned long ip, sp; 1275 int count = 0; 1276 1277 if (!p || p == current || p->state == TASK_RUNNING) 1278 return 0; 1279 1280 sp = p->thread.ksp; 1281 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1282 return 0; 1283 1284 do { 1285 sp = *(unsigned long *)sp; 1286 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1287 return 0; 1288 if (count > 0) { 1289 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1290 if (!in_sched_functions(ip)) 1291 return ip; 1292 } 1293 } while (count++ < 16); 1294 return 0; 1295 } 1296 1297 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1298 1299 void show_stack(struct task_struct *tsk, unsigned long *stack) 1300 { 1301 unsigned long sp, ip, lr, newsp; 1302 int count = 0; 1303 int firstframe = 1; 1304 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1305 int curr_frame = current->curr_ret_stack; 1306 extern void return_to_handler(void); 1307 unsigned long rth = (unsigned long)return_to_handler; 1308 unsigned long mrth = -1; 1309 #ifdef CONFIG_PPC64 1310 extern void mod_return_to_handler(void); 1311 rth = *(unsigned long *)rth; 1312 mrth = (unsigned long)mod_return_to_handler; 1313 mrth = *(unsigned long *)mrth; 1314 #endif 1315 #endif 1316 1317 sp = (unsigned long) stack; 1318 if (tsk == NULL) 1319 tsk = current; 1320 if (sp == 0) { 1321 if (tsk == current) 1322 asm("mr %0,1" : "=r" (sp)); 1323 else 1324 sp = tsk->thread.ksp; 1325 } 1326 1327 lr = 0; 1328 printk("Call Trace:\n"); 1329 do { 1330 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1331 return; 1332 1333 stack = (unsigned long *) sp; 1334 newsp = stack[0]; 1335 ip = stack[STACK_FRAME_LR_SAVE]; 1336 if (!firstframe || ip != lr) { 1337 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1338 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1339 if ((ip == rth || ip == mrth) && curr_frame >= 0) { 1340 printk(" (%pS)", 1341 (void *)current->ret_stack[curr_frame].ret); 1342 curr_frame--; 1343 } 1344 #endif 1345 if (firstframe) 1346 printk(" (unreliable)"); 1347 printk("\n"); 1348 } 1349 firstframe = 0; 1350 1351 /* 1352 * See if this is an exception frame. 1353 * We look for the "regshere" marker in the current frame. 1354 */ 1355 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1356 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1357 struct pt_regs *regs = (struct pt_regs *) 1358 (sp + STACK_FRAME_OVERHEAD); 1359 lr = regs->link; 1360 printk("--- Exception: %lx at %pS\n LR = %pS\n", 1361 regs->trap, (void *)regs->nip, (void *)lr); 1362 firstframe = 1; 1363 } 1364 1365 sp = newsp; 1366 } while (count++ < kstack_depth_to_print); 1367 } 1368 1369 #ifdef CONFIG_PPC64 1370 /* Called with hard IRQs off */ 1371 void __ppc64_runlatch_on(void) 1372 { 1373 struct thread_info *ti = current_thread_info(); 1374 unsigned long ctrl; 1375 1376 ctrl = mfspr(SPRN_CTRLF); 1377 ctrl |= CTRL_RUNLATCH; 1378 mtspr(SPRN_CTRLT, ctrl); 1379 1380 ti->local_flags |= _TLF_RUNLATCH; 1381 } 1382 1383 /* Called with hard IRQs off */ 1384 void __ppc64_runlatch_off(void) 1385 { 1386 struct thread_info *ti = current_thread_info(); 1387 unsigned long ctrl; 1388 1389 ti->local_flags &= ~_TLF_RUNLATCH; 1390 1391 ctrl = mfspr(SPRN_CTRLF); 1392 ctrl &= ~CTRL_RUNLATCH; 1393 mtspr(SPRN_CTRLT, ctrl); 1394 } 1395 #endif /* CONFIG_PPC64 */ 1396 1397 unsigned long arch_align_stack(unsigned long sp) 1398 { 1399 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1400 sp -= get_random_int() & ~PAGE_MASK; 1401 return sp & ~0xf; 1402 } 1403 1404 static inline unsigned long brk_rnd(void) 1405 { 1406 unsigned long rnd = 0; 1407 1408 /* 8MB for 32bit, 1GB for 64bit */ 1409 if (is_32bit_task()) 1410 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); 1411 else 1412 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); 1413 1414 return rnd << PAGE_SHIFT; 1415 } 1416 1417 unsigned long arch_randomize_brk(struct mm_struct *mm) 1418 { 1419 unsigned long base = mm->brk; 1420 unsigned long ret; 1421 1422 #ifdef CONFIG_PPC_STD_MMU_64 1423 /* 1424 * If we are using 1TB segments and we are allowed to randomise 1425 * the heap, we can put it above 1TB so it is backed by a 1TB 1426 * segment. Otherwise the heap will be in the bottom 1TB 1427 * which always uses 256MB segments and this may result in a 1428 * performance penalty. 1429 */ 1430 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1431 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1432 #endif 1433 1434 ret = PAGE_ALIGN(base + brk_rnd()); 1435 1436 if (ret < mm->brk) 1437 return mm->brk; 1438 1439 return ret; 1440 } 1441 1442 unsigned long randomize_et_dyn(unsigned long base) 1443 { 1444 unsigned long ret = PAGE_ALIGN(base + brk_rnd()); 1445 1446 if (ret < base) 1447 return base; 1448 1449 return ret; 1450 } 1451