1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/init.h> 29 #include <linux/prctl.h> 30 #include <linux/init_task.h> 31 #include <linux/export.h> 32 #include <linux/kallsyms.h> 33 #include <linux/mqueue.h> 34 #include <linux/hardirq.h> 35 #include <linux/utsname.h> 36 #include <linux/ftrace.h> 37 #include <linux/kernel_stat.h> 38 #include <linux/personality.h> 39 #include <linux/random.h> 40 #include <linux/hw_breakpoint.h> 41 42 #include <asm/pgtable.h> 43 #include <asm/uaccess.h> 44 #include <asm/io.h> 45 #include <asm/processor.h> 46 #include <asm/mmu.h> 47 #include <asm/prom.h> 48 #include <asm/machdep.h> 49 #include <asm/time.h> 50 #include <asm/runlatch.h> 51 #include <asm/syscalls.h> 52 #include <asm/switch_to.h> 53 #include <asm/tm.h> 54 #include <asm/debug.h> 55 #ifdef CONFIG_PPC64 56 #include <asm/firmware.h> 57 #endif 58 #include <linux/kprobes.h> 59 #include <linux/kdebug.h> 60 61 /* Transactional Memory debug */ 62 #ifdef TM_DEBUG_SW 63 #define TM_DEBUG(x...) printk(KERN_INFO x) 64 #else 65 #define TM_DEBUG(x...) do { } while(0) 66 #endif 67 68 extern unsigned long _get_SP(void); 69 70 #ifndef CONFIG_SMP 71 struct task_struct *last_task_used_math = NULL; 72 struct task_struct *last_task_used_altivec = NULL; 73 struct task_struct *last_task_used_vsx = NULL; 74 struct task_struct *last_task_used_spe = NULL; 75 #endif 76 77 #ifdef CONFIG_PPC_FPU 78 /* 79 * Make sure the floating-point register state in the 80 * the thread_struct is up to date for task tsk. 81 */ 82 void flush_fp_to_thread(struct task_struct *tsk) 83 { 84 if (tsk->thread.regs) { 85 /* 86 * We need to disable preemption here because if we didn't, 87 * another process could get scheduled after the regs->msr 88 * test but before we have finished saving the FP registers 89 * to the thread_struct. That process could take over the 90 * FPU, and then when we get scheduled again we would store 91 * bogus values for the remaining FP registers. 92 */ 93 preempt_disable(); 94 if (tsk->thread.regs->msr & MSR_FP) { 95 #ifdef CONFIG_SMP 96 /* 97 * This should only ever be called for current or 98 * for a stopped child process. Since we save away 99 * the FP register state on context switch on SMP, 100 * there is something wrong if a stopped child appears 101 * to still have its FP state in the CPU registers. 102 */ 103 BUG_ON(tsk != current); 104 #endif 105 giveup_fpu(tsk); 106 } 107 preempt_enable(); 108 } 109 } 110 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 111 #endif 112 113 void enable_kernel_fp(void) 114 { 115 WARN_ON(preemptible()); 116 117 #ifdef CONFIG_SMP 118 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) 119 giveup_fpu(current); 120 else 121 giveup_fpu(NULL); /* just enables FP for kernel */ 122 #else 123 giveup_fpu(last_task_used_math); 124 #endif /* CONFIG_SMP */ 125 } 126 EXPORT_SYMBOL(enable_kernel_fp); 127 128 #ifdef CONFIG_ALTIVEC 129 void enable_kernel_altivec(void) 130 { 131 WARN_ON(preemptible()); 132 133 #ifdef CONFIG_SMP 134 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) 135 giveup_altivec(current); 136 else 137 giveup_altivec_notask(); 138 #else 139 giveup_altivec(last_task_used_altivec); 140 #endif /* CONFIG_SMP */ 141 } 142 EXPORT_SYMBOL(enable_kernel_altivec); 143 144 /* 145 * Make sure the VMX/Altivec register state in the 146 * the thread_struct is up to date for task tsk. 147 */ 148 void flush_altivec_to_thread(struct task_struct *tsk) 149 { 150 if (tsk->thread.regs) { 151 preempt_disable(); 152 if (tsk->thread.regs->msr & MSR_VEC) { 153 #ifdef CONFIG_SMP 154 BUG_ON(tsk != current); 155 #endif 156 giveup_altivec(tsk); 157 } 158 preempt_enable(); 159 } 160 } 161 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 162 #endif /* CONFIG_ALTIVEC */ 163 164 #ifdef CONFIG_VSX 165 #if 0 166 /* not currently used, but some crazy RAID module might want to later */ 167 void enable_kernel_vsx(void) 168 { 169 WARN_ON(preemptible()); 170 171 #ifdef CONFIG_SMP 172 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) 173 giveup_vsx(current); 174 else 175 giveup_vsx(NULL); /* just enable vsx for kernel - force */ 176 #else 177 giveup_vsx(last_task_used_vsx); 178 #endif /* CONFIG_SMP */ 179 } 180 EXPORT_SYMBOL(enable_kernel_vsx); 181 #endif 182 183 void giveup_vsx(struct task_struct *tsk) 184 { 185 giveup_fpu(tsk); 186 giveup_altivec(tsk); 187 __giveup_vsx(tsk); 188 } 189 190 void flush_vsx_to_thread(struct task_struct *tsk) 191 { 192 if (tsk->thread.regs) { 193 preempt_disable(); 194 if (tsk->thread.regs->msr & MSR_VSX) { 195 #ifdef CONFIG_SMP 196 BUG_ON(tsk != current); 197 #endif 198 giveup_vsx(tsk); 199 } 200 preempt_enable(); 201 } 202 } 203 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 204 #endif /* CONFIG_VSX */ 205 206 #ifdef CONFIG_SPE 207 208 void enable_kernel_spe(void) 209 { 210 WARN_ON(preemptible()); 211 212 #ifdef CONFIG_SMP 213 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) 214 giveup_spe(current); 215 else 216 giveup_spe(NULL); /* just enable SPE for kernel - force */ 217 #else 218 giveup_spe(last_task_used_spe); 219 #endif /* __SMP __ */ 220 } 221 EXPORT_SYMBOL(enable_kernel_spe); 222 223 void flush_spe_to_thread(struct task_struct *tsk) 224 { 225 if (tsk->thread.regs) { 226 preempt_disable(); 227 if (tsk->thread.regs->msr & MSR_SPE) { 228 #ifdef CONFIG_SMP 229 BUG_ON(tsk != current); 230 #endif 231 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 232 giveup_spe(tsk); 233 } 234 preempt_enable(); 235 } 236 } 237 #endif /* CONFIG_SPE */ 238 239 #ifndef CONFIG_SMP 240 /* 241 * If we are doing lazy switching of CPU state (FP, altivec or SPE), 242 * and the current task has some state, discard it. 243 */ 244 void discard_lazy_cpu_state(void) 245 { 246 preempt_disable(); 247 if (last_task_used_math == current) 248 last_task_used_math = NULL; 249 #ifdef CONFIG_ALTIVEC 250 if (last_task_used_altivec == current) 251 last_task_used_altivec = NULL; 252 #endif /* CONFIG_ALTIVEC */ 253 #ifdef CONFIG_VSX 254 if (last_task_used_vsx == current) 255 last_task_used_vsx = NULL; 256 #endif /* CONFIG_VSX */ 257 #ifdef CONFIG_SPE 258 if (last_task_used_spe == current) 259 last_task_used_spe = NULL; 260 #endif 261 preempt_enable(); 262 } 263 #endif /* CONFIG_SMP */ 264 265 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 266 void do_send_trap(struct pt_regs *regs, unsigned long address, 267 unsigned long error_code, int signal_code, int breakpt) 268 { 269 siginfo_t info; 270 271 current->thread.trap_nr = signal_code; 272 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 273 11, SIGSEGV) == NOTIFY_STOP) 274 return; 275 276 /* Deliver the signal to userspace */ 277 info.si_signo = SIGTRAP; 278 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 279 info.si_code = signal_code; 280 info.si_addr = (void __user *)address; 281 force_sig_info(SIGTRAP, &info, current); 282 } 283 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 284 void do_break (struct pt_regs *regs, unsigned long address, 285 unsigned long error_code) 286 { 287 siginfo_t info; 288 289 current->thread.trap_nr = TRAP_HWBKPT; 290 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 291 11, SIGSEGV) == NOTIFY_STOP) 292 return; 293 294 if (debugger_break_match(regs)) 295 return; 296 297 /* Clear the breakpoint */ 298 hw_breakpoint_disable(); 299 300 /* Deliver the signal to userspace */ 301 info.si_signo = SIGTRAP; 302 info.si_errno = 0; 303 info.si_code = TRAP_HWBKPT; 304 info.si_addr = (void __user *)address; 305 force_sig_info(SIGTRAP, &info, current); 306 } 307 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 308 309 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 310 311 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 312 /* 313 * Set the debug registers back to their default "safe" values. 314 */ 315 static void set_debug_reg_defaults(struct thread_struct *thread) 316 { 317 thread->debug.iac1 = thread->debug.iac2 = 0; 318 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 319 thread->debug.iac3 = thread->debug.iac4 = 0; 320 #endif 321 thread->debug.dac1 = thread->debug.dac2 = 0; 322 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 323 thread->debug.dvc1 = thread->debug.dvc2 = 0; 324 #endif 325 thread->debug.dbcr0 = 0; 326 #ifdef CONFIG_BOOKE 327 /* 328 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 329 */ 330 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 331 DBCR1_IAC3US | DBCR1_IAC4US; 332 /* 333 * Force Data Address Compare User/Supervisor bits to be User-only 334 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 335 */ 336 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 337 #else 338 thread->debug.dbcr1 = 0; 339 #endif 340 } 341 342 static void prime_debug_regs(struct debug_reg *debug) 343 { 344 /* 345 * We could have inherited MSR_DE from userspace, since 346 * it doesn't get cleared on exception entry. Make sure 347 * MSR_DE is clear before we enable any debug events. 348 */ 349 mtmsr(mfmsr() & ~MSR_DE); 350 351 mtspr(SPRN_IAC1, debug->iac1); 352 mtspr(SPRN_IAC2, debug->iac2); 353 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 354 mtspr(SPRN_IAC3, debug->iac3); 355 mtspr(SPRN_IAC4, debug->iac4); 356 #endif 357 mtspr(SPRN_DAC1, debug->dac1); 358 mtspr(SPRN_DAC2, debug->dac2); 359 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 360 mtspr(SPRN_DVC1, debug->dvc1); 361 mtspr(SPRN_DVC2, debug->dvc2); 362 #endif 363 mtspr(SPRN_DBCR0, debug->dbcr0); 364 mtspr(SPRN_DBCR1, debug->dbcr1); 365 #ifdef CONFIG_BOOKE 366 mtspr(SPRN_DBCR2, debug->dbcr2); 367 #endif 368 } 369 /* 370 * Unless neither the old or new thread are making use of the 371 * debug registers, set the debug registers from the values 372 * stored in the new thread. 373 */ 374 void switch_booke_debug_regs(struct debug_reg *new_debug) 375 { 376 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 377 || (new_debug->dbcr0 & DBCR0_IDM)) 378 prime_debug_regs(new_debug); 379 } 380 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 381 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 382 #ifndef CONFIG_HAVE_HW_BREAKPOINT 383 static void set_debug_reg_defaults(struct thread_struct *thread) 384 { 385 thread->hw_brk.address = 0; 386 thread->hw_brk.type = 0; 387 set_breakpoint(&thread->hw_brk); 388 } 389 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 390 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 391 392 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 393 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 394 { 395 mtspr(SPRN_DAC1, dabr); 396 #ifdef CONFIG_PPC_47x 397 isync(); 398 #endif 399 return 0; 400 } 401 #elif defined(CONFIG_PPC_BOOK3S) 402 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 403 { 404 mtspr(SPRN_DABR, dabr); 405 if (cpu_has_feature(CPU_FTR_DABRX)) 406 mtspr(SPRN_DABRX, dabrx); 407 return 0; 408 } 409 #else 410 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 411 { 412 return -EINVAL; 413 } 414 #endif 415 416 static inline int set_dabr(struct arch_hw_breakpoint *brk) 417 { 418 unsigned long dabr, dabrx; 419 420 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 421 dabrx = ((brk->type >> 3) & 0x7); 422 423 if (ppc_md.set_dabr) 424 return ppc_md.set_dabr(dabr, dabrx); 425 426 return __set_dabr(dabr, dabrx); 427 } 428 429 static inline int set_dawr(struct arch_hw_breakpoint *brk) 430 { 431 unsigned long dawr, dawrx, mrd; 432 433 dawr = brk->address; 434 435 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 436 << (63 - 58); //* read/write bits */ 437 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 438 << (63 - 59); //* translate */ 439 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 440 >> 3; //* PRIM bits */ 441 /* dawr length is stored in field MDR bits 48:53. Matches range in 442 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 443 0b111111=64DW. 444 brk->len is in bytes. 445 This aligns up to double word size, shifts and does the bias. 446 */ 447 mrd = ((brk->len + 7) >> 3) - 1; 448 dawrx |= (mrd & 0x3f) << (63 - 53); 449 450 if (ppc_md.set_dawr) 451 return ppc_md.set_dawr(dawr, dawrx); 452 mtspr(SPRN_DAWR, dawr); 453 mtspr(SPRN_DAWRX, dawrx); 454 return 0; 455 } 456 457 int set_breakpoint(struct arch_hw_breakpoint *brk) 458 { 459 __get_cpu_var(current_brk) = *brk; 460 461 if (cpu_has_feature(CPU_FTR_DAWR)) 462 return set_dawr(brk); 463 464 return set_dabr(brk); 465 } 466 467 #ifdef CONFIG_PPC64 468 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 469 #endif 470 471 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 472 struct arch_hw_breakpoint *b) 473 { 474 if (a->address != b->address) 475 return false; 476 if (a->type != b->type) 477 return false; 478 if (a->len != b->len) 479 return false; 480 return true; 481 } 482 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 483 static inline void tm_reclaim_task(struct task_struct *tsk) 484 { 485 /* We have to work out if we're switching from/to a task that's in the 486 * middle of a transaction. 487 * 488 * In switching we need to maintain a 2nd register state as 489 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 490 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 491 * (current) FPRs into oldtask->thread.transact_fpr[]. 492 * 493 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 494 */ 495 struct thread_struct *thr = &tsk->thread; 496 497 if (!thr->regs) 498 return; 499 500 if (!MSR_TM_ACTIVE(thr->regs->msr)) 501 goto out_and_saveregs; 502 503 /* Stash the original thread MSR, as giveup_fpu et al will 504 * modify it. We hold onto it to see whether the task used 505 * FP & vector regs. 506 */ 507 thr->tm_orig_msr = thr->regs->msr; 508 509 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 510 "ccr=%lx, msr=%lx, trap=%lx)\n", 511 tsk->pid, thr->regs->nip, 512 thr->regs->ccr, thr->regs->msr, 513 thr->regs->trap); 514 515 tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED); 516 517 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 518 tsk->pid); 519 520 out_and_saveregs: 521 /* Always save the regs here, even if a transaction's not active. 522 * This context-switches a thread's TM info SPRs. We do it here to 523 * be consistent with the restore path (in recheckpoint) which 524 * cannot happen later in _switch(). 525 */ 526 tm_save_sprs(thr); 527 } 528 529 static inline void tm_recheckpoint_new_task(struct task_struct *new) 530 { 531 unsigned long msr; 532 533 if (!cpu_has_feature(CPU_FTR_TM)) 534 return; 535 536 /* Recheckpoint the registers of the thread we're about to switch to. 537 * 538 * If the task was using FP, we non-lazily reload both the original and 539 * the speculative FP register states. This is because the kernel 540 * doesn't see if/when a TM rollback occurs, so if we take an FP 541 * unavoidable later, we are unable to determine which set of FP regs 542 * need to be restored. 543 */ 544 if (!new->thread.regs) 545 return; 546 547 /* The TM SPRs are restored here, so that TEXASR.FS can be set 548 * before the trecheckpoint and no explosion occurs. 549 */ 550 tm_restore_sprs(&new->thread); 551 552 if (!MSR_TM_ACTIVE(new->thread.regs->msr)) 553 return; 554 msr = new->thread.tm_orig_msr; 555 /* Recheckpoint to restore original checkpointed register state. */ 556 TM_DEBUG("*** tm_recheckpoint of pid %d " 557 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 558 new->pid, new->thread.regs->msr, msr); 559 560 /* This loads the checkpointed FP/VEC state, if used */ 561 tm_recheckpoint(&new->thread, msr); 562 563 /* This loads the speculative FP/VEC state, if used */ 564 if (msr & MSR_FP) { 565 do_load_up_transact_fpu(&new->thread); 566 new->thread.regs->msr |= 567 (MSR_FP | new->thread.fpexc_mode); 568 } 569 #ifdef CONFIG_ALTIVEC 570 if (msr & MSR_VEC) { 571 do_load_up_transact_altivec(&new->thread); 572 new->thread.regs->msr |= MSR_VEC; 573 } 574 #endif 575 /* We may as well turn on VSX too since all the state is restored now */ 576 if (msr & MSR_VSX) 577 new->thread.regs->msr |= MSR_VSX; 578 579 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 580 "(kernel msr 0x%lx)\n", 581 new->pid, mfmsr()); 582 } 583 584 static inline void __switch_to_tm(struct task_struct *prev) 585 { 586 if (cpu_has_feature(CPU_FTR_TM)) { 587 tm_enable(); 588 tm_reclaim_task(prev); 589 } 590 } 591 #else 592 #define tm_recheckpoint_new_task(new) 593 #define __switch_to_tm(prev) 594 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 595 596 struct task_struct *__switch_to(struct task_struct *prev, 597 struct task_struct *new) 598 { 599 struct thread_struct *new_thread, *old_thread; 600 struct task_struct *last; 601 #ifdef CONFIG_PPC_BOOK3S_64 602 struct ppc64_tlb_batch *batch; 603 #endif 604 605 WARN_ON(!irqs_disabled()); 606 607 /* Back up the TAR across context switches. 608 * Note that the TAR is not available for use in the kernel. (To 609 * provide this, the TAR should be backed up/restored on exception 610 * entry/exit instead, and be in pt_regs. FIXME, this should be in 611 * pt_regs anyway (for debug).) 612 * Save the TAR here before we do treclaim/trecheckpoint as these 613 * will change the TAR. 614 */ 615 save_tar(&prev->thread); 616 617 __switch_to_tm(prev); 618 619 #ifdef CONFIG_SMP 620 /* avoid complexity of lazy save/restore of fpu 621 * by just saving it every time we switch out if 622 * this task used the fpu during the last quantum. 623 * 624 * If it tries to use the fpu again, it'll trap and 625 * reload its fp regs. So we don't have to do a restore 626 * every switch, just a save. 627 * -- Cort 628 */ 629 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) 630 giveup_fpu(prev); 631 #ifdef CONFIG_ALTIVEC 632 /* 633 * If the previous thread used altivec in the last quantum 634 * (thus changing altivec regs) then save them. 635 * We used to check the VRSAVE register but not all apps 636 * set it, so we don't rely on it now (and in fact we need 637 * to save & restore VSCR even if VRSAVE == 0). -- paulus 638 * 639 * On SMP we always save/restore altivec regs just to avoid the 640 * complexity of changing processors. 641 * -- Cort 642 */ 643 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) 644 giveup_altivec(prev); 645 #endif /* CONFIG_ALTIVEC */ 646 #ifdef CONFIG_VSX 647 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) 648 /* VMX and FPU registers are already save here */ 649 __giveup_vsx(prev); 650 #endif /* CONFIG_VSX */ 651 #ifdef CONFIG_SPE 652 /* 653 * If the previous thread used spe in the last quantum 654 * (thus changing spe regs) then save them. 655 * 656 * On SMP we always save/restore spe regs just to avoid the 657 * complexity of changing processors. 658 */ 659 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) 660 giveup_spe(prev); 661 #endif /* CONFIG_SPE */ 662 663 #else /* CONFIG_SMP */ 664 #ifdef CONFIG_ALTIVEC 665 /* Avoid the trap. On smp this this never happens since 666 * we don't set last_task_used_altivec -- Cort 667 */ 668 if (new->thread.regs && last_task_used_altivec == new) 669 new->thread.regs->msr |= MSR_VEC; 670 #endif /* CONFIG_ALTIVEC */ 671 #ifdef CONFIG_VSX 672 if (new->thread.regs && last_task_used_vsx == new) 673 new->thread.regs->msr |= MSR_VSX; 674 #endif /* CONFIG_VSX */ 675 #ifdef CONFIG_SPE 676 /* Avoid the trap. On smp this this never happens since 677 * we don't set last_task_used_spe 678 */ 679 if (new->thread.regs && last_task_used_spe == new) 680 new->thread.regs->msr |= MSR_SPE; 681 #endif /* CONFIG_SPE */ 682 683 #endif /* CONFIG_SMP */ 684 685 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 686 switch_booke_debug_regs(&new->thread.debug); 687 #else 688 /* 689 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 690 * schedule DABR 691 */ 692 #ifndef CONFIG_HAVE_HW_BREAKPOINT 693 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) 694 set_breakpoint(&new->thread.hw_brk); 695 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 696 #endif 697 698 699 new_thread = &new->thread; 700 old_thread = ¤t->thread; 701 702 #ifdef CONFIG_PPC64 703 /* 704 * Collect processor utilization data per process 705 */ 706 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 707 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); 708 long unsigned start_tb, current_tb; 709 start_tb = old_thread->start_tb; 710 cu->current_tb = current_tb = mfspr(SPRN_PURR); 711 old_thread->accum_tb += (current_tb - start_tb); 712 new_thread->start_tb = current_tb; 713 } 714 #endif /* CONFIG_PPC64 */ 715 716 #ifdef CONFIG_PPC_BOOK3S_64 717 batch = &__get_cpu_var(ppc64_tlb_batch); 718 if (batch->active) { 719 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 720 if (batch->index) 721 __flush_tlb_pending(batch); 722 batch->active = 0; 723 } 724 #endif /* CONFIG_PPC_BOOK3S_64 */ 725 726 /* 727 * We can't take a PMU exception inside _switch() since there is a 728 * window where the kernel stack SLB and the kernel stack are out 729 * of sync. Hard disable here. 730 */ 731 hard_irq_disable(); 732 733 tm_recheckpoint_new_task(new); 734 735 last = _switch(old_thread, new_thread); 736 737 #ifdef CONFIG_PPC_BOOK3S_64 738 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 739 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 740 batch = &__get_cpu_var(ppc64_tlb_batch); 741 batch->active = 1; 742 } 743 #endif /* CONFIG_PPC_BOOK3S_64 */ 744 745 return last; 746 } 747 748 static int instructions_to_print = 16; 749 750 static void show_instructions(struct pt_regs *regs) 751 { 752 int i; 753 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 754 sizeof(int)); 755 756 printk("Instruction dump:"); 757 758 for (i = 0; i < instructions_to_print; i++) { 759 int instr; 760 761 if (!(i % 8)) 762 printk("\n"); 763 764 #if !defined(CONFIG_BOOKE) 765 /* If executing with the IMMU off, adjust pc rather 766 * than print XXXXXXXX. 767 */ 768 if (!(regs->msr & MSR_IR)) 769 pc = (unsigned long)phys_to_virt(pc); 770 #endif 771 772 /* We use __get_user here *only* to avoid an OOPS on a 773 * bad address because the pc *should* only be a 774 * kernel address. 775 */ 776 if (!__kernel_text_address(pc) || 777 __get_user(instr, (unsigned int __user *)pc)) { 778 printk(KERN_CONT "XXXXXXXX "); 779 } else { 780 if (regs->nip == pc) 781 printk(KERN_CONT "<%08x> ", instr); 782 else 783 printk(KERN_CONT "%08x ", instr); 784 } 785 786 pc += sizeof(int); 787 } 788 789 printk("\n"); 790 } 791 792 static struct regbit { 793 unsigned long bit; 794 const char *name; 795 } msr_bits[] = { 796 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 797 {MSR_SF, "SF"}, 798 {MSR_HV, "HV"}, 799 #endif 800 {MSR_VEC, "VEC"}, 801 {MSR_VSX, "VSX"}, 802 #ifdef CONFIG_BOOKE 803 {MSR_CE, "CE"}, 804 #endif 805 {MSR_EE, "EE"}, 806 {MSR_PR, "PR"}, 807 {MSR_FP, "FP"}, 808 {MSR_ME, "ME"}, 809 #ifdef CONFIG_BOOKE 810 {MSR_DE, "DE"}, 811 #else 812 {MSR_SE, "SE"}, 813 {MSR_BE, "BE"}, 814 #endif 815 {MSR_IR, "IR"}, 816 {MSR_DR, "DR"}, 817 {MSR_PMM, "PMM"}, 818 #ifndef CONFIG_BOOKE 819 {MSR_RI, "RI"}, 820 {MSR_LE, "LE"}, 821 #endif 822 {0, NULL} 823 }; 824 825 static void printbits(unsigned long val, struct regbit *bits) 826 { 827 const char *sep = ""; 828 829 printk("<"); 830 for (; bits->bit; ++bits) 831 if (val & bits->bit) { 832 printk("%s%s", sep, bits->name); 833 sep = ","; 834 } 835 printk(">"); 836 } 837 838 #ifdef CONFIG_PPC64 839 #define REG "%016lx" 840 #define REGS_PER_LINE 4 841 #define LAST_VOLATILE 13 842 #else 843 #define REG "%08lx" 844 #define REGS_PER_LINE 8 845 #define LAST_VOLATILE 12 846 #endif 847 848 void show_regs(struct pt_regs * regs) 849 { 850 int i, trap; 851 852 show_regs_print_info(KERN_DEFAULT); 853 854 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 855 regs->nip, regs->link, regs->ctr); 856 printk("REGS: %p TRAP: %04lx %s (%s)\n", 857 regs, regs->trap, print_tainted(), init_utsname()->release); 858 printk("MSR: "REG" ", regs->msr); 859 printbits(regs->msr, msr_bits); 860 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 861 trap = TRAP(regs); 862 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 863 printk("CFAR: "REG" ", regs->orig_gpr3); 864 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 865 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 866 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 867 #else 868 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 869 #endif 870 #ifdef CONFIG_PPC64 871 printk("SOFTE: %ld ", regs->softe); 872 #endif 873 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 874 if (MSR_TM_ACTIVE(regs->msr)) 875 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 876 #endif 877 878 for (i = 0; i < 32; i++) { 879 if ((i % REGS_PER_LINE) == 0) 880 printk("\nGPR%02d: ", i); 881 printk(REG " ", regs->gpr[i]); 882 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 883 break; 884 } 885 printk("\n"); 886 #ifdef CONFIG_KALLSYMS 887 /* 888 * Lookup NIP late so we have the best change of getting the 889 * above info out without failing 890 */ 891 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 892 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 893 #endif 894 show_stack(current, (unsigned long *) regs->gpr[1]); 895 if (!user_mode(regs)) 896 show_instructions(regs); 897 } 898 899 void exit_thread(void) 900 { 901 discard_lazy_cpu_state(); 902 } 903 904 void flush_thread(void) 905 { 906 discard_lazy_cpu_state(); 907 908 #ifdef CONFIG_HAVE_HW_BREAKPOINT 909 flush_ptrace_hw_breakpoint(current); 910 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 911 set_debug_reg_defaults(¤t->thread); 912 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 913 } 914 915 void 916 release_thread(struct task_struct *t) 917 { 918 } 919 920 /* 921 * this gets called so that we can store coprocessor state into memory and 922 * copy the current task into the new thread. 923 */ 924 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 925 { 926 flush_fp_to_thread(src); 927 flush_altivec_to_thread(src); 928 flush_vsx_to_thread(src); 929 flush_spe_to_thread(src); 930 931 *dst = *src; 932 933 clear_task_ebb(dst); 934 935 return 0; 936 } 937 938 /* 939 * Copy a thread.. 940 */ 941 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */ 942 943 int copy_thread(unsigned long clone_flags, unsigned long usp, 944 unsigned long arg, struct task_struct *p) 945 { 946 struct pt_regs *childregs, *kregs; 947 extern void ret_from_fork(void); 948 extern void ret_from_kernel_thread(void); 949 void (*f)(void); 950 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 951 952 /* Copy registers */ 953 sp -= sizeof(struct pt_regs); 954 childregs = (struct pt_regs *) sp; 955 if (unlikely(p->flags & PF_KTHREAD)) { 956 struct thread_info *ti = (void *)task_stack_page(p); 957 memset(childregs, 0, sizeof(struct pt_regs)); 958 childregs->gpr[1] = sp + sizeof(struct pt_regs); 959 childregs->gpr[14] = usp; /* function */ 960 #ifdef CONFIG_PPC64 961 clear_tsk_thread_flag(p, TIF_32BIT); 962 childregs->softe = 1; 963 #endif 964 childregs->gpr[15] = arg; 965 p->thread.regs = NULL; /* no user register state */ 966 ti->flags |= _TIF_RESTOREALL; 967 f = ret_from_kernel_thread; 968 } else { 969 struct pt_regs *regs = current_pt_regs(); 970 CHECK_FULL_REGS(regs); 971 *childregs = *regs; 972 if (usp) 973 childregs->gpr[1] = usp; 974 p->thread.regs = childregs; 975 childregs->gpr[3] = 0; /* Result from fork() */ 976 if (clone_flags & CLONE_SETTLS) { 977 #ifdef CONFIG_PPC64 978 if (!is_32bit_task()) 979 childregs->gpr[13] = childregs->gpr[6]; 980 else 981 #endif 982 childregs->gpr[2] = childregs->gpr[6]; 983 } 984 985 f = ret_from_fork; 986 } 987 sp -= STACK_FRAME_OVERHEAD; 988 989 /* 990 * The way this works is that at some point in the future 991 * some task will call _switch to switch to the new task. 992 * That will pop off the stack frame created below and start 993 * the new task running at ret_from_fork. The new task will 994 * do some house keeping and then return from the fork or clone 995 * system call, using the stack frame created above. 996 */ 997 ((unsigned long *)sp)[0] = 0; 998 sp -= sizeof(struct pt_regs); 999 kregs = (struct pt_regs *) sp; 1000 sp -= STACK_FRAME_OVERHEAD; 1001 p->thread.ksp = sp; 1002 #ifdef CONFIG_PPC32 1003 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1004 _ALIGN_UP(sizeof(struct thread_info), 16); 1005 #endif 1006 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1007 p->thread.ptrace_bps[0] = NULL; 1008 #endif 1009 1010 p->thread.fp_save_area = NULL; 1011 #ifdef CONFIG_ALTIVEC 1012 p->thread.vr_save_area = NULL; 1013 #endif 1014 1015 #ifdef CONFIG_PPC_STD_MMU_64 1016 if (mmu_has_feature(MMU_FTR_SLB)) { 1017 unsigned long sp_vsid; 1018 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1019 1020 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1021 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1022 << SLB_VSID_SHIFT_1T; 1023 else 1024 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1025 << SLB_VSID_SHIFT; 1026 sp_vsid |= SLB_VSID_KERNEL | llp; 1027 p->thread.ksp_vsid = sp_vsid; 1028 } 1029 #endif /* CONFIG_PPC_STD_MMU_64 */ 1030 #ifdef CONFIG_PPC64 1031 if (cpu_has_feature(CPU_FTR_DSCR)) { 1032 p->thread.dscr_inherit = current->thread.dscr_inherit; 1033 p->thread.dscr = current->thread.dscr; 1034 } 1035 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1036 p->thread.ppr = INIT_PPR; 1037 #endif 1038 /* 1039 * The PPC64 ABI makes use of a TOC to contain function 1040 * pointers. The function (ret_from_except) is actually a pointer 1041 * to the TOC entry. The first entry is a pointer to the actual 1042 * function. 1043 */ 1044 #ifdef CONFIG_PPC64 1045 kregs->nip = *((unsigned long *)f); 1046 #else 1047 kregs->nip = (unsigned long)f; 1048 #endif 1049 return 0; 1050 } 1051 1052 /* 1053 * Set up a thread for executing a new program 1054 */ 1055 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1056 { 1057 #ifdef CONFIG_PPC64 1058 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1059 #endif 1060 1061 /* 1062 * If we exec out of a kernel thread then thread.regs will not be 1063 * set. Do it now. 1064 */ 1065 if (!current->thread.regs) { 1066 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1067 current->thread.regs = regs - 1; 1068 } 1069 1070 memset(regs->gpr, 0, sizeof(regs->gpr)); 1071 regs->ctr = 0; 1072 regs->link = 0; 1073 regs->xer = 0; 1074 regs->ccr = 0; 1075 regs->gpr[1] = sp; 1076 1077 /* 1078 * We have just cleared all the nonvolatile GPRs, so make 1079 * FULL_REGS(regs) return true. This is necessary to allow 1080 * ptrace to examine the thread immediately after exec. 1081 */ 1082 regs->trap &= ~1UL; 1083 1084 #ifdef CONFIG_PPC32 1085 regs->mq = 0; 1086 regs->nip = start; 1087 regs->msr = MSR_USER; 1088 #else 1089 if (!is_32bit_task()) { 1090 unsigned long entry; 1091 1092 if (is_elf2_task()) { 1093 /* Look ma, no function descriptors! */ 1094 entry = start; 1095 1096 /* 1097 * Ulrich says: 1098 * The latest iteration of the ABI requires that when 1099 * calling a function (at its global entry point), 1100 * the caller must ensure r12 holds the entry point 1101 * address (so that the function can quickly 1102 * establish addressability). 1103 */ 1104 regs->gpr[12] = start; 1105 /* Make sure that's restored on entry to userspace. */ 1106 set_thread_flag(TIF_RESTOREALL); 1107 } else { 1108 unsigned long toc; 1109 1110 /* start is a relocated pointer to the function 1111 * descriptor for the elf _start routine. The first 1112 * entry in the function descriptor is the entry 1113 * address of _start and the second entry is the TOC 1114 * value we need to use. 1115 */ 1116 __get_user(entry, (unsigned long __user *)start); 1117 __get_user(toc, (unsigned long __user *)start+1); 1118 1119 /* Check whether the e_entry function descriptor entries 1120 * need to be relocated before we can use them. 1121 */ 1122 if (load_addr != 0) { 1123 entry += load_addr; 1124 toc += load_addr; 1125 } 1126 regs->gpr[2] = toc; 1127 } 1128 regs->nip = entry; 1129 regs->msr = MSR_USER64; 1130 } else { 1131 regs->nip = start; 1132 regs->gpr[2] = 0; 1133 regs->msr = MSR_USER32; 1134 } 1135 #endif 1136 discard_lazy_cpu_state(); 1137 #ifdef CONFIG_VSX 1138 current->thread.used_vsr = 0; 1139 #endif 1140 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1141 current->thread.fp_save_area = NULL; 1142 #ifdef CONFIG_ALTIVEC 1143 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1144 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1145 current->thread.vr_save_area = NULL; 1146 current->thread.vrsave = 0; 1147 current->thread.used_vr = 0; 1148 #endif /* CONFIG_ALTIVEC */ 1149 #ifdef CONFIG_SPE 1150 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1151 current->thread.acc = 0; 1152 current->thread.spefscr = 0; 1153 current->thread.used_spe = 0; 1154 #endif /* CONFIG_SPE */ 1155 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1156 if (cpu_has_feature(CPU_FTR_TM)) 1157 regs->msr |= MSR_TM; 1158 current->thread.tm_tfhar = 0; 1159 current->thread.tm_texasr = 0; 1160 current->thread.tm_tfiar = 0; 1161 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1162 } 1163 1164 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1165 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1166 1167 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1168 { 1169 struct pt_regs *regs = tsk->thread.regs; 1170 1171 /* This is a bit hairy. If we are an SPE enabled processor 1172 * (have embedded fp) we store the IEEE exception enable flags in 1173 * fpexc_mode. fpexc_mode is also used for setting FP exception 1174 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1175 if (val & PR_FP_EXC_SW_ENABLE) { 1176 #ifdef CONFIG_SPE 1177 if (cpu_has_feature(CPU_FTR_SPE)) { 1178 tsk->thread.fpexc_mode = val & 1179 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1180 return 0; 1181 } else { 1182 return -EINVAL; 1183 } 1184 #else 1185 return -EINVAL; 1186 #endif 1187 } 1188 1189 /* on a CONFIG_SPE this does not hurt us. The bits that 1190 * __pack_fe01 use do not overlap with bits used for 1191 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1192 * on CONFIG_SPE implementations are reserved so writing to 1193 * them does not change anything */ 1194 if (val > PR_FP_EXC_PRECISE) 1195 return -EINVAL; 1196 tsk->thread.fpexc_mode = __pack_fe01(val); 1197 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1198 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1199 | tsk->thread.fpexc_mode; 1200 return 0; 1201 } 1202 1203 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1204 { 1205 unsigned int val; 1206 1207 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1208 #ifdef CONFIG_SPE 1209 if (cpu_has_feature(CPU_FTR_SPE)) 1210 val = tsk->thread.fpexc_mode; 1211 else 1212 return -EINVAL; 1213 #else 1214 return -EINVAL; 1215 #endif 1216 else 1217 val = __unpack_fe01(tsk->thread.fpexc_mode); 1218 return put_user(val, (unsigned int __user *) adr); 1219 } 1220 1221 int set_endian(struct task_struct *tsk, unsigned int val) 1222 { 1223 struct pt_regs *regs = tsk->thread.regs; 1224 1225 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1226 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1227 return -EINVAL; 1228 1229 if (regs == NULL) 1230 return -EINVAL; 1231 1232 if (val == PR_ENDIAN_BIG) 1233 regs->msr &= ~MSR_LE; 1234 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1235 regs->msr |= MSR_LE; 1236 else 1237 return -EINVAL; 1238 1239 return 0; 1240 } 1241 1242 int get_endian(struct task_struct *tsk, unsigned long adr) 1243 { 1244 struct pt_regs *regs = tsk->thread.regs; 1245 unsigned int val; 1246 1247 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1248 !cpu_has_feature(CPU_FTR_REAL_LE)) 1249 return -EINVAL; 1250 1251 if (regs == NULL) 1252 return -EINVAL; 1253 1254 if (regs->msr & MSR_LE) { 1255 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1256 val = PR_ENDIAN_LITTLE; 1257 else 1258 val = PR_ENDIAN_PPC_LITTLE; 1259 } else 1260 val = PR_ENDIAN_BIG; 1261 1262 return put_user(val, (unsigned int __user *)adr); 1263 } 1264 1265 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1266 { 1267 tsk->thread.align_ctl = val; 1268 return 0; 1269 } 1270 1271 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1272 { 1273 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1274 } 1275 1276 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1277 unsigned long nbytes) 1278 { 1279 unsigned long stack_page; 1280 unsigned long cpu = task_cpu(p); 1281 1282 /* 1283 * Avoid crashing if the stack has overflowed and corrupted 1284 * task_cpu(p), which is in the thread_info struct. 1285 */ 1286 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1287 stack_page = (unsigned long) hardirq_ctx[cpu]; 1288 if (sp >= stack_page + sizeof(struct thread_struct) 1289 && sp <= stack_page + THREAD_SIZE - nbytes) 1290 return 1; 1291 1292 stack_page = (unsigned long) softirq_ctx[cpu]; 1293 if (sp >= stack_page + sizeof(struct thread_struct) 1294 && sp <= stack_page + THREAD_SIZE - nbytes) 1295 return 1; 1296 } 1297 return 0; 1298 } 1299 1300 int validate_sp(unsigned long sp, struct task_struct *p, 1301 unsigned long nbytes) 1302 { 1303 unsigned long stack_page = (unsigned long)task_stack_page(p); 1304 1305 if (sp >= stack_page + sizeof(struct thread_struct) 1306 && sp <= stack_page + THREAD_SIZE - nbytes) 1307 return 1; 1308 1309 return valid_irq_stack(sp, p, nbytes); 1310 } 1311 1312 EXPORT_SYMBOL(validate_sp); 1313 1314 unsigned long get_wchan(struct task_struct *p) 1315 { 1316 unsigned long ip, sp; 1317 int count = 0; 1318 1319 if (!p || p == current || p->state == TASK_RUNNING) 1320 return 0; 1321 1322 sp = p->thread.ksp; 1323 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1324 return 0; 1325 1326 do { 1327 sp = *(unsigned long *)sp; 1328 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1329 return 0; 1330 if (count > 0) { 1331 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1332 if (!in_sched_functions(ip)) 1333 return ip; 1334 } 1335 } while (count++ < 16); 1336 return 0; 1337 } 1338 1339 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1340 1341 void show_stack(struct task_struct *tsk, unsigned long *stack) 1342 { 1343 unsigned long sp, ip, lr, newsp; 1344 int count = 0; 1345 int firstframe = 1; 1346 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1347 int curr_frame = current->curr_ret_stack; 1348 extern void return_to_handler(void); 1349 unsigned long rth = (unsigned long)return_to_handler; 1350 unsigned long mrth = -1; 1351 #ifdef CONFIG_PPC64 1352 extern void mod_return_to_handler(void); 1353 rth = *(unsigned long *)rth; 1354 mrth = (unsigned long)mod_return_to_handler; 1355 mrth = *(unsigned long *)mrth; 1356 #endif 1357 #endif 1358 1359 sp = (unsigned long) stack; 1360 if (tsk == NULL) 1361 tsk = current; 1362 if (sp == 0) { 1363 if (tsk == current) 1364 asm("mr %0,1" : "=r" (sp)); 1365 else 1366 sp = tsk->thread.ksp; 1367 } 1368 1369 lr = 0; 1370 printk("Call Trace:\n"); 1371 do { 1372 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1373 return; 1374 1375 stack = (unsigned long *) sp; 1376 newsp = stack[0]; 1377 ip = stack[STACK_FRAME_LR_SAVE]; 1378 if (!firstframe || ip != lr) { 1379 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1380 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1381 if ((ip == rth || ip == mrth) && curr_frame >= 0) { 1382 printk(" (%pS)", 1383 (void *)current->ret_stack[curr_frame].ret); 1384 curr_frame--; 1385 } 1386 #endif 1387 if (firstframe) 1388 printk(" (unreliable)"); 1389 printk("\n"); 1390 } 1391 firstframe = 0; 1392 1393 /* 1394 * See if this is an exception frame. 1395 * We look for the "regshere" marker in the current frame. 1396 */ 1397 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1398 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1399 struct pt_regs *regs = (struct pt_regs *) 1400 (sp + STACK_FRAME_OVERHEAD); 1401 lr = regs->link; 1402 printk("--- Exception: %lx at %pS\n LR = %pS\n", 1403 regs->trap, (void *)regs->nip, (void *)lr); 1404 firstframe = 1; 1405 } 1406 1407 sp = newsp; 1408 } while (count++ < kstack_depth_to_print); 1409 } 1410 1411 #ifdef CONFIG_PPC64 1412 /* Called with hard IRQs off */ 1413 void notrace __ppc64_runlatch_on(void) 1414 { 1415 struct thread_info *ti = current_thread_info(); 1416 unsigned long ctrl; 1417 1418 ctrl = mfspr(SPRN_CTRLF); 1419 ctrl |= CTRL_RUNLATCH; 1420 mtspr(SPRN_CTRLT, ctrl); 1421 1422 ti->local_flags |= _TLF_RUNLATCH; 1423 } 1424 1425 /* Called with hard IRQs off */ 1426 void notrace __ppc64_runlatch_off(void) 1427 { 1428 struct thread_info *ti = current_thread_info(); 1429 unsigned long ctrl; 1430 1431 ti->local_flags &= ~_TLF_RUNLATCH; 1432 1433 ctrl = mfspr(SPRN_CTRLF); 1434 ctrl &= ~CTRL_RUNLATCH; 1435 mtspr(SPRN_CTRLT, ctrl); 1436 } 1437 #endif /* CONFIG_PPC64 */ 1438 1439 unsigned long arch_align_stack(unsigned long sp) 1440 { 1441 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1442 sp -= get_random_int() & ~PAGE_MASK; 1443 return sp & ~0xf; 1444 } 1445 1446 static inline unsigned long brk_rnd(void) 1447 { 1448 unsigned long rnd = 0; 1449 1450 /* 8MB for 32bit, 1GB for 64bit */ 1451 if (is_32bit_task()) 1452 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); 1453 else 1454 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); 1455 1456 return rnd << PAGE_SHIFT; 1457 } 1458 1459 unsigned long arch_randomize_brk(struct mm_struct *mm) 1460 { 1461 unsigned long base = mm->brk; 1462 unsigned long ret; 1463 1464 #ifdef CONFIG_PPC_STD_MMU_64 1465 /* 1466 * If we are using 1TB segments and we are allowed to randomise 1467 * the heap, we can put it above 1TB so it is backed by a 1TB 1468 * segment. Otherwise the heap will be in the bottom 1TB 1469 * which always uses 256MB segments and this may result in a 1470 * performance penalty. 1471 */ 1472 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1473 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1474 #endif 1475 1476 ret = PAGE_ALIGN(base + brk_rnd()); 1477 1478 if (ret < mm->brk) 1479 return mm->brk; 1480 1481 return ret; 1482 } 1483 1484 unsigned long randomize_et_dyn(unsigned long base) 1485 { 1486 unsigned long ret = PAGE_ALIGN(base + brk_rnd()); 1487 1488 if (ret < base) 1489 return base; 1490 1491 return ret; 1492 } 1493