1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/prctl.h> 29 #include <linux/init_task.h> 30 #include <linux/export.h> 31 #include <linux/kallsyms.h> 32 #include <linux/mqueue.h> 33 #include <linux/hardirq.h> 34 #include <linux/utsname.h> 35 #include <linux/ftrace.h> 36 #include <linux/kernel_stat.h> 37 #include <linux/personality.h> 38 #include <linux/random.h> 39 #include <linux/hw_breakpoint.h> 40 41 #include <asm/pgtable.h> 42 #include <asm/uaccess.h> 43 #include <asm/io.h> 44 #include <asm/processor.h> 45 #include <asm/mmu.h> 46 #include <asm/prom.h> 47 #include <asm/machdep.h> 48 #include <asm/time.h> 49 #include <asm/runlatch.h> 50 #include <asm/syscalls.h> 51 #include <asm/switch_to.h> 52 #include <asm/tm.h> 53 #include <asm/debug.h> 54 #ifdef CONFIG_PPC64 55 #include <asm/firmware.h> 56 #endif 57 #include <linux/kprobes.h> 58 #include <linux/kdebug.h> 59 60 /* Transactional Memory debug */ 61 #ifdef TM_DEBUG_SW 62 #define TM_DEBUG(x...) printk(KERN_INFO x) 63 #else 64 #define TM_DEBUG(x...) do { } while(0) 65 #endif 66 67 extern unsigned long _get_SP(void); 68 69 #ifndef CONFIG_SMP 70 struct task_struct *last_task_used_math = NULL; 71 struct task_struct *last_task_used_altivec = NULL; 72 struct task_struct *last_task_used_vsx = NULL; 73 struct task_struct *last_task_used_spe = NULL; 74 #endif 75 76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 77 void giveup_fpu_maybe_transactional(struct task_struct *tsk) 78 { 79 /* 80 * If we are saving the current thread's registers, and the 81 * thread is in a transactional state, set the TIF_RESTORE_TM 82 * bit so that we know to restore the registers before 83 * returning to userspace. 84 */ 85 if (tsk == current && tsk->thread.regs && 86 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 87 !test_thread_flag(TIF_RESTORE_TM)) { 88 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; 89 set_thread_flag(TIF_RESTORE_TM); 90 } 91 92 giveup_fpu(tsk); 93 } 94 95 void giveup_altivec_maybe_transactional(struct task_struct *tsk) 96 { 97 /* 98 * If we are saving the current thread's registers, and the 99 * thread is in a transactional state, set the TIF_RESTORE_TM 100 * bit so that we know to restore the registers before 101 * returning to userspace. 102 */ 103 if (tsk == current && tsk->thread.regs && 104 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 105 !test_thread_flag(TIF_RESTORE_TM)) { 106 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; 107 set_thread_flag(TIF_RESTORE_TM); 108 } 109 110 giveup_altivec(tsk); 111 } 112 113 #else 114 #define giveup_fpu_maybe_transactional(tsk) giveup_fpu(tsk) 115 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk) 116 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 117 118 #ifdef CONFIG_PPC_FPU 119 /* 120 * Make sure the floating-point register state in the 121 * the thread_struct is up to date for task tsk. 122 */ 123 void flush_fp_to_thread(struct task_struct *tsk) 124 { 125 if (tsk->thread.regs) { 126 /* 127 * We need to disable preemption here because if we didn't, 128 * another process could get scheduled after the regs->msr 129 * test but before we have finished saving the FP registers 130 * to the thread_struct. That process could take over the 131 * FPU, and then when we get scheduled again we would store 132 * bogus values for the remaining FP registers. 133 */ 134 preempt_disable(); 135 if (tsk->thread.regs->msr & MSR_FP) { 136 #ifdef CONFIG_SMP 137 /* 138 * This should only ever be called for current or 139 * for a stopped child process. Since we save away 140 * the FP register state on context switch on SMP, 141 * there is something wrong if a stopped child appears 142 * to still have its FP state in the CPU registers. 143 */ 144 BUG_ON(tsk != current); 145 #endif 146 giveup_fpu_maybe_transactional(tsk); 147 } 148 preempt_enable(); 149 } 150 } 151 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 152 #endif /* CONFIG_PPC_FPU */ 153 154 void enable_kernel_fp(void) 155 { 156 WARN_ON(preemptible()); 157 158 #ifdef CONFIG_SMP 159 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) 160 giveup_fpu_maybe_transactional(current); 161 else 162 giveup_fpu(NULL); /* just enables FP for kernel */ 163 #else 164 giveup_fpu_maybe_transactional(last_task_used_math); 165 #endif /* CONFIG_SMP */ 166 } 167 EXPORT_SYMBOL(enable_kernel_fp); 168 169 #ifdef CONFIG_ALTIVEC 170 void enable_kernel_altivec(void) 171 { 172 WARN_ON(preemptible()); 173 174 #ifdef CONFIG_SMP 175 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) 176 giveup_altivec_maybe_transactional(current); 177 else 178 giveup_altivec_notask(); 179 #else 180 giveup_altivec_maybe_transactional(last_task_used_altivec); 181 #endif /* CONFIG_SMP */ 182 } 183 EXPORT_SYMBOL(enable_kernel_altivec); 184 185 /* 186 * Make sure the VMX/Altivec register state in the 187 * the thread_struct is up to date for task tsk. 188 */ 189 void flush_altivec_to_thread(struct task_struct *tsk) 190 { 191 if (tsk->thread.regs) { 192 preempt_disable(); 193 if (tsk->thread.regs->msr & MSR_VEC) { 194 #ifdef CONFIG_SMP 195 BUG_ON(tsk != current); 196 #endif 197 giveup_altivec_maybe_transactional(tsk); 198 } 199 preempt_enable(); 200 } 201 } 202 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 203 #endif /* CONFIG_ALTIVEC */ 204 205 #ifdef CONFIG_VSX 206 #if 0 207 /* not currently used, but some crazy RAID module might want to later */ 208 void enable_kernel_vsx(void) 209 { 210 WARN_ON(preemptible()); 211 212 #ifdef CONFIG_SMP 213 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) 214 giveup_vsx(current); 215 else 216 giveup_vsx(NULL); /* just enable vsx for kernel - force */ 217 #else 218 giveup_vsx(last_task_used_vsx); 219 #endif /* CONFIG_SMP */ 220 } 221 EXPORT_SYMBOL(enable_kernel_vsx); 222 #endif 223 224 void giveup_vsx(struct task_struct *tsk) 225 { 226 giveup_fpu_maybe_transactional(tsk); 227 giveup_altivec_maybe_transactional(tsk); 228 __giveup_vsx(tsk); 229 } 230 231 void flush_vsx_to_thread(struct task_struct *tsk) 232 { 233 if (tsk->thread.regs) { 234 preempt_disable(); 235 if (tsk->thread.regs->msr & MSR_VSX) { 236 #ifdef CONFIG_SMP 237 BUG_ON(tsk != current); 238 #endif 239 giveup_vsx(tsk); 240 } 241 preempt_enable(); 242 } 243 } 244 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 245 #endif /* CONFIG_VSX */ 246 247 #ifdef CONFIG_SPE 248 249 void enable_kernel_spe(void) 250 { 251 WARN_ON(preemptible()); 252 253 #ifdef CONFIG_SMP 254 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) 255 giveup_spe(current); 256 else 257 giveup_spe(NULL); /* just enable SPE for kernel - force */ 258 #else 259 giveup_spe(last_task_used_spe); 260 #endif /* __SMP __ */ 261 } 262 EXPORT_SYMBOL(enable_kernel_spe); 263 264 void flush_spe_to_thread(struct task_struct *tsk) 265 { 266 if (tsk->thread.regs) { 267 preempt_disable(); 268 if (tsk->thread.regs->msr & MSR_SPE) { 269 #ifdef CONFIG_SMP 270 BUG_ON(tsk != current); 271 #endif 272 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 273 giveup_spe(tsk); 274 } 275 preempt_enable(); 276 } 277 } 278 #endif /* CONFIG_SPE */ 279 280 #ifndef CONFIG_SMP 281 /* 282 * If we are doing lazy switching of CPU state (FP, altivec or SPE), 283 * and the current task has some state, discard it. 284 */ 285 void discard_lazy_cpu_state(void) 286 { 287 preempt_disable(); 288 if (last_task_used_math == current) 289 last_task_used_math = NULL; 290 #ifdef CONFIG_ALTIVEC 291 if (last_task_used_altivec == current) 292 last_task_used_altivec = NULL; 293 #endif /* CONFIG_ALTIVEC */ 294 #ifdef CONFIG_VSX 295 if (last_task_used_vsx == current) 296 last_task_used_vsx = NULL; 297 #endif /* CONFIG_VSX */ 298 #ifdef CONFIG_SPE 299 if (last_task_used_spe == current) 300 last_task_used_spe = NULL; 301 #endif 302 preempt_enable(); 303 } 304 #endif /* CONFIG_SMP */ 305 306 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 307 void do_send_trap(struct pt_regs *regs, unsigned long address, 308 unsigned long error_code, int signal_code, int breakpt) 309 { 310 siginfo_t info; 311 312 current->thread.trap_nr = signal_code; 313 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 314 11, SIGSEGV) == NOTIFY_STOP) 315 return; 316 317 /* Deliver the signal to userspace */ 318 info.si_signo = SIGTRAP; 319 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 320 info.si_code = signal_code; 321 info.si_addr = (void __user *)address; 322 force_sig_info(SIGTRAP, &info, current); 323 } 324 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 325 void do_break (struct pt_regs *regs, unsigned long address, 326 unsigned long error_code) 327 { 328 siginfo_t info; 329 330 current->thread.trap_nr = TRAP_HWBKPT; 331 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 332 11, SIGSEGV) == NOTIFY_STOP) 333 return; 334 335 if (debugger_break_match(regs)) 336 return; 337 338 /* Clear the breakpoint */ 339 hw_breakpoint_disable(); 340 341 /* Deliver the signal to userspace */ 342 info.si_signo = SIGTRAP; 343 info.si_errno = 0; 344 info.si_code = TRAP_HWBKPT; 345 info.si_addr = (void __user *)address; 346 force_sig_info(SIGTRAP, &info, current); 347 } 348 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 349 350 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 351 352 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 353 /* 354 * Set the debug registers back to their default "safe" values. 355 */ 356 static void set_debug_reg_defaults(struct thread_struct *thread) 357 { 358 thread->debug.iac1 = thread->debug.iac2 = 0; 359 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 360 thread->debug.iac3 = thread->debug.iac4 = 0; 361 #endif 362 thread->debug.dac1 = thread->debug.dac2 = 0; 363 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 364 thread->debug.dvc1 = thread->debug.dvc2 = 0; 365 #endif 366 thread->debug.dbcr0 = 0; 367 #ifdef CONFIG_BOOKE 368 /* 369 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 370 */ 371 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 372 DBCR1_IAC3US | DBCR1_IAC4US; 373 /* 374 * Force Data Address Compare User/Supervisor bits to be User-only 375 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 376 */ 377 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 378 #else 379 thread->debug.dbcr1 = 0; 380 #endif 381 } 382 383 static void prime_debug_regs(struct debug_reg *debug) 384 { 385 /* 386 * We could have inherited MSR_DE from userspace, since 387 * it doesn't get cleared on exception entry. Make sure 388 * MSR_DE is clear before we enable any debug events. 389 */ 390 mtmsr(mfmsr() & ~MSR_DE); 391 392 mtspr(SPRN_IAC1, debug->iac1); 393 mtspr(SPRN_IAC2, debug->iac2); 394 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 395 mtspr(SPRN_IAC3, debug->iac3); 396 mtspr(SPRN_IAC4, debug->iac4); 397 #endif 398 mtspr(SPRN_DAC1, debug->dac1); 399 mtspr(SPRN_DAC2, debug->dac2); 400 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 401 mtspr(SPRN_DVC1, debug->dvc1); 402 mtspr(SPRN_DVC2, debug->dvc2); 403 #endif 404 mtspr(SPRN_DBCR0, debug->dbcr0); 405 mtspr(SPRN_DBCR1, debug->dbcr1); 406 #ifdef CONFIG_BOOKE 407 mtspr(SPRN_DBCR2, debug->dbcr2); 408 #endif 409 } 410 /* 411 * Unless neither the old or new thread are making use of the 412 * debug registers, set the debug registers from the values 413 * stored in the new thread. 414 */ 415 void switch_booke_debug_regs(struct debug_reg *new_debug) 416 { 417 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 418 || (new_debug->dbcr0 & DBCR0_IDM)) 419 prime_debug_regs(new_debug); 420 } 421 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 422 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 423 #ifndef CONFIG_HAVE_HW_BREAKPOINT 424 static void set_debug_reg_defaults(struct thread_struct *thread) 425 { 426 thread->hw_brk.address = 0; 427 thread->hw_brk.type = 0; 428 set_breakpoint(&thread->hw_brk); 429 } 430 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 431 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 432 433 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 434 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 435 { 436 mtspr(SPRN_DAC1, dabr); 437 #ifdef CONFIG_PPC_47x 438 isync(); 439 #endif 440 return 0; 441 } 442 #elif defined(CONFIG_PPC_BOOK3S) 443 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 444 { 445 mtspr(SPRN_DABR, dabr); 446 if (cpu_has_feature(CPU_FTR_DABRX)) 447 mtspr(SPRN_DABRX, dabrx); 448 return 0; 449 } 450 #else 451 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 452 { 453 return -EINVAL; 454 } 455 #endif 456 457 static inline int set_dabr(struct arch_hw_breakpoint *brk) 458 { 459 unsigned long dabr, dabrx; 460 461 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 462 dabrx = ((brk->type >> 3) & 0x7); 463 464 if (ppc_md.set_dabr) 465 return ppc_md.set_dabr(dabr, dabrx); 466 467 return __set_dabr(dabr, dabrx); 468 } 469 470 static inline int set_dawr(struct arch_hw_breakpoint *brk) 471 { 472 unsigned long dawr, dawrx, mrd; 473 474 dawr = brk->address; 475 476 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 477 << (63 - 58); //* read/write bits */ 478 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 479 << (63 - 59); //* translate */ 480 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 481 >> 3; //* PRIM bits */ 482 /* dawr length is stored in field MDR bits 48:53. Matches range in 483 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 484 0b111111=64DW. 485 brk->len is in bytes. 486 This aligns up to double word size, shifts and does the bias. 487 */ 488 mrd = ((brk->len + 7) >> 3) - 1; 489 dawrx |= (mrd & 0x3f) << (63 - 53); 490 491 if (ppc_md.set_dawr) 492 return ppc_md.set_dawr(dawr, dawrx); 493 mtspr(SPRN_DAWR, dawr); 494 mtspr(SPRN_DAWRX, dawrx); 495 return 0; 496 } 497 498 int set_breakpoint(struct arch_hw_breakpoint *brk) 499 { 500 __get_cpu_var(current_brk) = *brk; 501 502 if (cpu_has_feature(CPU_FTR_DAWR)) 503 return set_dawr(brk); 504 505 return set_dabr(brk); 506 } 507 508 #ifdef CONFIG_PPC64 509 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 510 #endif 511 512 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 513 struct arch_hw_breakpoint *b) 514 { 515 if (a->address != b->address) 516 return false; 517 if (a->type != b->type) 518 return false; 519 if (a->len != b->len) 520 return false; 521 return true; 522 } 523 524 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 525 static void tm_reclaim_thread(struct thread_struct *thr, 526 struct thread_info *ti, uint8_t cause) 527 { 528 unsigned long msr_diff = 0; 529 530 /* 531 * If FP/VSX registers have been already saved to the 532 * thread_struct, move them to the transact_fp array. 533 * We clear the TIF_RESTORE_TM bit since after the reclaim 534 * the thread will no longer be transactional. 535 */ 536 if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { 537 msr_diff = thr->tm_orig_msr & ~thr->regs->msr; 538 if (msr_diff & MSR_FP) 539 memcpy(&thr->transact_fp, &thr->fp_state, 540 sizeof(struct thread_fp_state)); 541 if (msr_diff & MSR_VEC) 542 memcpy(&thr->transact_vr, &thr->vr_state, 543 sizeof(struct thread_vr_state)); 544 clear_ti_thread_flag(ti, TIF_RESTORE_TM); 545 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; 546 } 547 548 tm_reclaim(thr, thr->regs->msr, cause); 549 550 /* Having done the reclaim, we now have the checkpointed 551 * FP/VSX values in the registers. These might be valid 552 * even if we have previously called enable_kernel_fp() or 553 * flush_fp_to_thread(), so update thr->regs->msr to 554 * indicate their current validity. 555 */ 556 thr->regs->msr |= msr_diff; 557 } 558 559 void tm_reclaim_current(uint8_t cause) 560 { 561 tm_enable(); 562 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 563 } 564 565 static inline void tm_reclaim_task(struct task_struct *tsk) 566 { 567 /* We have to work out if we're switching from/to a task that's in the 568 * middle of a transaction. 569 * 570 * In switching we need to maintain a 2nd register state as 571 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 572 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 573 * (current) FPRs into oldtask->thread.transact_fpr[]. 574 * 575 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 576 */ 577 struct thread_struct *thr = &tsk->thread; 578 579 if (!thr->regs) 580 return; 581 582 if (!MSR_TM_ACTIVE(thr->regs->msr)) 583 goto out_and_saveregs; 584 585 /* Stash the original thread MSR, as giveup_fpu et al will 586 * modify it. We hold onto it to see whether the task used 587 * FP & vector regs. If the TIF_RESTORE_TM flag is set, 588 * tm_orig_msr is already set. 589 */ 590 if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) 591 thr->tm_orig_msr = thr->regs->msr; 592 593 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 594 "ccr=%lx, msr=%lx, trap=%lx)\n", 595 tsk->pid, thr->regs->nip, 596 thr->regs->ccr, thr->regs->msr, 597 thr->regs->trap); 598 599 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 600 601 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 602 tsk->pid); 603 604 out_and_saveregs: 605 /* Always save the regs here, even if a transaction's not active. 606 * This context-switches a thread's TM info SPRs. We do it here to 607 * be consistent with the restore path (in recheckpoint) which 608 * cannot happen later in _switch(). 609 */ 610 tm_save_sprs(thr); 611 } 612 613 extern void __tm_recheckpoint(struct thread_struct *thread, 614 unsigned long orig_msr); 615 616 void tm_recheckpoint(struct thread_struct *thread, 617 unsigned long orig_msr) 618 { 619 unsigned long flags; 620 621 /* We really can't be interrupted here as the TEXASR registers can't 622 * change and later in the trecheckpoint code, we have a userspace R1. 623 * So let's hard disable over this region. 624 */ 625 local_irq_save(flags); 626 hard_irq_disable(); 627 628 /* The TM SPRs are restored here, so that TEXASR.FS can be set 629 * before the trecheckpoint and no explosion occurs. 630 */ 631 tm_restore_sprs(thread); 632 633 __tm_recheckpoint(thread, orig_msr); 634 635 local_irq_restore(flags); 636 } 637 638 static inline void tm_recheckpoint_new_task(struct task_struct *new) 639 { 640 unsigned long msr; 641 642 if (!cpu_has_feature(CPU_FTR_TM)) 643 return; 644 645 /* Recheckpoint the registers of the thread we're about to switch to. 646 * 647 * If the task was using FP, we non-lazily reload both the original and 648 * the speculative FP register states. This is because the kernel 649 * doesn't see if/when a TM rollback occurs, so if we take an FP 650 * unavoidable later, we are unable to determine which set of FP regs 651 * need to be restored. 652 */ 653 if (!new->thread.regs) 654 return; 655 656 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 657 tm_restore_sprs(&new->thread); 658 return; 659 } 660 msr = new->thread.tm_orig_msr; 661 /* Recheckpoint to restore original checkpointed register state. */ 662 TM_DEBUG("*** tm_recheckpoint of pid %d " 663 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 664 new->pid, new->thread.regs->msr, msr); 665 666 /* This loads the checkpointed FP/VEC state, if used */ 667 tm_recheckpoint(&new->thread, msr); 668 669 /* This loads the speculative FP/VEC state, if used */ 670 if (msr & MSR_FP) { 671 do_load_up_transact_fpu(&new->thread); 672 new->thread.regs->msr |= 673 (MSR_FP | new->thread.fpexc_mode); 674 } 675 #ifdef CONFIG_ALTIVEC 676 if (msr & MSR_VEC) { 677 do_load_up_transact_altivec(&new->thread); 678 new->thread.regs->msr |= MSR_VEC; 679 } 680 #endif 681 /* We may as well turn on VSX too since all the state is restored now */ 682 if (msr & MSR_VSX) 683 new->thread.regs->msr |= MSR_VSX; 684 685 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 686 "(kernel msr 0x%lx)\n", 687 new->pid, mfmsr()); 688 } 689 690 static inline void __switch_to_tm(struct task_struct *prev) 691 { 692 if (cpu_has_feature(CPU_FTR_TM)) { 693 tm_enable(); 694 tm_reclaim_task(prev); 695 } 696 } 697 698 /* 699 * This is called if we are on the way out to userspace and the 700 * TIF_RESTORE_TM flag is set. It checks if we need to reload 701 * FP and/or vector state and does so if necessary. 702 * If userspace is inside a transaction (whether active or 703 * suspended) and FP/VMX/VSX instructions have ever been enabled 704 * inside that transaction, then we have to keep them enabled 705 * and keep the FP/VMX/VSX state loaded while ever the transaction 706 * continues. The reason is that if we didn't, and subsequently 707 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 708 * we don't know whether it's the same transaction, and thus we 709 * don't know which of the checkpointed state and the transactional 710 * state to use. 711 */ 712 void restore_tm_state(struct pt_regs *regs) 713 { 714 unsigned long msr_diff; 715 716 clear_thread_flag(TIF_RESTORE_TM); 717 if (!MSR_TM_ACTIVE(regs->msr)) 718 return; 719 720 msr_diff = current->thread.tm_orig_msr & ~regs->msr; 721 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 722 if (msr_diff & MSR_FP) { 723 fp_enable(); 724 load_fp_state(¤t->thread.fp_state); 725 regs->msr |= current->thread.fpexc_mode; 726 } 727 if (msr_diff & MSR_VEC) { 728 vec_enable(); 729 load_vr_state(¤t->thread.vr_state); 730 } 731 regs->msr |= msr_diff; 732 } 733 734 #else 735 #define tm_recheckpoint_new_task(new) 736 #define __switch_to_tm(prev) 737 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 738 739 struct task_struct *__switch_to(struct task_struct *prev, 740 struct task_struct *new) 741 { 742 struct thread_struct *new_thread, *old_thread; 743 struct task_struct *last; 744 #ifdef CONFIG_PPC_BOOK3S_64 745 struct ppc64_tlb_batch *batch; 746 #endif 747 748 WARN_ON(!irqs_disabled()); 749 750 /* Back up the TAR across context switches. 751 * Note that the TAR is not available for use in the kernel. (To 752 * provide this, the TAR should be backed up/restored on exception 753 * entry/exit instead, and be in pt_regs. FIXME, this should be in 754 * pt_regs anyway (for debug).) 755 * Save the TAR here before we do treclaim/trecheckpoint as these 756 * will change the TAR. 757 */ 758 save_tar(&prev->thread); 759 760 __switch_to_tm(prev); 761 762 #ifdef CONFIG_SMP 763 /* avoid complexity of lazy save/restore of fpu 764 * by just saving it every time we switch out if 765 * this task used the fpu during the last quantum. 766 * 767 * If it tries to use the fpu again, it'll trap and 768 * reload its fp regs. So we don't have to do a restore 769 * every switch, just a save. 770 * -- Cort 771 */ 772 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) 773 giveup_fpu(prev); 774 #ifdef CONFIG_ALTIVEC 775 /* 776 * If the previous thread used altivec in the last quantum 777 * (thus changing altivec regs) then save them. 778 * We used to check the VRSAVE register but not all apps 779 * set it, so we don't rely on it now (and in fact we need 780 * to save & restore VSCR even if VRSAVE == 0). -- paulus 781 * 782 * On SMP we always save/restore altivec regs just to avoid the 783 * complexity of changing processors. 784 * -- Cort 785 */ 786 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) 787 giveup_altivec(prev); 788 #endif /* CONFIG_ALTIVEC */ 789 #ifdef CONFIG_VSX 790 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) 791 /* VMX and FPU registers are already save here */ 792 __giveup_vsx(prev); 793 #endif /* CONFIG_VSX */ 794 #ifdef CONFIG_SPE 795 /* 796 * If the previous thread used spe in the last quantum 797 * (thus changing spe regs) then save them. 798 * 799 * On SMP we always save/restore spe regs just to avoid the 800 * complexity of changing processors. 801 */ 802 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) 803 giveup_spe(prev); 804 #endif /* CONFIG_SPE */ 805 806 #else /* CONFIG_SMP */ 807 #ifdef CONFIG_ALTIVEC 808 /* Avoid the trap. On smp this this never happens since 809 * we don't set last_task_used_altivec -- Cort 810 */ 811 if (new->thread.regs && last_task_used_altivec == new) 812 new->thread.regs->msr |= MSR_VEC; 813 #endif /* CONFIG_ALTIVEC */ 814 #ifdef CONFIG_VSX 815 if (new->thread.regs && last_task_used_vsx == new) 816 new->thread.regs->msr |= MSR_VSX; 817 #endif /* CONFIG_VSX */ 818 #ifdef CONFIG_SPE 819 /* Avoid the trap. On smp this this never happens since 820 * we don't set last_task_used_spe 821 */ 822 if (new->thread.regs && last_task_used_spe == new) 823 new->thread.regs->msr |= MSR_SPE; 824 #endif /* CONFIG_SPE */ 825 826 #endif /* CONFIG_SMP */ 827 828 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 829 switch_booke_debug_regs(&new->thread.debug); 830 #else 831 /* 832 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 833 * schedule DABR 834 */ 835 #ifndef CONFIG_HAVE_HW_BREAKPOINT 836 if (unlikely(!hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) 837 set_breakpoint(&new->thread.hw_brk); 838 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 839 #endif 840 841 842 new_thread = &new->thread; 843 old_thread = ¤t->thread; 844 845 #ifdef CONFIG_PPC64 846 /* 847 * Collect processor utilization data per process 848 */ 849 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 850 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); 851 long unsigned start_tb, current_tb; 852 start_tb = old_thread->start_tb; 853 cu->current_tb = current_tb = mfspr(SPRN_PURR); 854 old_thread->accum_tb += (current_tb - start_tb); 855 new_thread->start_tb = current_tb; 856 } 857 #endif /* CONFIG_PPC64 */ 858 859 #ifdef CONFIG_PPC_BOOK3S_64 860 batch = &__get_cpu_var(ppc64_tlb_batch); 861 if (batch->active) { 862 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 863 if (batch->index) 864 __flush_tlb_pending(batch); 865 batch->active = 0; 866 } 867 #endif /* CONFIG_PPC_BOOK3S_64 */ 868 869 /* 870 * We can't take a PMU exception inside _switch() since there is a 871 * window where the kernel stack SLB and the kernel stack are out 872 * of sync. Hard disable here. 873 */ 874 hard_irq_disable(); 875 876 tm_recheckpoint_new_task(new); 877 878 last = _switch(old_thread, new_thread); 879 880 #ifdef CONFIG_PPC_BOOK3S_64 881 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 882 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 883 batch = &__get_cpu_var(ppc64_tlb_batch); 884 batch->active = 1; 885 } 886 #endif /* CONFIG_PPC_BOOK3S_64 */ 887 888 return last; 889 } 890 891 static int instructions_to_print = 16; 892 893 static void show_instructions(struct pt_regs *regs) 894 { 895 int i; 896 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 897 sizeof(int)); 898 899 printk("Instruction dump:"); 900 901 for (i = 0; i < instructions_to_print; i++) { 902 int instr; 903 904 if (!(i % 8)) 905 printk("\n"); 906 907 #if !defined(CONFIG_BOOKE) 908 /* If executing with the IMMU off, adjust pc rather 909 * than print XXXXXXXX. 910 */ 911 if (!(regs->msr & MSR_IR)) 912 pc = (unsigned long)phys_to_virt(pc); 913 #endif 914 915 /* We use __get_user here *only* to avoid an OOPS on a 916 * bad address because the pc *should* only be a 917 * kernel address. 918 */ 919 if (!__kernel_text_address(pc) || 920 __get_user(instr, (unsigned int __user *)pc)) { 921 printk(KERN_CONT "XXXXXXXX "); 922 } else { 923 if (regs->nip == pc) 924 printk(KERN_CONT "<%08x> ", instr); 925 else 926 printk(KERN_CONT "%08x ", instr); 927 } 928 929 pc += sizeof(int); 930 } 931 932 printk("\n"); 933 } 934 935 static struct regbit { 936 unsigned long bit; 937 const char *name; 938 } msr_bits[] = { 939 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 940 {MSR_SF, "SF"}, 941 {MSR_HV, "HV"}, 942 #endif 943 {MSR_VEC, "VEC"}, 944 {MSR_VSX, "VSX"}, 945 #ifdef CONFIG_BOOKE 946 {MSR_CE, "CE"}, 947 #endif 948 {MSR_EE, "EE"}, 949 {MSR_PR, "PR"}, 950 {MSR_FP, "FP"}, 951 {MSR_ME, "ME"}, 952 #ifdef CONFIG_BOOKE 953 {MSR_DE, "DE"}, 954 #else 955 {MSR_SE, "SE"}, 956 {MSR_BE, "BE"}, 957 #endif 958 {MSR_IR, "IR"}, 959 {MSR_DR, "DR"}, 960 {MSR_PMM, "PMM"}, 961 #ifndef CONFIG_BOOKE 962 {MSR_RI, "RI"}, 963 {MSR_LE, "LE"}, 964 #endif 965 {0, NULL} 966 }; 967 968 static void printbits(unsigned long val, struct regbit *bits) 969 { 970 const char *sep = ""; 971 972 printk("<"); 973 for (; bits->bit; ++bits) 974 if (val & bits->bit) { 975 printk("%s%s", sep, bits->name); 976 sep = ","; 977 } 978 printk(">"); 979 } 980 981 #ifdef CONFIG_PPC64 982 #define REG "%016lx" 983 #define REGS_PER_LINE 4 984 #define LAST_VOLATILE 13 985 #else 986 #define REG "%08lx" 987 #define REGS_PER_LINE 8 988 #define LAST_VOLATILE 12 989 #endif 990 991 void show_regs(struct pt_regs * regs) 992 { 993 int i, trap; 994 995 show_regs_print_info(KERN_DEFAULT); 996 997 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 998 regs->nip, regs->link, regs->ctr); 999 printk("REGS: %p TRAP: %04lx %s (%s)\n", 1000 regs, regs->trap, print_tainted(), init_utsname()->release); 1001 printk("MSR: "REG" ", regs->msr); 1002 printbits(regs->msr, msr_bits); 1003 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1004 trap = TRAP(regs); 1005 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1006 printk("CFAR: "REG" ", regs->orig_gpr3); 1007 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1008 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1009 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1010 #else 1011 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1012 #endif 1013 #ifdef CONFIG_PPC64 1014 printk("SOFTE: %ld ", regs->softe); 1015 #endif 1016 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1017 if (MSR_TM_ACTIVE(regs->msr)) 1018 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1019 #endif 1020 1021 for (i = 0; i < 32; i++) { 1022 if ((i % REGS_PER_LINE) == 0) 1023 printk("\nGPR%02d: ", i); 1024 printk(REG " ", regs->gpr[i]); 1025 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1026 break; 1027 } 1028 printk("\n"); 1029 #ifdef CONFIG_KALLSYMS 1030 /* 1031 * Lookup NIP late so we have the best change of getting the 1032 * above info out without failing 1033 */ 1034 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1035 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1036 #endif 1037 show_stack(current, (unsigned long *) regs->gpr[1]); 1038 if (!user_mode(regs)) 1039 show_instructions(regs); 1040 } 1041 1042 void exit_thread(void) 1043 { 1044 discard_lazy_cpu_state(); 1045 } 1046 1047 void flush_thread(void) 1048 { 1049 discard_lazy_cpu_state(); 1050 1051 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1052 flush_ptrace_hw_breakpoint(current); 1053 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1054 set_debug_reg_defaults(¤t->thread); 1055 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1056 } 1057 1058 void 1059 release_thread(struct task_struct *t) 1060 { 1061 } 1062 1063 /* 1064 * this gets called so that we can store coprocessor state into memory and 1065 * copy the current task into the new thread. 1066 */ 1067 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1068 { 1069 flush_fp_to_thread(src); 1070 flush_altivec_to_thread(src); 1071 flush_vsx_to_thread(src); 1072 flush_spe_to_thread(src); 1073 /* 1074 * Flush TM state out so we can copy it. __switch_to_tm() does this 1075 * flush but it removes the checkpointed state from the current CPU and 1076 * transitions the CPU out of TM mode. Hence we need to call 1077 * tm_recheckpoint_new_task() (on the same task) to restore the 1078 * checkpointed state back and the TM mode. 1079 */ 1080 __switch_to_tm(src); 1081 tm_recheckpoint_new_task(src); 1082 1083 *dst = *src; 1084 1085 clear_task_ebb(dst); 1086 1087 return 0; 1088 } 1089 1090 /* 1091 * Copy a thread.. 1092 */ 1093 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */ 1094 1095 int copy_thread(unsigned long clone_flags, unsigned long usp, 1096 unsigned long arg, struct task_struct *p) 1097 { 1098 struct pt_regs *childregs, *kregs; 1099 extern void ret_from_fork(void); 1100 extern void ret_from_kernel_thread(void); 1101 void (*f)(void); 1102 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1103 1104 /* Copy registers */ 1105 sp -= sizeof(struct pt_regs); 1106 childregs = (struct pt_regs *) sp; 1107 if (unlikely(p->flags & PF_KTHREAD)) { 1108 struct thread_info *ti = (void *)task_stack_page(p); 1109 memset(childregs, 0, sizeof(struct pt_regs)); 1110 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1111 childregs->gpr[14] = usp; /* function */ 1112 #ifdef CONFIG_PPC64 1113 clear_tsk_thread_flag(p, TIF_32BIT); 1114 childregs->softe = 1; 1115 #endif 1116 childregs->gpr[15] = arg; 1117 p->thread.regs = NULL; /* no user register state */ 1118 ti->flags |= _TIF_RESTOREALL; 1119 f = ret_from_kernel_thread; 1120 } else { 1121 struct pt_regs *regs = current_pt_regs(); 1122 CHECK_FULL_REGS(regs); 1123 *childregs = *regs; 1124 if (usp) 1125 childregs->gpr[1] = usp; 1126 p->thread.regs = childregs; 1127 childregs->gpr[3] = 0; /* Result from fork() */ 1128 if (clone_flags & CLONE_SETTLS) { 1129 #ifdef CONFIG_PPC64 1130 if (!is_32bit_task()) 1131 childregs->gpr[13] = childregs->gpr[6]; 1132 else 1133 #endif 1134 childregs->gpr[2] = childregs->gpr[6]; 1135 } 1136 1137 f = ret_from_fork; 1138 } 1139 sp -= STACK_FRAME_OVERHEAD; 1140 1141 /* 1142 * The way this works is that at some point in the future 1143 * some task will call _switch to switch to the new task. 1144 * That will pop off the stack frame created below and start 1145 * the new task running at ret_from_fork. The new task will 1146 * do some house keeping and then return from the fork or clone 1147 * system call, using the stack frame created above. 1148 */ 1149 ((unsigned long *)sp)[0] = 0; 1150 sp -= sizeof(struct pt_regs); 1151 kregs = (struct pt_regs *) sp; 1152 sp -= STACK_FRAME_OVERHEAD; 1153 p->thread.ksp = sp; 1154 #ifdef CONFIG_PPC32 1155 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1156 _ALIGN_UP(sizeof(struct thread_info), 16); 1157 #endif 1158 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1159 p->thread.ptrace_bps[0] = NULL; 1160 #endif 1161 1162 p->thread.fp_save_area = NULL; 1163 #ifdef CONFIG_ALTIVEC 1164 p->thread.vr_save_area = NULL; 1165 #endif 1166 1167 #ifdef CONFIG_PPC_STD_MMU_64 1168 if (mmu_has_feature(MMU_FTR_SLB)) { 1169 unsigned long sp_vsid; 1170 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1171 1172 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1173 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1174 << SLB_VSID_SHIFT_1T; 1175 else 1176 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1177 << SLB_VSID_SHIFT; 1178 sp_vsid |= SLB_VSID_KERNEL | llp; 1179 p->thread.ksp_vsid = sp_vsid; 1180 } 1181 #endif /* CONFIG_PPC_STD_MMU_64 */ 1182 #ifdef CONFIG_PPC64 1183 if (cpu_has_feature(CPU_FTR_DSCR)) { 1184 p->thread.dscr_inherit = current->thread.dscr_inherit; 1185 p->thread.dscr = current->thread.dscr; 1186 } 1187 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1188 p->thread.ppr = INIT_PPR; 1189 #endif 1190 /* 1191 * The PPC64 ABI makes use of a TOC to contain function 1192 * pointers. The function (ret_from_except) is actually a pointer 1193 * to the TOC entry. The first entry is a pointer to the actual 1194 * function. 1195 */ 1196 #ifdef CONFIG_PPC64 1197 kregs->nip = *((unsigned long *)f); 1198 #else 1199 kregs->nip = (unsigned long)f; 1200 #endif 1201 return 0; 1202 } 1203 1204 /* 1205 * Set up a thread for executing a new program 1206 */ 1207 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1208 { 1209 #ifdef CONFIG_PPC64 1210 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1211 #endif 1212 1213 /* 1214 * If we exec out of a kernel thread then thread.regs will not be 1215 * set. Do it now. 1216 */ 1217 if (!current->thread.regs) { 1218 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1219 current->thread.regs = regs - 1; 1220 } 1221 1222 memset(regs->gpr, 0, sizeof(regs->gpr)); 1223 regs->ctr = 0; 1224 regs->link = 0; 1225 regs->xer = 0; 1226 regs->ccr = 0; 1227 regs->gpr[1] = sp; 1228 1229 /* 1230 * We have just cleared all the nonvolatile GPRs, so make 1231 * FULL_REGS(regs) return true. This is necessary to allow 1232 * ptrace to examine the thread immediately after exec. 1233 */ 1234 regs->trap &= ~1UL; 1235 1236 #ifdef CONFIG_PPC32 1237 regs->mq = 0; 1238 regs->nip = start; 1239 regs->msr = MSR_USER; 1240 #else 1241 if (!is_32bit_task()) { 1242 unsigned long entry; 1243 1244 if (is_elf2_task()) { 1245 /* Look ma, no function descriptors! */ 1246 entry = start; 1247 1248 /* 1249 * Ulrich says: 1250 * The latest iteration of the ABI requires that when 1251 * calling a function (at its global entry point), 1252 * the caller must ensure r12 holds the entry point 1253 * address (so that the function can quickly 1254 * establish addressability). 1255 */ 1256 regs->gpr[12] = start; 1257 /* Make sure that's restored on entry to userspace. */ 1258 set_thread_flag(TIF_RESTOREALL); 1259 } else { 1260 unsigned long toc; 1261 1262 /* start is a relocated pointer to the function 1263 * descriptor for the elf _start routine. The first 1264 * entry in the function descriptor is the entry 1265 * address of _start and the second entry is the TOC 1266 * value we need to use. 1267 */ 1268 __get_user(entry, (unsigned long __user *)start); 1269 __get_user(toc, (unsigned long __user *)start+1); 1270 1271 /* Check whether the e_entry function descriptor entries 1272 * need to be relocated before we can use them. 1273 */ 1274 if (load_addr != 0) { 1275 entry += load_addr; 1276 toc += load_addr; 1277 } 1278 regs->gpr[2] = toc; 1279 } 1280 regs->nip = entry; 1281 regs->msr = MSR_USER64; 1282 } else { 1283 regs->nip = start; 1284 regs->gpr[2] = 0; 1285 regs->msr = MSR_USER32; 1286 } 1287 #endif 1288 discard_lazy_cpu_state(); 1289 #ifdef CONFIG_VSX 1290 current->thread.used_vsr = 0; 1291 #endif 1292 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1293 current->thread.fp_save_area = NULL; 1294 #ifdef CONFIG_ALTIVEC 1295 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1296 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1297 current->thread.vr_save_area = NULL; 1298 current->thread.vrsave = 0; 1299 current->thread.used_vr = 0; 1300 #endif /* CONFIG_ALTIVEC */ 1301 #ifdef CONFIG_SPE 1302 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1303 current->thread.acc = 0; 1304 current->thread.spefscr = 0; 1305 current->thread.used_spe = 0; 1306 #endif /* CONFIG_SPE */ 1307 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1308 if (cpu_has_feature(CPU_FTR_TM)) 1309 regs->msr |= MSR_TM; 1310 current->thread.tm_tfhar = 0; 1311 current->thread.tm_texasr = 0; 1312 current->thread.tm_tfiar = 0; 1313 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1314 } 1315 1316 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1317 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1318 1319 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1320 { 1321 struct pt_regs *regs = tsk->thread.regs; 1322 1323 /* This is a bit hairy. If we are an SPE enabled processor 1324 * (have embedded fp) we store the IEEE exception enable flags in 1325 * fpexc_mode. fpexc_mode is also used for setting FP exception 1326 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1327 if (val & PR_FP_EXC_SW_ENABLE) { 1328 #ifdef CONFIG_SPE 1329 if (cpu_has_feature(CPU_FTR_SPE)) { 1330 /* 1331 * When the sticky exception bits are set 1332 * directly by userspace, it must call prctl 1333 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1334 * in the existing prctl settings) or 1335 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1336 * the bits being set). <fenv.h> functions 1337 * saving and restoring the whole 1338 * floating-point environment need to do so 1339 * anyway to restore the prctl settings from 1340 * the saved environment. 1341 */ 1342 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1343 tsk->thread.fpexc_mode = val & 1344 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1345 return 0; 1346 } else { 1347 return -EINVAL; 1348 } 1349 #else 1350 return -EINVAL; 1351 #endif 1352 } 1353 1354 /* on a CONFIG_SPE this does not hurt us. The bits that 1355 * __pack_fe01 use do not overlap with bits used for 1356 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1357 * on CONFIG_SPE implementations are reserved so writing to 1358 * them does not change anything */ 1359 if (val > PR_FP_EXC_PRECISE) 1360 return -EINVAL; 1361 tsk->thread.fpexc_mode = __pack_fe01(val); 1362 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1363 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1364 | tsk->thread.fpexc_mode; 1365 return 0; 1366 } 1367 1368 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1369 { 1370 unsigned int val; 1371 1372 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1373 #ifdef CONFIG_SPE 1374 if (cpu_has_feature(CPU_FTR_SPE)) { 1375 /* 1376 * When the sticky exception bits are set 1377 * directly by userspace, it must call prctl 1378 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1379 * in the existing prctl settings) or 1380 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1381 * the bits being set). <fenv.h> functions 1382 * saving and restoring the whole 1383 * floating-point environment need to do so 1384 * anyway to restore the prctl settings from 1385 * the saved environment. 1386 */ 1387 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1388 val = tsk->thread.fpexc_mode; 1389 } else 1390 return -EINVAL; 1391 #else 1392 return -EINVAL; 1393 #endif 1394 else 1395 val = __unpack_fe01(tsk->thread.fpexc_mode); 1396 return put_user(val, (unsigned int __user *) adr); 1397 } 1398 1399 int set_endian(struct task_struct *tsk, unsigned int val) 1400 { 1401 struct pt_regs *regs = tsk->thread.regs; 1402 1403 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1404 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1405 return -EINVAL; 1406 1407 if (regs == NULL) 1408 return -EINVAL; 1409 1410 if (val == PR_ENDIAN_BIG) 1411 regs->msr &= ~MSR_LE; 1412 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1413 regs->msr |= MSR_LE; 1414 else 1415 return -EINVAL; 1416 1417 return 0; 1418 } 1419 1420 int get_endian(struct task_struct *tsk, unsigned long adr) 1421 { 1422 struct pt_regs *regs = tsk->thread.regs; 1423 unsigned int val; 1424 1425 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1426 !cpu_has_feature(CPU_FTR_REAL_LE)) 1427 return -EINVAL; 1428 1429 if (regs == NULL) 1430 return -EINVAL; 1431 1432 if (regs->msr & MSR_LE) { 1433 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1434 val = PR_ENDIAN_LITTLE; 1435 else 1436 val = PR_ENDIAN_PPC_LITTLE; 1437 } else 1438 val = PR_ENDIAN_BIG; 1439 1440 return put_user(val, (unsigned int __user *)adr); 1441 } 1442 1443 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1444 { 1445 tsk->thread.align_ctl = val; 1446 return 0; 1447 } 1448 1449 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1450 { 1451 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1452 } 1453 1454 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1455 unsigned long nbytes) 1456 { 1457 unsigned long stack_page; 1458 unsigned long cpu = task_cpu(p); 1459 1460 /* 1461 * Avoid crashing if the stack has overflowed and corrupted 1462 * task_cpu(p), which is in the thread_info struct. 1463 */ 1464 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1465 stack_page = (unsigned long) hardirq_ctx[cpu]; 1466 if (sp >= stack_page + sizeof(struct thread_struct) 1467 && sp <= stack_page + THREAD_SIZE - nbytes) 1468 return 1; 1469 1470 stack_page = (unsigned long) softirq_ctx[cpu]; 1471 if (sp >= stack_page + sizeof(struct thread_struct) 1472 && sp <= stack_page + THREAD_SIZE - nbytes) 1473 return 1; 1474 } 1475 return 0; 1476 } 1477 1478 int validate_sp(unsigned long sp, struct task_struct *p, 1479 unsigned long nbytes) 1480 { 1481 unsigned long stack_page = (unsigned long)task_stack_page(p); 1482 1483 if (sp >= stack_page + sizeof(struct thread_struct) 1484 && sp <= stack_page + THREAD_SIZE - nbytes) 1485 return 1; 1486 1487 return valid_irq_stack(sp, p, nbytes); 1488 } 1489 1490 EXPORT_SYMBOL(validate_sp); 1491 1492 unsigned long get_wchan(struct task_struct *p) 1493 { 1494 unsigned long ip, sp; 1495 int count = 0; 1496 1497 if (!p || p == current || p->state == TASK_RUNNING) 1498 return 0; 1499 1500 sp = p->thread.ksp; 1501 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1502 return 0; 1503 1504 do { 1505 sp = *(unsigned long *)sp; 1506 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1507 return 0; 1508 if (count > 0) { 1509 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1510 if (!in_sched_functions(ip)) 1511 return ip; 1512 } 1513 } while (count++ < 16); 1514 return 0; 1515 } 1516 1517 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1518 1519 void show_stack(struct task_struct *tsk, unsigned long *stack) 1520 { 1521 unsigned long sp, ip, lr, newsp; 1522 int count = 0; 1523 int firstframe = 1; 1524 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1525 int curr_frame = current->curr_ret_stack; 1526 extern void return_to_handler(void); 1527 unsigned long rth = (unsigned long)return_to_handler; 1528 unsigned long mrth = -1; 1529 #ifdef CONFIG_PPC64 1530 extern void mod_return_to_handler(void); 1531 rth = *(unsigned long *)rth; 1532 mrth = (unsigned long)mod_return_to_handler; 1533 mrth = *(unsigned long *)mrth; 1534 #endif 1535 #endif 1536 1537 sp = (unsigned long) stack; 1538 if (tsk == NULL) 1539 tsk = current; 1540 if (sp == 0) { 1541 if (tsk == current) 1542 asm("mr %0,1" : "=r" (sp)); 1543 else 1544 sp = tsk->thread.ksp; 1545 } 1546 1547 lr = 0; 1548 printk("Call Trace:\n"); 1549 do { 1550 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1551 return; 1552 1553 stack = (unsigned long *) sp; 1554 newsp = stack[0]; 1555 ip = stack[STACK_FRAME_LR_SAVE]; 1556 if (!firstframe || ip != lr) { 1557 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1558 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1559 if ((ip == rth || ip == mrth) && curr_frame >= 0) { 1560 printk(" (%pS)", 1561 (void *)current->ret_stack[curr_frame].ret); 1562 curr_frame--; 1563 } 1564 #endif 1565 if (firstframe) 1566 printk(" (unreliable)"); 1567 printk("\n"); 1568 } 1569 firstframe = 0; 1570 1571 /* 1572 * See if this is an exception frame. 1573 * We look for the "regshere" marker in the current frame. 1574 */ 1575 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1576 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1577 struct pt_regs *regs = (struct pt_regs *) 1578 (sp + STACK_FRAME_OVERHEAD); 1579 lr = regs->link; 1580 printk("--- Exception: %lx at %pS\n LR = %pS\n", 1581 regs->trap, (void *)regs->nip, (void *)lr); 1582 firstframe = 1; 1583 } 1584 1585 sp = newsp; 1586 } while (count++ < kstack_depth_to_print); 1587 } 1588 1589 #ifdef CONFIG_PPC64 1590 /* Called with hard IRQs off */ 1591 void notrace __ppc64_runlatch_on(void) 1592 { 1593 struct thread_info *ti = current_thread_info(); 1594 unsigned long ctrl; 1595 1596 ctrl = mfspr(SPRN_CTRLF); 1597 ctrl |= CTRL_RUNLATCH; 1598 mtspr(SPRN_CTRLT, ctrl); 1599 1600 ti->local_flags |= _TLF_RUNLATCH; 1601 } 1602 1603 /* Called with hard IRQs off */ 1604 void notrace __ppc64_runlatch_off(void) 1605 { 1606 struct thread_info *ti = current_thread_info(); 1607 unsigned long ctrl; 1608 1609 ti->local_flags &= ~_TLF_RUNLATCH; 1610 1611 ctrl = mfspr(SPRN_CTRLF); 1612 ctrl &= ~CTRL_RUNLATCH; 1613 mtspr(SPRN_CTRLT, ctrl); 1614 } 1615 #endif /* CONFIG_PPC64 */ 1616 1617 unsigned long arch_align_stack(unsigned long sp) 1618 { 1619 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1620 sp -= get_random_int() & ~PAGE_MASK; 1621 return sp & ~0xf; 1622 } 1623 1624 static inline unsigned long brk_rnd(void) 1625 { 1626 unsigned long rnd = 0; 1627 1628 /* 8MB for 32bit, 1GB for 64bit */ 1629 if (is_32bit_task()) 1630 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); 1631 else 1632 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); 1633 1634 return rnd << PAGE_SHIFT; 1635 } 1636 1637 unsigned long arch_randomize_brk(struct mm_struct *mm) 1638 { 1639 unsigned long base = mm->brk; 1640 unsigned long ret; 1641 1642 #ifdef CONFIG_PPC_STD_MMU_64 1643 /* 1644 * If we are using 1TB segments and we are allowed to randomise 1645 * the heap, we can put it above 1TB so it is backed by a 1TB 1646 * segment. Otherwise the heap will be in the bottom 1TB 1647 * which always uses 256MB segments and this may result in a 1648 * performance penalty. 1649 */ 1650 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1651 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1652 #endif 1653 1654 ret = PAGE_ALIGN(base + brk_rnd()); 1655 1656 if (ret < mm->brk) 1657 return mm->brk; 1658 1659 return ret; 1660 } 1661 1662 unsigned long randomize_et_dyn(unsigned long base) 1663 { 1664 unsigned long ret = PAGE_ALIGN(base + brk_rnd()); 1665 1666 if (ret < base) 1667 return base; 1668 1669 return ret; 1670 } 1671