1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/prctl.h> 29 #include <linux/init_task.h> 30 #include <linux/export.h> 31 #include <linux/kallsyms.h> 32 #include <linux/mqueue.h> 33 #include <linux/hardirq.h> 34 #include <linux/utsname.h> 35 #include <linux/ftrace.h> 36 #include <linux/kernel_stat.h> 37 #include <linux/personality.h> 38 #include <linux/random.h> 39 #include <linux/hw_breakpoint.h> 40 #include <linux/uaccess.h> 41 42 #include <asm/pgtable.h> 43 #include <asm/io.h> 44 #include <asm/processor.h> 45 #include <asm/mmu.h> 46 #include <asm/prom.h> 47 #include <asm/machdep.h> 48 #include <asm/time.h> 49 #include <asm/runlatch.h> 50 #include <asm/syscalls.h> 51 #include <asm/switch_to.h> 52 #include <asm/tm.h> 53 #include <asm/debug.h> 54 #ifdef CONFIG_PPC64 55 #include <asm/firmware.h> 56 #endif 57 #include <asm/code-patching.h> 58 #include <linux/kprobes.h> 59 #include <linux/kdebug.h> 60 61 /* Transactional Memory debug */ 62 #ifdef TM_DEBUG_SW 63 #define TM_DEBUG(x...) printk(KERN_INFO x) 64 #else 65 #define TM_DEBUG(x...) do { } while(0) 66 #endif 67 68 extern unsigned long _get_SP(void); 69 70 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 71 static void check_if_tm_restore_required(struct task_struct *tsk) 72 { 73 /* 74 * If we are saving the current thread's registers, and the 75 * thread is in a transactional state, set the TIF_RESTORE_TM 76 * bit so that we know to restore the registers before 77 * returning to userspace. 78 */ 79 if (tsk == current && tsk->thread.regs && 80 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 81 !test_thread_flag(TIF_RESTORE_TM)) { 82 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 83 set_thread_flag(TIF_RESTORE_TM); 84 } 85 } 86 #else 87 static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 88 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 89 90 bool strict_msr_control; 91 EXPORT_SYMBOL(strict_msr_control); 92 93 static int __init enable_strict_msr_control(char *str) 94 { 95 strict_msr_control = true; 96 pr_info("Enabling strict facility control\n"); 97 98 return 0; 99 } 100 early_param("ppc_strict_facility_enable", enable_strict_msr_control); 101 102 void msr_check_and_set(unsigned long bits) 103 { 104 unsigned long oldmsr = mfmsr(); 105 unsigned long newmsr; 106 107 newmsr = oldmsr | bits; 108 109 #ifdef CONFIG_VSX 110 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 111 newmsr |= MSR_VSX; 112 #endif 113 114 if (oldmsr != newmsr) 115 mtmsr_isync(newmsr); 116 } 117 118 void __msr_check_and_clear(unsigned long bits) 119 { 120 unsigned long oldmsr = mfmsr(); 121 unsigned long newmsr; 122 123 newmsr = oldmsr & ~bits; 124 125 #ifdef CONFIG_VSX 126 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 127 newmsr &= ~MSR_VSX; 128 #endif 129 130 if (oldmsr != newmsr) 131 mtmsr_isync(newmsr); 132 } 133 EXPORT_SYMBOL(__msr_check_and_clear); 134 135 #ifdef CONFIG_PPC_FPU 136 void giveup_fpu(struct task_struct *tsk) 137 { 138 check_if_tm_restore_required(tsk); 139 140 msr_check_and_set(MSR_FP); 141 __giveup_fpu(tsk); 142 msr_check_and_clear(MSR_FP); 143 } 144 EXPORT_SYMBOL(giveup_fpu); 145 146 /* 147 * Make sure the floating-point register state in the 148 * the thread_struct is up to date for task tsk. 149 */ 150 void flush_fp_to_thread(struct task_struct *tsk) 151 { 152 if (tsk->thread.regs) { 153 /* 154 * We need to disable preemption here because if we didn't, 155 * another process could get scheduled after the regs->msr 156 * test but before we have finished saving the FP registers 157 * to the thread_struct. That process could take over the 158 * FPU, and then when we get scheduled again we would store 159 * bogus values for the remaining FP registers. 160 */ 161 preempt_disable(); 162 if (tsk->thread.regs->msr & MSR_FP) { 163 /* 164 * This should only ever be called for current or 165 * for a stopped child process. Since we save away 166 * the FP register state on context switch, 167 * there is something wrong if a stopped child appears 168 * to still have its FP state in the CPU registers. 169 */ 170 BUG_ON(tsk != current); 171 giveup_fpu(tsk); 172 } 173 preempt_enable(); 174 } 175 } 176 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 177 178 void enable_kernel_fp(void) 179 { 180 WARN_ON(preemptible()); 181 182 msr_check_and_set(MSR_FP); 183 184 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 185 check_if_tm_restore_required(current); 186 __giveup_fpu(current); 187 } 188 } 189 EXPORT_SYMBOL(enable_kernel_fp); 190 #endif /* CONFIG_PPC_FPU */ 191 192 #ifdef CONFIG_ALTIVEC 193 void giveup_altivec(struct task_struct *tsk) 194 { 195 check_if_tm_restore_required(tsk); 196 197 msr_check_and_set(MSR_VEC); 198 __giveup_altivec(tsk); 199 msr_check_and_clear(MSR_VEC); 200 } 201 EXPORT_SYMBOL(giveup_altivec); 202 203 void enable_kernel_altivec(void) 204 { 205 WARN_ON(preemptible()); 206 207 msr_check_and_set(MSR_VEC); 208 209 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 210 check_if_tm_restore_required(current); 211 __giveup_altivec(current); 212 } 213 } 214 EXPORT_SYMBOL(enable_kernel_altivec); 215 216 /* 217 * Make sure the VMX/Altivec register state in the 218 * the thread_struct is up to date for task tsk. 219 */ 220 void flush_altivec_to_thread(struct task_struct *tsk) 221 { 222 if (tsk->thread.regs) { 223 preempt_disable(); 224 if (tsk->thread.regs->msr & MSR_VEC) { 225 BUG_ON(tsk != current); 226 giveup_altivec(tsk); 227 } 228 preempt_enable(); 229 } 230 } 231 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 232 #endif /* CONFIG_ALTIVEC */ 233 234 #ifdef CONFIG_VSX 235 void giveup_vsx(struct task_struct *tsk) 236 { 237 check_if_tm_restore_required(tsk); 238 239 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 240 if (tsk->thread.regs->msr & MSR_FP) 241 __giveup_fpu(tsk); 242 if (tsk->thread.regs->msr & MSR_VEC) 243 __giveup_altivec(tsk); 244 __giveup_vsx(tsk); 245 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 246 } 247 EXPORT_SYMBOL(giveup_vsx); 248 249 void enable_kernel_vsx(void) 250 { 251 WARN_ON(preemptible()); 252 253 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 254 255 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { 256 check_if_tm_restore_required(current); 257 if (current->thread.regs->msr & MSR_FP) 258 __giveup_fpu(current); 259 if (current->thread.regs->msr & MSR_VEC) 260 __giveup_altivec(current); 261 __giveup_vsx(current); 262 } 263 } 264 EXPORT_SYMBOL(enable_kernel_vsx); 265 266 void flush_vsx_to_thread(struct task_struct *tsk) 267 { 268 if (tsk->thread.regs) { 269 preempt_disable(); 270 if (tsk->thread.regs->msr & MSR_VSX) { 271 BUG_ON(tsk != current); 272 giveup_vsx(tsk); 273 } 274 preempt_enable(); 275 } 276 } 277 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 278 #endif /* CONFIG_VSX */ 279 280 #ifdef CONFIG_SPE 281 void giveup_spe(struct task_struct *tsk) 282 { 283 check_if_tm_restore_required(tsk); 284 285 msr_check_and_set(MSR_SPE); 286 __giveup_spe(tsk); 287 msr_check_and_clear(MSR_SPE); 288 } 289 EXPORT_SYMBOL(giveup_spe); 290 291 void enable_kernel_spe(void) 292 { 293 WARN_ON(preemptible()); 294 295 msr_check_and_set(MSR_SPE); 296 297 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 298 check_if_tm_restore_required(current); 299 __giveup_spe(current); 300 } 301 } 302 EXPORT_SYMBOL(enable_kernel_spe); 303 304 void flush_spe_to_thread(struct task_struct *tsk) 305 { 306 if (tsk->thread.regs) { 307 preempt_disable(); 308 if (tsk->thread.regs->msr & MSR_SPE) { 309 BUG_ON(tsk != current); 310 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 311 giveup_spe(tsk); 312 } 313 preempt_enable(); 314 } 315 } 316 #endif /* CONFIG_SPE */ 317 318 static unsigned long msr_all_available; 319 320 static int __init init_msr_all_available(void) 321 { 322 #ifdef CONFIG_PPC_FPU 323 msr_all_available |= MSR_FP; 324 #endif 325 #ifdef CONFIG_ALTIVEC 326 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 327 msr_all_available |= MSR_VEC; 328 #endif 329 #ifdef CONFIG_VSX 330 if (cpu_has_feature(CPU_FTR_VSX)) 331 msr_all_available |= MSR_VSX; 332 #endif 333 #ifdef CONFIG_SPE 334 if (cpu_has_feature(CPU_FTR_SPE)) 335 msr_all_available |= MSR_SPE; 336 #endif 337 338 return 0; 339 } 340 early_initcall(init_msr_all_available); 341 342 void giveup_all(struct task_struct *tsk) 343 { 344 unsigned long usermsr; 345 346 if (!tsk->thread.regs) 347 return; 348 349 usermsr = tsk->thread.regs->msr; 350 351 if ((usermsr & msr_all_available) == 0) 352 return; 353 354 msr_check_and_set(msr_all_available); 355 356 #ifdef CONFIG_PPC_FPU 357 if (usermsr & MSR_FP) 358 __giveup_fpu(tsk); 359 #endif 360 #ifdef CONFIG_ALTIVEC 361 if (usermsr & MSR_VEC) 362 __giveup_altivec(tsk); 363 #endif 364 #ifdef CONFIG_VSX 365 if (usermsr & MSR_VSX) 366 __giveup_vsx(tsk); 367 #endif 368 #ifdef CONFIG_SPE 369 if (usermsr & MSR_SPE) 370 __giveup_spe(tsk); 371 #endif 372 373 msr_check_and_clear(msr_all_available); 374 } 375 EXPORT_SYMBOL(giveup_all); 376 377 void flush_all_to_thread(struct task_struct *tsk) 378 { 379 if (tsk->thread.regs) { 380 preempt_disable(); 381 BUG_ON(tsk != current); 382 giveup_all(tsk); 383 384 #ifdef CONFIG_SPE 385 if (tsk->thread.regs->msr & MSR_SPE) 386 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 387 #endif 388 389 preempt_enable(); 390 } 391 } 392 EXPORT_SYMBOL(flush_all_to_thread); 393 394 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 395 void do_send_trap(struct pt_regs *regs, unsigned long address, 396 unsigned long error_code, int signal_code, int breakpt) 397 { 398 siginfo_t info; 399 400 current->thread.trap_nr = signal_code; 401 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 402 11, SIGSEGV) == NOTIFY_STOP) 403 return; 404 405 /* Deliver the signal to userspace */ 406 info.si_signo = SIGTRAP; 407 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 408 info.si_code = signal_code; 409 info.si_addr = (void __user *)address; 410 force_sig_info(SIGTRAP, &info, current); 411 } 412 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 413 void do_break (struct pt_regs *regs, unsigned long address, 414 unsigned long error_code) 415 { 416 siginfo_t info; 417 418 current->thread.trap_nr = TRAP_HWBKPT; 419 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 420 11, SIGSEGV) == NOTIFY_STOP) 421 return; 422 423 if (debugger_break_match(regs)) 424 return; 425 426 /* Clear the breakpoint */ 427 hw_breakpoint_disable(); 428 429 /* Deliver the signal to userspace */ 430 info.si_signo = SIGTRAP; 431 info.si_errno = 0; 432 info.si_code = TRAP_HWBKPT; 433 info.si_addr = (void __user *)address; 434 force_sig_info(SIGTRAP, &info, current); 435 } 436 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 437 438 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 439 440 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 441 /* 442 * Set the debug registers back to their default "safe" values. 443 */ 444 static void set_debug_reg_defaults(struct thread_struct *thread) 445 { 446 thread->debug.iac1 = thread->debug.iac2 = 0; 447 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 448 thread->debug.iac3 = thread->debug.iac4 = 0; 449 #endif 450 thread->debug.dac1 = thread->debug.dac2 = 0; 451 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 452 thread->debug.dvc1 = thread->debug.dvc2 = 0; 453 #endif 454 thread->debug.dbcr0 = 0; 455 #ifdef CONFIG_BOOKE 456 /* 457 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 458 */ 459 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 460 DBCR1_IAC3US | DBCR1_IAC4US; 461 /* 462 * Force Data Address Compare User/Supervisor bits to be User-only 463 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 464 */ 465 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 466 #else 467 thread->debug.dbcr1 = 0; 468 #endif 469 } 470 471 static void prime_debug_regs(struct debug_reg *debug) 472 { 473 /* 474 * We could have inherited MSR_DE from userspace, since 475 * it doesn't get cleared on exception entry. Make sure 476 * MSR_DE is clear before we enable any debug events. 477 */ 478 mtmsr(mfmsr() & ~MSR_DE); 479 480 mtspr(SPRN_IAC1, debug->iac1); 481 mtspr(SPRN_IAC2, debug->iac2); 482 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 483 mtspr(SPRN_IAC3, debug->iac3); 484 mtspr(SPRN_IAC4, debug->iac4); 485 #endif 486 mtspr(SPRN_DAC1, debug->dac1); 487 mtspr(SPRN_DAC2, debug->dac2); 488 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 489 mtspr(SPRN_DVC1, debug->dvc1); 490 mtspr(SPRN_DVC2, debug->dvc2); 491 #endif 492 mtspr(SPRN_DBCR0, debug->dbcr0); 493 mtspr(SPRN_DBCR1, debug->dbcr1); 494 #ifdef CONFIG_BOOKE 495 mtspr(SPRN_DBCR2, debug->dbcr2); 496 #endif 497 } 498 /* 499 * Unless neither the old or new thread are making use of the 500 * debug registers, set the debug registers from the values 501 * stored in the new thread. 502 */ 503 void switch_booke_debug_regs(struct debug_reg *new_debug) 504 { 505 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 506 || (new_debug->dbcr0 & DBCR0_IDM)) 507 prime_debug_regs(new_debug); 508 } 509 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 510 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 511 #ifndef CONFIG_HAVE_HW_BREAKPOINT 512 static void set_debug_reg_defaults(struct thread_struct *thread) 513 { 514 thread->hw_brk.address = 0; 515 thread->hw_brk.type = 0; 516 set_breakpoint(&thread->hw_brk); 517 } 518 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 519 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 520 521 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 522 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 523 { 524 mtspr(SPRN_DAC1, dabr); 525 #ifdef CONFIG_PPC_47x 526 isync(); 527 #endif 528 return 0; 529 } 530 #elif defined(CONFIG_PPC_BOOK3S) 531 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 532 { 533 mtspr(SPRN_DABR, dabr); 534 if (cpu_has_feature(CPU_FTR_DABRX)) 535 mtspr(SPRN_DABRX, dabrx); 536 return 0; 537 } 538 #else 539 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 540 { 541 return -EINVAL; 542 } 543 #endif 544 545 static inline int set_dabr(struct arch_hw_breakpoint *brk) 546 { 547 unsigned long dabr, dabrx; 548 549 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 550 dabrx = ((brk->type >> 3) & 0x7); 551 552 if (ppc_md.set_dabr) 553 return ppc_md.set_dabr(dabr, dabrx); 554 555 return __set_dabr(dabr, dabrx); 556 } 557 558 static inline int set_dawr(struct arch_hw_breakpoint *brk) 559 { 560 unsigned long dawr, dawrx, mrd; 561 562 dawr = brk->address; 563 564 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 565 << (63 - 58); //* read/write bits */ 566 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 567 << (63 - 59); //* translate */ 568 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 569 >> 3; //* PRIM bits */ 570 /* dawr length is stored in field MDR bits 48:53. Matches range in 571 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 572 0b111111=64DW. 573 brk->len is in bytes. 574 This aligns up to double word size, shifts and does the bias. 575 */ 576 mrd = ((brk->len + 7) >> 3) - 1; 577 dawrx |= (mrd & 0x3f) << (63 - 53); 578 579 if (ppc_md.set_dawr) 580 return ppc_md.set_dawr(dawr, dawrx); 581 mtspr(SPRN_DAWR, dawr); 582 mtspr(SPRN_DAWRX, dawrx); 583 return 0; 584 } 585 586 void __set_breakpoint(struct arch_hw_breakpoint *brk) 587 { 588 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); 589 590 if (cpu_has_feature(CPU_FTR_DAWR)) 591 set_dawr(brk); 592 else 593 set_dabr(brk); 594 } 595 596 void set_breakpoint(struct arch_hw_breakpoint *brk) 597 { 598 preempt_disable(); 599 __set_breakpoint(brk); 600 preempt_enable(); 601 } 602 603 #ifdef CONFIG_PPC64 604 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 605 #endif 606 607 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 608 struct arch_hw_breakpoint *b) 609 { 610 if (a->address != b->address) 611 return false; 612 if (a->type != b->type) 613 return false; 614 if (a->len != b->len) 615 return false; 616 return true; 617 } 618 619 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 620 static void tm_reclaim_thread(struct thread_struct *thr, 621 struct thread_info *ti, uint8_t cause) 622 { 623 unsigned long msr_diff = 0; 624 625 /* 626 * If FP/VSX registers have been already saved to the 627 * thread_struct, move them to the transact_fp array. 628 * We clear the TIF_RESTORE_TM bit since after the reclaim 629 * the thread will no longer be transactional. 630 */ 631 if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { 632 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr; 633 if (msr_diff & MSR_FP) 634 memcpy(&thr->transact_fp, &thr->fp_state, 635 sizeof(struct thread_fp_state)); 636 if (msr_diff & MSR_VEC) 637 memcpy(&thr->transact_vr, &thr->vr_state, 638 sizeof(struct thread_vr_state)); 639 clear_ti_thread_flag(ti, TIF_RESTORE_TM); 640 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; 641 } 642 643 /* 644 * Use the current MSR TM suspended bit to track if we have 645 * checkpointed state outstanding. 646 * On signal delivery, we'd normally reclaim the checkpointed 647 * state to obtain stack pointer (see:get_tm_stackpointer()). 648 * This will then directly return to userspace without going 649 * through __switch_to(). However, if the stack frame is bad, 650 * we need to exit this thread which calls __switch_to() which 651 * will again attempt to reclaim the already saved tm state. 652 * Hence we need to check that we've not already reclaimed 653 * this state. 654 * We do this using the current MSR, rather tracking it in 655 * some specific thread_struct bit, as it has the additional 656 * benifit of checking for a potential TM bad thing exception. 657 */ 658 if (!MSR_TM_SUSPENDED(mfmsr())) 659 return; 660 661 tm_reclaim(thr, thr->regs->msr, cause); 662 663 /* Having done the reclaim, we now have the checkpointed 664 * FP/VSX values in the registers. These might be valid 665 * even if we have previously called enable_kernel_fp() or 666 * flush_fp_to_thread(), so update thr->regs->msr to 667 * indicate their current validity. 668 */ 669 thr->regs->msr |= msr_diff; 670 } 671 672 void tm_reclaim_current(uint8_t cause) 673 { 674 tm_enable(); 675 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 676 } 677 678 static inline void tm_reclaim_task(struct task_struct *tsk) 679 { 680 /* We have to work out if we're switching from/to a task that's in the 681 * middle of a transaction. 682 * 683 * In switching we need to maintain a 2nd register state as 684 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 685 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 686 * (current) FPRs into oldtask->thread.transact_fpr[]. 687 * 688 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 689 */ 690 struct thread_struct *thr = &tsk->thread; 691 692 if (!thr->regs) 693 return; 694 695 if (!MSR_TM_ACTIVE(thr->regs->msr)) 696 goto out_and_saveregs; 697 698 /* Stash the original thread MSR, as giveup_fpu et al will 699 * modify it. We hold onto it to see whether the task used 700 * FP & vector regs. If the TIF_RESTORE_TM flag is set, 701 * ckpt_regs.msr is already set. 702 */ 703 if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) 704 thr->ckpt_regs.msr = thr->regs->msr; 705 706 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 707 "ccr=%lx, msr=%lx, trap=%lx)\n", 708 tsk->pid, thr->regs->nip, 709 thr->regs->ccr, thr->regs->msr, 710 thr->regs->trap); 711 712 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 713 714 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 715 tsk->pid); 716 717 out_and_saveregs: 718 /* Always save the regs here, even if a transaction's not active. 719 * This context-switches a thread's TM info SPRs. We do it here to 720 * be consistent with the restore path (in recheckpoint) which 721 * cannot happen later in _switch(). 722 */ 723 tm_save_sprs(thr); 724 } 725 726 extern void __tm_recheckpoint(struct thread_struct *thread, 727 unsigned long orig_msr); 728 729 void tm_recheckpoint(struct thread_struct *thread, 730 unsigned long orig_msr) 731 { 732 unsigned long flags; 733 734 /* We really can't be interrupted here as the TEXASR registers can't 735 * change and later in the trecheckpoint code, we have a userspace R1. 736 * So let's hard disable over this region. 737 */ 738 local_irq_save(flags); 739 hard_irq_disable(); 740 741 /* The TM SPRs are restored here, so that TEXASR.FS can be set 742 * before the trecheckpoint and no explosion occurs. 743 */ 744 tm_restore_sprs(thread); 745 746 __tm_recheckpoint(thread, orig_msr); 747 748 local_irq_restore(flags); 749 } 750 751 static inline void tm_recheckpoint_new_task(struct task_struct *new) 752 { 753 unsigned long msr; 754 755 if (!cpu_has_feature(CPU_FTR_TM)) 756 return; 757 758 /* Recheckpoint the registers of the thread we're about to switch to. 759 * 760 * If the task was using FP, we non-lazily reload both the original and 761 * the speculative FP register states. This is because the kernel 762 * doesn't see if/when a TM rollback occurs, so if we take an FP 763 * unavoidable later, we are unable to determine which set of FP regs 764 * need to be restored. 765 */ 766 if (!new->thread.regs) 767 return; 768 769 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 770 tm_restore_sprs(&new->thread); 771 return; 772 } 773 msr = new->thread.ckpt_regs.msr; 774 /* Recheckpoint to restore original checkpointed register state. */ 775 TM_DEBUG("*** tm_recheckpoint of pid %d " 776 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 777 new->pid, new->thread.regs->msr, msr); 778 779 /* This loads the checkpointed FP/VEC state, if used */ 780 tm_recheckpoint(&new->thread, msr); 781 782 /* This loads the speculative FP/VEC state, if used */ 783 if (msr & MSR_FP) { 784 do_load_up_transact_fpu(&new->thread); 785 new->thread.regs->msr |= 786 (MSR_FP | new->thread.fpexc_mode); 787 } 788 #ifdef CONFIG_ALTIVEC 789 if (msr & MSR_VEC) { 790 do_load_up_transact_altivec(&new->thread); 791 new->thread.regs->msr |= MSR_VEC; 792 } 793 #endif 794 /* We may as well turn on VSX too since all the state is restored now */ 795 if (msr & MSR_VSX) 796 new->thread.regs->msr |= MSR_VSX; 797 798 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 799 "(kernel msr 0x%lx)\n", 800 new->pid, mfmsr()); 801 } 802 803 static inline void __switch_to_tm(struct task_struct *prev) 804 { 805 if (cpu_has_feature(CPU_FTR_TM)) { 806 tm_enable(); 807 tm_reclaim_task(prev); 808 } 809 } 810 811 /* 812 * This is called if we are on the way out to userspace and the 813 * TIF_RESTORE_TM flag is set. It checks if we need to reload 814 * FP and/or vector state and does so if necessary. 815 * If userspace is inside a transaction (whether active or 816 * suspended) and FP/VMX/VSX instructions have ever been enabled 817 * inside that transaction, then we have to keep them enabled 818 * and keep the FP/VMX/VSX state loaded while ever the transaction 819 * continues. The reason is that if we didn't, and subsequently 820 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 821 * we don't know whether it's the same transaction, and thus we 822 * don't know which of the checkpointed state and the transactional 823 * state to use. 824 */ 825 void restore_tm_state(struct pt_regs *regs) 826 { 827 unsigned long msr_diff; 828 829 clear_thread_flag(TIF_RESTORE_TM); 830 if (!MSR_TM_ACTIVE(regs->msr)) 831 return; 832 833 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 834 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 835 if (msr_diff & MSR_FP) { 836 msr_check_and_set(MSR_FP); 837 load_fp_state(¤t->thread.fp_state); 838 msr_check_and_clear(MSR_FP); 839 regs->msr |= current->thread.fpexc_mode; 840 } 841 if (msr_diff & MSR_VEC) { 842 msr_check_and_set(MSR_VEC); 843 load_vr_state(¤t->thread.vr_state); 844 msr_check_and_clear(MSR_VEC); 845 } 846 regs->msr |= msr_diff; 847 } 848 849 #else 850 #define tm_recheckpoint_new_task(new) 851 #define __switch_to_tm(prev) 852 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 853 854 static inline void save_sprs(struct thread_struct *t) 855 { 856 #ifdef CONFIG_ALTIVEC 857 if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC))) 858 t->vrsave = mfspr(SPRN_VRSAVE); 859 #endif 860 #ifdef CONFIG_PPC_BOOK3S_64 861 if (cpu_has_feature(CPU_FTR_DSCR)) 862 t->dscr = mfspr(SPRN_DSCR); 863 864 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 865 t->bescr = mfspr(SPRN_BESCR); 866 t->ebbhr = mfspr(SPRN_EBBHR); 867 t->ebbrr = mfspr(SPRN_EBBRR); 868 869 t->fscr = mfspr(SPRN_FSCR); 870 871 /* 872 * Note that the TAR is not available for use in the kernel. 873 * (To provide this, the TAR should be backed up/restored on 874 * exception entry/exit instead, and be in pt_regs. FIXME, 875 * this should be in pt_regs anyway (for debug).) 876 */ 877 t->tar = mfspr(SPRN_TAR); 878 } 879 #endif 880 } 881 882 static inline void restore_sprs(struct thread_struct *old_thread, 883 struct thread_struct *new_thread) 884 { 885 #ifdef CONFIG_ALTIVEC 886 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 887 old_thread->vrsave != new_thread->vrsave) 888 mtspr(SPRN_VRSAVE, new_thread->vrsave); 889 #endif 890 #ifdef CONFIG_PPC_BOOK3S_64 891 if (cpu_has_feature(CPU_FTR_DSCR)) { 892 u64 dscr = get_paca()->dscr_default; 893 u64 fscr = old_thread->fscr & ~FSCR_DSCR; 894 895 if (new_thread->dscr_inherit) { 896 dscr = new_thread->dscr; 897 fscr |= FSCR_DSCR; 898 } 899 900 if (old_thread->dscr != dscr) 901 mtspr(SPRN_DSCR, dscr); 902 903 if (old_thread->fscr != fscr) 904 mtspr(SPRN_FSCR, fscr); 905 } 906 907 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 908 if (old_thread->bescr != new_thread->bescr) 909 mtspr(SPRN_BESCR, new_thread->bescr); 910 if (old_thread->ebbhr != new_thread->ebbhr) 911 mtspr(SPRN_EBBHR, new_thread->ebbhr); 912 if (old_thread->ebbrr != new_thread->ebbrr) 913 mtspr(SPRN_EBBRR, new_thread->ebbrr); 914 915 if (old_thread->tar != new_thread->tar) 916 mtspr(SPRN_TAR, new_thread->tar); 917 } 918 #endif 919 } 920 921 struct task_struct *__switch_to(struct task_struct *prev, 922 struct task_struct *new) 923 { 924 struct thread_struct *new_thread, *old_thread; 925 struct task_struct *last; 926 #ifdef CONFIG_PPC_BOOK3S_64 927 struct ppc64_tlb_batch *batch; 928 #endif 929 930 new_thread = &new->thread; 931 old_thread = ¤t->thread; 932 933 WARN_ON(!irqs_disabled()); 934 935 #ifdef CONFIG_PPC64 936 /* 937 * Collect processor utilization data per process 938 */ 939 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 940 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); 941 long unsigned start_tb, current_tb; 942 start_tb = old_thread->start_tb; 943 cu->current_tb = current_tb = mfspr(SPRN_PURR); 944 old_thread->accum_tb += (current_tb - start_tb); 945 new_thread->start_tb = current_tb; 946 } 947 #endif /* CONFIG_PPC64 */ 948 949 #ifdef CONFIG_PPC_BOOK3S_64 950 batch = this_cpu_ptr(&ppc64_tlb_batch); 951 if (batch->active) { 952 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 953 if (batch->index) 954 __flush_tlb_pending(batch); 955 batch->active = 0; 956 } 957 #endif /* CONFIG_PPC_BOOK3S_64 */ 958 959 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 960 switch_booke_debug_regs(&new->thread.debug); 961 #else 962 /* 963 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 964 * schedule DABR 965 */ 966 #ifndef CONFIG_HAVE_HW_BREAKPOINT 967 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) 968 __set_breakpoint(&new->thread.hw_brk); 969 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 970 #endif 971 972 /* 973 * We need to save SPRs before treclaim/trecheckpoint as these will 974 * change a number of them. 975 */ 976 save_sprs(&prev->thread); 977 978 __switch_to_tm(prev); 979 980 /* Save FPU, Altivec, VSX and SPE state */ 981 giveup_all(prev); 982 983 /* 984 * We can't take a PMU exception inside _switch() since there is a 985 * window where the kernel stack SLB and the kernel stack are out 986 * of sync. Hard disable here. 987 */ 988 hard_irq_disable(); 989 990 tm_recheckpoint_new_task(new); 991 992 /* 993 * Call restore_sprs() before calling _switch(). If we move it after 994 * _switch() then we miss out on calling it for new tasks. The reason 995 * for this is we manually create a stack frame for new tasks that 996 * directly returns through ret_from_fork() or 997 * ret_from_kernel_thread(). See copy_thread() for details. 998 */ 999 restore_sprs(old_thread, new_thread); 1000 1001 last = _switch(old_thread, new_thread); 1002 1003 #ifdef CONFIG_PPC_BOOK3S_64 1004 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1005 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 1006 batch = this_cpu_ptr(&ppc64_tlb_batch); 1007 batch->active = 1; 1008 } 1009 #endif /* CONFIG_PPC_BOOK3S_64 */ 1010 1011 return last; 1012 } 1013 1014 static int instructions_to_print = 16; 1015 1016 static void show_instructions(struct pt_regs *regs) 1017 { 1018 int i; 1019 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 1020 sizeof(int)); 1021 1022 printk("Instruction dump:"); 1023 1024 for (i = 0; i < instructions_to_print; i++) { 1025 int instr; 1026 1027 if (!(i % 8)) 1028 printk("\n"); 1029 1030 #if !defined(CONFIG_BOOKE) 1031 /* If executing with the IMMU off, adjust pc rather 1032 * than print XXXXXXXX. 1033 */ 1034 if (!(regs->msr & MSR_IR)) 1035 pc = (unsigned long)phys_to_virt(pc); 1036 #endif 1037 1038 if (!__kernel_text_address(pc) || 1039 probe_kernel_address((unsigned int __user *)pc, instr)) { 1040 printk(KERN_CONT "XXXXXXXX "); 1041 } else { 1042 if (regs->nip == pc) 1043 printk(KERN_CONT "<%08x> ", instr); 1044 else 1045 printk(KERN_CONT "%08x ", instr); 1046 } 1047 1048 pc += sizeof(int); 1049 } 1050 1051 printk("\n"); 1052 } 1053 1054 struct regbit { 1055 unsigned long bit; 1056 const char *name; 1057 }; 1058 1059 static struct regbit msr_bits[] = { 1060 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 1061 {MSR_SF, "SF"}, 1062 {MSR_HV, "HV"}, 1063 #endif 1064 {MSR_VEC, "VEC"}, 1065 {MSR_VSX, "VSX"}, 1066 #ifdef CONFIG_BOOKE 1067 {MSR_CE, "CE"}, 1068 #endif 1069 {MSR_EE, "EE"}, 1070 {MSR_PR, "PR"}, 1071 {MSR_FP, "FP"}, 1072 {MSR_ME, "ME"}, 1073 #ifdef CONFIG_BOOKE 1074 {MSR_DE, "DE"}, 1075 #else 1076 {MSR_SE, "SE"}, 1077 {MSR_BE, "BE"}, 1078 #endif 1079 {MSR_IR, "IR"}, 1080 {MSR_DR, "DR"}, 1081 {MSR_PMM, "PMM"}, 1082 #ifndef CONFIG_BOOKE 1083 {MSR_RI, "RI"}, 1084 {MSR_LE, "LE"}, 1085 #endif 1086 {0, NULL} 1087 }; 1088 1089 static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 1090 { 1091 const char *s = ""; 1092 1093 for (; bits->bit; ++bits) 1094 if (val & bits->bit) { 1095 printk("%s%s", s, bits->name); 1096 s = sep; 1097 } 1098 } 1099 1100 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1101 static struct regbit msr_tm_bits[] = { 1102 {MSR_TS_T, "T"}, 1103 {MSR_TS_S, "S"}, 1104 {MSR_TM, "E"}, 1105 {0, NULL} 1106 }; 1107 1108 static void print_tm_bits(unsigned long val) 1109 { 1110 /* 1111 * This only prints something if at least one of the TM bit is set. 1112 * Inside the TM[], the output means: 1113 * E: Enabled (bit 32) 1114 * S: Suspended (bit 33) 1115 * T: Transactional (bit 34) 1116 */ 1117 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1118 printk(",TM["); 1119 print_bits(val, msr_tm_bits, ""); 1120 printk("]"); 1121 } 1122 } 1123 #else 1124 static void print_tm_bits(unsigned long val) {} 1125 #endif 1126 1127 static void print_msr_bits(unsigned long val) 1128 { 1129 printk("<"); 1130 print_bits(val, msr_bits, ","); 1131 print_tm_bits(val); 1132 printk(">"); 1133 } 1134 1135 #ifdef CONFIG_PPC64 1136 #define REG "%016lx" 1137 #define REGS_PER_LINE 4 1138 #define LAST_VOLATILE 13 1139 #else 1140 #define REG "%08lx" 1141 #define REGS_PER_LINE 8 1142 #define LAST_VOLATILE 12 1143 #endif 1144 1145 void show_regs(struct pt_regs * regs) 1146 { 1147 int i, trap; 1148 1149 show_regs_print_info(KERN_DEFAULT); 1150 1151 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 1152 regs->nip, regs->link, regs->ctr); 1153 printk("REGS: %p TRAP: %04lx %s (%s)\n", 1154 regs, regs->trap, print_tainted(), init_utsname()->release); 1155 printk("MSR: "REG" ", regs->msr); 1156 print_msr_bits(regs->msr); 1157 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1158 trap = TRAP(regs); 1159 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1160 printk("CFAR: "REG" ", regs->orig_gpr3); 1161 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1162 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1163 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1164 #else 1165 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1166 #endif 1167 #ifdef CONFIG_PPC64 1168 printk("SOFTE: %ld ", regs->softe); 1169 #endif 1170 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1171 if (MSR_TM_ACTIVE(regs->msr)) 1172 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1173 #endif 1174 1175 for (i = 0; i < 32; i++) { 1176 if ((i % REGS_PER_LINE) == 0) 1177 printk("\nGPR%02d: ", i); 1178 printk(REG " ", regs->gpr[i]); 1179 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1180 break; 1181 } 1182 printk("\n"); 1183 #ifdef CONFIG_KALLSYMS 1184 /* 1185 * Lookup NIP late so we have the best change of getting the 1186 * above info out without failing 1187 */ 1188 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1189 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1190 #endif 1191 show_stack(current, (unsigned long *) regs->gpr[1]); 1192 if (!user_mode(regs)) 1193 show_instructions(regs); 1194 } 1195 1196 void exit_thread(void) 1197 { 1198 } 1199 1200 void flush_thread(void) 1201 { 1202 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1203 flush_ptrace_hw_breakpoint(current); 1204 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1205 set_debug_reg_defaults(¤t->thread); 1206 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1207 } 1208 1209 void 1210 release_thread(struct task_struct *t) 1211 { 1212 } 1213 1214 /* 1215 * this gets called so that we can store coprocessor state into memory and 1216 * copy the current task into the new thread. 1217 */ 1218 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1219 { 1220 flush_all_to_thread(src); 1221 /* 1222 * Flush TM state out so we can copy it. __switch_to_tm() does this 1223 * flush but it removes the checkpointed state from the current CPU and 1224 * transitions the CPU out of TM mode. Hence we need to call 1225 * tm_recheckpoint_new_task() (on the same task) to restore the 1226 * checkpointed state back and the TM mode. 1227 */ 1228 __switch_to_tm(src); 1229 tm_recheckpoint_new_task(src); 1230 1231 *dst = *src; 1232 1233 clear_task_ebb(dst); 1234 1235 return 0; 1236 } 1237 1238 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1239 { 1240 #ifdef CONFIG_PPC_STD_MMU_64 1241 unsigned long sp_vsid; 1242 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1243 1244 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1245 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1246 << SLB_VSID_SHIFT_1T; 1247 else 1248 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1249 << SLB_VSID_SHIFT; 1250 sp_vsid |= SLB_VSID_KERNEL | llp; 1251 p->thread.ksp_vsid = sp_vsid; 1252 #endif 1253 } 1254 1255 /* 1256 * Copy a thread.. 1257 */ 1258 1259 /* 1260 * Copy architecture-specific thread state 1261 */ 1262 int copy_thread(unsigned long clone_flags, unsigned long usp, 1263 unsigned long kthread_arg, struct task_struct *p) 1264 { 1265 struct pt_regs *childregs, *kregs; 1266 extern void ret_from_fork(void); 1267 extern void ret_from_kernel_thread(void); 1268 void (*f)(void); 1269 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1270 1271 /* Copy registers */ 1272 sp -= sizeof(struct pt_regs); 1273 childregs = (struct pt_regs *) sp; 1274 if (unlikely(p->flags & PF_KTHREAD)) { 1275 /* kernel thread */ 1276 struct thread_info *ti = (void *)task_stack_page(p); 1277 memset(childregs, 0, sizeof(struct pt_regs)); 1278 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1279 /* function */ 1280 if (usp) 1281 childregs->gpr[14] = ppc_function_entry((void *)usp); 1282 #ifdef CONFIG_PPC64 1283 clear_tsk_thread_flag(p, TIF_32BIT); 1284 childregs->softe = 1; 1285 #endif 1286 childregs->gpr[15] = kthread_arg; 1287 p->thread.regs = NULL; /* no user register state */ 1288 ti->flags |= _TIF_RESTOREALL; 1289 f = ret_from_kernel_thread; 1290 } else { 1291 /* user thread */ 1292 struct pt_regs *regs = current_pt_regs(); 1293 CHECK_FULL_REGS(regs); 1294 *childregs = *regs; 1295 if (usp) 1296 childregs->gpr[1] = usp; 1297 p->thread.regs = childregs; 1298 childregs->gpr[3] = 0; /* Result from fork() */ 1299 if (clone_flags & CLONE_SETTLS) { 1300 #ifdef CONFIG_PPC64 1301 if (!is_32bit_task()) 1302 childregs->gpr[13] = childregs->gpr[6]; 1303 else 1304 #endif 1305 childregs->gpr[2] = childregs->gpr[6]; 1306 } 1307 1308 f = ret_from_fork; 1309 } 1310 sp -= STACK_FRAME_OVERHEAD; 1311 1312 /* 1313 * The way this works is that at some point in the future 1314 * some task will call _switch to switch to the new task. 1315 * That will pop off the stack frame created below and start 1316 * the new task running at ret_from_fork. The new task will 1317 * do some house keeping and then return from the fork or clone 1318 * system call, using the stack frame created above. 1319 */ 1320 ((unsigned long *)sp)[0] = 0; 1321 sp -= sizeof(struct pt_regs); 1322 kregs = (struct pt_regs *) sp; 1323 sp -= STACK_FRAME_OVERHEAD; 1324 p->thread.ksp = sp; 1325 #ifdef CONFIG_PPC32 1326 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1327 _ALIGN_UP(sizeof(struct thread_info), 16); 1328 #endif 1329 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1330 p->thread.ptrace_bps[0] = NULL; 1331 #endif 1332 1333 p->thread.fp_save_area = NULL; 1334 #ifdef CONFIG_ALTIVEC 1335 p->thread.vr_save_area = NULL; 1336 #endif 1337 1338 setup_ksp_vsid(p, sp); 1339 1340 #ifdef CONFIG_PPC64 1341 if (cpu_has_feature(CPU_FTR_DSCR)) { 1342 p->thread.dscr_inherit = current->thread.dscr_inherit; 1343 p->thread.dscr = mfspr(SPRN_DSCR); 1344 } 1345 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1346 p->thread.ppr = INIT_PPR; 1347 #endif 1348 kregs->nip = ppc_function_entry(f); 1349 return 0; 1350 } 1351 1352 /* 1353 * Set up a thread for executing a new program 1354 */ 1355 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1356 { 1357 #ifdef CONFIG_PPC64 1358 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1359 #endif 1360 1361 /* 1362 * If we exec out of a kernel thread then thread.regs will not be 1363 * set. Do it now. 1364 */ 1365 if (!current->thread.regs) { 1366 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1367 current->thread.regs = regs - 1; 1368 } 1369 1370 memset(regs->gpr, 0, sizeof(regs->gpr)); 1371 regs->ctr = 0; 1372 regs->link = 0; 1373 regs->xer = 0; 1374 regs->ccr = 0; 1375 regs->gpr[1] = sp; 1376 1377 /* 1378 * We have just cleared all the nonvolatile GPRs, so make 1379 * FULL_REGS(regs) return true. This is necessary to allow 1380 * ptrace to examine the thread immediately after exec. 1381 */ 1382 regs->trap &= ~1UL; 1383 1384 #ifdef CONFIG_PPC32 1385 regs->mq = 0; 1386 regs->nip = start; 1387 regs->msr = MSR_USER; 1388 #else 1389 if (!is_32bit_task()) { 1390 unsigned long entry; 1391 1392 if (is_elf2_task()) { 1393 /* Look ma, no function descriptors! */ 1394 entry = start; 1395 1396 /* 1397 * Ulrich says: 1398 * The latest iteration of the ABI requires that when 1399 * calling a function (at its global entry point), 1400 * the caller must ensure r12 holds the entry point 1401 * address (so that the function can quickly 1402 * establish addressability). 1403 */ 1404 regs->gpr[12] = start; 1405 /* Make sure that's restored on entry to userspace. */ 1406 set_thread_flag(TIF_RESTOREALL); 1407 } else { 1408 unsigned long toc; 1409 1410 /* start is a relocated pointer to the function 1411 * descriptor for the elf _start routine. The first 1412 * entry in the function descriptor is the entry 1413 * address of _start and the second entry is the TOC 1414 * value we need to use. 1415 */ 1416 __get_user(entry, (unsigned long __user *)start); 1417 __get_user(toc, (unsigned long __user *)start+1); 1418 1419 /* Check whether the e_entry function descriptor entries 1420 * need to be relocated before we can use them. 1421 */ 1422 if (load_addr != 0) { 1423 entry += load_addr; 1424 toc += load_addr; 1425 } 1426 regs->gpr[2] = toc; 1427 } 1428 regs->nip = entry; 1429 regs->msr = MSR_USER64; 1430 } else { 1431 regs->nip = start; 1432 regs->gpr[2] = 0; 1433 regs->msr = MSR_USER32; 1434 } 1435 #endif 1436 #ifdef CONFIG_VSX 1437 current->thread.used_vsr = 0; 1438 #endif 1439 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1440 current->thread.fp_save_area = NULL; 1441 #ifdef CONFIG_ALTIVEC 1442 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1443 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1444 current->thread.vr_save_area = NULL; 1445 current->thread.vrsave = 0; 1446 current->thread.used_vr = 0; 1447 #endif /* CONFIG_ALTIVEC */ 1448 #ifdef CONFIG_SPE 1449 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1450 current->thread.acc = 0; 1451 current->thread.spefscr = 0; 1452 current->thread.used_spe = 0; 1453 #endif /* CONFIG_SPE */ 1454 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1455 if (cpu_has_feature(CPU_FTR_TM)) 1456 regs->msr |= MSR_TM; 1457 current->thread.tm_tfhar = 0; 1458 current->thread.tm_texasr = 0; 1459 current->thread.tm_tfiar = 0; 1460 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1461 } 1462 EXPORT_SYMBOL(start_thread); 1463 1464 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1465 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1466 1467 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1468 { 1469 struct pt_regs *regs = tsk->thread.regs; 1470 1471 /* This is a bit hairy. If we are an SPE enabled processor 1472 * (have embedded fp) we store the IEEE exception enable flags in 1473 * fpexc_mode. fpexc_mode is also used for setting FP exception 1474 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1475 if (val & PR_FP_EXC_SW_ENABLE) { 1476 #ifdef CONFIG_SPE 1477 if (cpu_has_feature(CPU_FTR_SPE)) { 1478 /* 1479 * When the sticky exception bits are set 1480 * directly by userspace, it must call prctl 1481 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1482 * in the existing prctl settings) or 1483 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1484 * the bits being set). <fenv.h> functions 1485 * saving and restoring the whole 1486 * floating-point environment need to do so 1487 * anyway to restore the prctl settings from 1488 * the saved environment. 1489 */ 1490 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1491 tsk->thread.fpexc_mode = val & 1492 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1493 return 0; 1494 } else { 1495 return -EINVAL; 1496 } 1497 #else 1498 return -EINVAL; 1499 #endif 1500 } 1501 1502 /* on a CONFIG_SPE this does not hurt us. The bits that 1503 * __pack_fe01 use do not overlap with bits used for 1504 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1505 * on CONFIG_SPE implementations are reserved so writing to 1506 * them does not change anything */ 1507 if (val > PR_FP_EXC_PRECISE) 1508 return -EINVAL; 1509 tsk->thread.fpexc_mode = __pack_fe01(val); 1510 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1511 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1512 | tsk->thread.fpexc_mode; 1513 return 0; 1514 } 1515 1516 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1517 { 1518 unsigned int val; 1519 1520 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1521 #ifdef CONFIG_SPE 1522 if (cpu_has_feature(CPU_FTR_SPE)) { 1523 /* 1524 * When the sticky exception bits are set 1525 * directly by userspace, it must call prctl 1526 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1527 * in the existing prctl settings) or 1528 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1529 * the bits being set). <fenv.h> functions 1530 * saving and restoring the whole 1531 * floating-point environment need to do so 1532 * anyway to restore the prctl settings from 1533 * the saved environment. 1534 */ 1535 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1536 val = tsk->thread.fpexc_mode; 1537 } else 1538 return -EINVAL; 1539 #else 1540 return -EINVAL; 1541 #endif 1542 else 1543 val = __unpack_fe01(tsk->thread.fpexc_mode); 1544 return put_user(val, (unsigned int __user *) adr); 1545 } 1546 1547 int set_endian(struct task_struct *tsk, unsigned int val) 1548 { 1549 struct pt_regs *regs = tsk->thread.regs; 1550 1551 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1552 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1553 return -EINVAL; 1554 1555 if (regs == NULL) 1556 return -EINVAL; 1557 1558 if (val == PR_ENDIAN_BIG) 1559 regs->msr &= ~MSR_LE; 1560 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1561 regs->msr |= MSR_LE; 1562 else 1563 return -EINVAL; 1564 1565 return 0; 1566 } 1567 1568 int get_endian(struct task_struct *tsk, unsigned long adr) 1569 { 1570 struct pt_regs *regs = tsk->thread.regs; 1571 unsigned int val; 1572 1573 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1574 !cpu_has_feature(CPU_FTR_REAL_LE)) 1575 return -EINVAL; 1576 1577 if (regs == NULL) 1578 return -EINVAL; 1579 1580 if (regs->msr & MSR_LE) { 1581 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1582 val = PR_ENDIAN_LITTLE; 1583 else 1584 val = PR_ENDIAN_PPC_LITTLE; 1585 } else 1586 val = PR_ENDIAN_BIG; 1587 1588 return put_user(val, (unsigned int __user *)adr); 1589 } 1590 1591 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1592 { 1593 tsk->thread.align_ctl = val; 1594 return 0; 1595 } 1596 1597 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1598 { 1599 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1600 } 1601 1602 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1603 unsigned long nbytes) 1604 { 1605 unsigned long stack_page; 1606 unsigned long cpu = task_cpu(p); 1607 1608 /* 1609 * Avoid crashing if the stack has overflowed and corrupted 1610 * task_cpu(p), which is in the thread_info struct. 1611 */ 1612 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1613 stack_page = (unsigned long) hardirq_ctx[cpu]; 1614 if (sp >= stack_page + sizeof(struct thread_struct) 1615 && sp <= stack_page + THREAD_SIZE - nbytes) 1616 return 1; 1617 1618 stack_page = (unsigned long) softirq_ctx[cpu]; 1619 if (sp >= stack_page + sizeof(struct thread_struct) 1620 && sp <= stack_page + THREAD_SIZE - nbytes) 1621 return 1; 1622 } 1623 return 0; 1624 } 1625 1626 int validate_sp(unsigned long sp, struct task_struct *p, 1627 unsigned long nbytes) 1628 { 1629 unsigned long stack_page = (unsigned long)task_stack_page(p); 1630 1631 if (sp >= stack_page + sizeof(struct thread_struct) 1632 && sp <= stack_page + THREAD_SIZE - nbytes) 1633 return 1; 1634 1635 return valid_irq_stack(sp, p, nbytes); 1636 } 1637 1638 EXPORT_SYMBOL(validate_sp); 1639 1640 unsigned long get_wchan(struct task_struct *p) 1641 { 1642 unsigned long ip, sp; 1643 int count = 0; 1644 1645 if (!p || p == current || p->state == TASK_RUNNING) 1646 return 0; 1647 1648 sp = p->thread.ksp; 1649 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1650 return 0; 1651 1652 do { 1653 sp = *(unsigned long *)sp; 1654 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1655 return 0; 1656 if (count > 0) { 1657 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1658 if (!in_sched_functions(ip)) 1659 return ip; 1660 } 1661 } while (count++ < 16); 1662 return 0; 1663 } 1664 1665 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1666 1667 void show_stack(struct task_struct *tsk, unsigned long *stack) 1668 { 1669 unsigned long sp, ip, lr, newsp; 1670 int count = 0; 1671 int firstframe = 1; 1672 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1673 int curr_frame = current->curr_ret_stack; 1674 extern void return_to_handler(void); 1675 unsigned long rth = (unsigned long)return_to_handler; 1676 #endif 1677 1678 sp = (unsigned long) stack; 1679 if (tsk == NULL) 1680 tsk = current; 1681 if (sp == 0) { 1682 if (tsk == current) 1683 sp = current_stack_pointer(); 1684 else 1685 sp = tsk->thread.ksp; 1686 } 1687 1688 lr = 0; 1689 printk("Call Trace:\n"); 1690 do { 1691 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1692 return; 1693 1694 stack = (unsigned long *) sp; 1695 newsp = stack[0]; 1696 ip = stack[STACK_FRAME_LR_SAVE]; 1697 if (!firstframe || ip != lr) { 1698 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1699 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1700 if ((ip == rth) && curr_frame >= 0) { 1701 printk(" (%pS)", 1702 (void *)current->ret_stack[curr_frame].ret); 1703 curr_frame--; 1704 } 1705 #endif 1706 if (firstframe) 1707 printk(" (unreliable)"); 1708 printk("\n"); 1709 } 1710 firstframe = 0; 1711 1712 /* 1713 * See if this is an exception frame. 1714 * We look for the "regshere" marker in the current frame. 1715 */ 1716 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1717 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1718 struct pt_regs *regs = (struct pt_regs *) 1719 (sp + STACK_FRAME_OVERHEAD); 1720 lr = regs->link; 1721 printk("--- interrupt: %lx at %pS\n LR = %pS\n", 1722 regs->trap, (void *)regs->nip, (void *)lr); 1723 firstframe = 1; 1724 } 1725 1726 sp = newsp; 1727 } while (count++ < kstack_depth_to_print); 1728 } 1729 1730 #ifdef CONFIG_PPC64 1731 /* Called with hard IRQs off */ 1732 void notrace __ppc64_runlatch_on(void) 1733 { 1734 struct thread_info *ti = current_thread_info(); 1735 unsigned long ctrl; 1736 1737 ctrl = mfspr(SPRN_CTRLF); 1738 ctrl |= CTRL_RUNLATCH; 1739 mtspr(SPRN_CTRLT, ctrl); 1740 1741 ti->local_flags |= _TLF_RUNLATCH; 1742 } 1743 1744 /* Called with hard IRQs off */ 1745 void notrace __ppc64_runlatch_off(void) 1746 { 1747 struct thread_info *ti = current_thread_info(); 1748 unsigned long ctrl; 1749 1750 ti->local_flags &= ~_TLF_RUNLATCH; 1751 1752 ctrl = mfspr(SPRN_CTRLF); 1753 ctrl &= ~CTRL_RUNLATCH; 1754 mtspr(SPRN_CTRLT, ctrl); 1755 } 1756 #endif /* CONFIG_PPC64 */ 1757 1758 unsigned long arch_align_stack(unsigned long sp) 1759 { 1760 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1761 sp -= get_random_int() & ~PAGE_MASK; 1762 return sp & ~0xf; 1763 } 1764 1765 static inline unsigned long brk_rnd(void) 1766 { 1767 unsigned long rnd = 0; 1768 1769 /* 8MB for 32bit, 1GB for 64bit */ 1770 if (is_32bit_task()) 1771 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); 1772 else 1773 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); 1774 1775 return rnd << PAGE_SHIFT; 1776 } 1777 1778 unsigned long arch_randomize_brk(struct mm_struct *mm) 1779 { 1780 unsigned long base = mm->brk; 1781 unsigned long ret; 1782 1783 #ifdef CONFIG_PPC_STD_MMU_64 1784 /* 1785 * If we are using 1TB segments and we are allowed to randomise 1786 * the heap, we can put it above 1TB so it is backed by a 1TB 1787 * segment. Otherwise the heap will be in the bottom 1TB 1788 * which always uses 256MB segments and this may result in a 1789 * performance penalty. 1790 */ 1791 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1792 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1793 #endif 1794 1795 ret = PAGE_ALIGN(base + brk_rnd()); 1796 1797 if (ret < mm->brk) 1798 return mm->brk; 1799 1800 return ret; 1801 } 1802 1803