1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/init.h> 29 #include <linux/prctl.h> 30 #include <linux/init_task.h> 31 #include <linux/export.h> 32 #include <linux/kallsyms.h> 33 #include <linux/mqueue.h> 34 #include <linux/hardirq.h> 35 #include <linux/utsname.h> 36 #include <linux/ftrace.h> 37 #include <linux/kernel_stat.h> 38 #include <linux/personality.h> 39 #include <linux/random.h> 40 #include <linux/hw_breakpoint.h> 41 42 #include <asm/pgtable.h> 43 #include <asm/uaccess.h> 44 #include <asm/io.h> 45 #include <asm/processor.h> 46 #include <asm/mmu.h> 47 #include <asm/prom.h> 48 #include <asm/machdep.h> 49 #include <asm/time.h> 50 #include <asm/runlatch.h> 51 #include <asm/syscalls.h> 52 #include <asm/switch_to.h> 53 #include <asm/tm.h> 54 #include <asm/debug.h> 55 #ifdef CONFIG_PPC64 56 #include <asm/firmware.h> 57 #endif 58 #include <linux/kprobes.h> 59 #include <linux/kdebug.h> 60 61 /* Transactional Memory debug */ 62 #ifdef TM_DEBUG_SW 63 #define TM_DEBUG(x...) printk(KERN_INFO x) 64 #else 65 #define TM_DEBUG(x...) do { } while(0) 66 #endif 67 68 extern unsigned long _get_SP(void); 69 70 #ifndef CONFIG_SMP 71 struct task_struct *last_task_used_math = NULL; 72 struct task_struct *last_task_used_altivec = NULL; 73 struct task_struct *last_task_used_vsx = NULL; 74 struct task_struct *last_task_used_spe = NULL; 75 #endif 76 77 /* 78 * Make sure the floating-point register state in the 79 * the thread_struct is up to date for task tsk. 80 */ 81 void flush_fp_to_thread(struct task_struct *tsk) 82 { 83 if (tsk->thread.regs) { 84 /* 85 * We need to disable preemption here because if we didn't, 86 * another process could get scheduled after the regs->msr 87 * test but before we have finished saving the FP registers 88 * to the thread_struct. That process could take over the 89 * FPU, and then when we get scheduled again we would store 90 * bogus values for the remaining FP registers. 91 */ 92 preempt_disable(); 93 if (tsk->thread.regs->msr & MSR_FP) { 94 #ifdef CONFIG_SMP 95 /* 96 * This should only ever be called for current or 97 * for a stopped child process. Since we save away 98 * the FP register state on context switch on SMP, 99 * there is something wrong if a stopped child appears 100 * to still have its FP state in the CPU registers. 101 */ 102 BUG_ON(tsk != current); 103 #endif 104 giveup_fpu(tsk); 105 } 106 preempt_enable(); 107 } 108 } 109 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 110 111 void enable_kernel_fp(void) 112 { 113 WARN_ON(preemptible()); 114 115 #ifdef CONFIG_SMP 116 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) 117 giveup_fpu(current); 118 else 119 giveup_fpu(NULL); /* just enables FP for kernel */ 120 #else 121 giveup_fpu(last_task_used_math); 122 #endif /* CONFIG_SMP */ 123 } 124 EXPORT_SYMBOL(enable_kernel_fp); 125 126 #ifdef CONFIG_ALTIVEC 127 void enable_kernel_altivec(void) 128 { 129 WARN_ON(preemptible()); 130 131 #ifdef CONFIG_SMP 132 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) 133 giveup_altivec(current); 134 else 135 giveup_altivec_notask(); 136 #else 137 giveup_altivec(last_task_used_altivec); 138 #endif /* CONFIG_SMP */ 139 } 140 EXPORT_SYMBOL(enable_kernel_altivec); 141 142 /* 143 * Make sure the VMX/Altivec register state in the 144 * the thread_struct is up to date for task tsk. 145 */ 146 void flush_altivec_to_thread(struct task_struct *tsk) 147 { 148 if (tsk->thread.regs) { 149 preempt_disable(); 150 if (tsk->thread.regs->msr & MSR_VEC) { 151 #ifdef CONFIG_SMP 152 BUG_ON(tsk != current); 153 #endif 154 giveup_altivec(tsk); 155 } 156 preempt_enable(); 157 } 158 } 159 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 160 #endif /* CONFIG_ALTIVEC */ 161 162 #ifdef CONFIG_VSX 163 #if 0 164 /* not currently used, but some crazy RAID module might want to later */ 165 void enable_kernel_vsx(void) 166 { 167 WARN_ON(preemptible()); 168 169 #ifdef CONFIG_SMP 170 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) 171 giveup_vsx(current); 172 else 173 giveup_vsx(NULL); /* just enable vsx for kernel - force */ 174 #else 175 giveup_vsx(last_task_used_vsx); 176 #endif /* CONFIG_SMP */ 177 } 178 EXPORT_SYMBOL(enable_kernel_vsx); 179 #endif 180 181 void giveup_vsx(struct task_struct *tsk) 182 { 183 giveup_fpu(tsk); 184 giveup_altivec(tsk); 185 __giveup_vsx(tsk); 186 } 187 188 void flush_vsx_to_thread(struct task_struct *tsk) 189 { 190 if (tsk->thread.regs) { 191 preempt_disable(); 192 if (tsk->thread.regs->msr & MSR_VSX) { 193 #ifdef CONFIG_SMP 194 BUG_ON(tsk != current); 195 #endif 196 giveup_vsx(tsk); 197 } 198 preempt_enable(); 199 } 200 } 201 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 202 #endif /* CONFIG_VSX */ 203 204 #ifdef CONFIG_SPE 205 206 void enable_kernel_spe(void) 207 { 208 WARN_ON(preemptible()); 209 210 #ifdef CONFIG_SMP 211 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) 212 giveup_spe(current); 213 else 214 giveup_spe(NULL); /* just enable SPE for kernel - force */ 215 #else 216 giveup_spe(last_task_used_spe); 217 #endif /* __SMP __ */ 218 } 219 EXPORT_SYMBOL(enable_kernel_spe); 220 221 void flush_spe_to_thread(struct task_struct *tsk) 222 { 223 if (tsk->thread.regs) { 224 preempt_disable(); 225 if (tsk->thread.regs->msr & MSR_SPE) { 226 #ifdef CONFIG_SMP 227 BUG_ON(tsk != current); 228 #endif 229 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 230 giveup_spe(tsk); 231 } 232 preempt_enable(); 233 } 234 } 235 #endif /* CONFIG_SPE */ 236 237 #ifndef CONFIG_SMP 238 /* 239 * If we are doing lazy switching of CPU state (FP, altivec or SPE), 240 * and the current task has some state, discard it. 241 */ 242 void discard_lazy_cpu_state(void) 243 { 244 preempt_disable(); 245 if (last_task_used_math == current) 246 last_task_used_math = NULL; 247 #ifdef CONFIG_ALTIVEC 248 if (last_task_used_altivec == current) 249 last_task_used_altivec = NULL; 250 #endif /* CONFIG_ALTIVEC */ 251 #ifdef CONFIG_VSX 252 if (last_task_used_vsx == current) 253 last_task_used_vsx = NULL; 254 #endif /* CONFIG_VSX */ 255 #ifdef CONFIG_SPE 256 if (last_task_used_spe == current) 257 last_task_used_spe = NULL; 258 #endif 259 preempt_enable(); 260 } 261 #endif /* CONFIG_SMP */ 262 263 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 264 void do_send_trap(struct pt_regs *regs, unsigned long address, 265 unsigned long error_code, int signal_code, int breakpt) 266 { 267 siginfo_t info; 268 269 current->thread.trap_nr = signal_code; 270 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 271 11, SIGSEGV) == NOTIFY_STOP) 272 return; 273 274 /* Deliver the signal to userspace */ 275 info.si_signo = SIGTRAP; 276 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 277 info.si_code = signal_code; 278 info.si_addr = (void __user *)address; 279 force_sig_info(SIGTRAP, &info, current); 280 } 281 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 282 void do_break (struct pt_regs *regs, unsigned long address, 283 unsigned long error_code) 284 { 285 siginfo_t info; 286 287 current->thread.trap_nr = TRAP_HWBKPT; 288 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 289 11, SIGSEGV) == NOTIFY_STOP) 290 return; 291 292 if (debugger_break_match(regs)) 293 return; 294 295 /* Clear the breakpoint */ 296 hw_breakpoint_disable(); 297 298 /* Deliver the signal to userspace */ 299 info.si_signo = SIGTRAP; 300 info.si_errno = 0; 301 info.si_code = TRAP_HWBKPT; 302 info.si_addr = (void __user *)address; 303 force_sig_info(SIGTRAP, &info, current); 304 } 305 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 306 307 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 308 309 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 310 /* 311 * Set the debug registers back to their default "safe" values. 312 */ 313 static void set_debug_reg_defaults(struct thread_struct *thread) 314 { 315 thread->iac1 = thread->iac2 = 0; 316 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 317 thread->iac3 = thread->iac4 = 0; 318 #endif 319 thread->dac1 = thread->dac2 = 0; 320 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 321 thread->dvc1 = thread->dvc2 = 0; 322 #endif 323 thread->dbcr0 = 0; 324 #ifdef CONFIG_BOOKE 325 /* 326 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 327 */ 328 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \ 329 DBCR1_IAC3US | DBCR1_IAC4US; 330 /* 331 * Force Data Address Compare User/Supervisor bits to be User-only 332 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 333 */ 334 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 335 #else 336 thread->dbcr1 = 0; 337 #endif 338 } 339 340 static void prime_debug_regs(struct thread_struct *thread) 341 { 342 mtspr(SPRN_IAC1, thread->iac1); 343 mtspr(SPRN_IAC2, thread->iac2); 344 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 345 mtspr(SPRN_IAC3, thread->iac3); 346 mtspr(SPRN_IAC4, thread->iac4); 347 #endif 348 mtspr(SPRN_DAC1, thread->dac1); 349 mtspr(SPRN_DAC2, thread->dac2); 350 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 351 mtspr(SPRN_DVC1, thread->dvc1); 352 mtspr(SPRN_DVC2, thread->dvc2); 353 #endif 354 mtspr(SPRN_DBCR0, thread->dbcr0); 355 mtspr(SPRN_DBCR1, thread->dbcr1); 356 #ifdef CONFIG_BOOKE 357 mtspr(SPRN_DBCR2, thread->dbcr2); 358 #endif 359 } 360 /* 361 * Unless neither the old or new thread are making use of the 362 * debug registers, set the debug registers from the values 363 * stored in the new thread. 364 */ 365 static void switch_booke_debug_regs(struct thread_struct *new_thread) 366 { 367 if ((current->thread.dbcr0 & DBCR0_IDM) 368 || (new_thread->dbcr0 & DBCR0_IDM)) 369 prime_debug_regs(new_thread); 370 } 371 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 372 #ifndef CONFIG_HAVE_HW_BREAKPOINT 373 static void set_debug_reg_defaults(struct thread_struct *thread) 374 { 375 thread->hw_brk.address = 0; 376 thread->hw_brk.type = 0; 377 set_breakpoint(&thread->hw_brk); 378 } 379 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 380 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 381 382 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 383 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 384 { 385 mtspr(SPRN_DAC1, dabr); 386 #ifdef CONFIG_PPC_47x 387 isync(); 388 #endif 389 return 0; 390 } 391 #elif defined(CONFIG_PPC_BOOK3S) 392 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 393 { 394 mtspr(SPRN_DABR, dabr); 395 mtspr(SPRN_DABRX, dabrx); 396 return 0; 397 } 398 #else 399 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 400 { 401 return -EINVAL; 402 } 403 #endif 404 405 static inline int set_dabr(struct arch_hw_breakpoint *brk) 406 { 407 unsigned long dabr, dabrx; 408 409 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 410 dabrx = ((brk->type >> 3) & 0x7); 411 412 if (ppc_md.set_dabr) 413 return ppc_md.set_dabr(dabr, dabrx); 414 415 return __set_dabr(dabr, dabrx); 416 } 417 418 static inline int set_dawr(struct arch_hw_breakpoint *brk) 419 { 420 unsigned long dawr, dawrx, mrd; 421 422 dawr = brk->address; 423 424 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 425 << (63 - 58); //* read/write bits */ 426 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 427 << (63 - 59); //* translate */ 428 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 429 >> 3; //* PRIM bits */ 430 /* dawr length is stored in field MDR bits 48:53. Matches range in 431 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 432 0b111111=64DW. 433 brk->len is in bytes. 434 This aligns up to double word size, shifts and does the bias. 435 */ 436 mrd = ((brk->len + 7) >> 3) - 1; 437 dawrx |= (mrd & 0x3f) << (63 - 53); 438 439 if (ppc_md.set_dawr) 440 return ppc_md.set_dawr(dawr, dawrx); 441 mtspr(SPRN_DAWR, dawr); 442 mtspr(SPRN_DAWRX, dawrx); 443 return 0; 444 } 445 446 int set_breakpoint(struct arch_hw_breakpoint *brk) 447 { 448 __get_cpu_var(current_brk) = *brk; 449 450 if (cpu_has_feature(CPU_FTR_DAWR)) 451 return set_dawr(brk); 452 453 return set_dabr(brk); 454 } 455 456 #ifdef CONFIG_PPC64 457 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 458 #endif 459 460 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 461 struct arch_hw_breakpoint *b) 462 { 463 if (a->address != b->address) 464 return false; 465 if (a->type != b->type) 466 return false; 467 if (a->len != b->len) 468 return false; 469 return true; 470 } 471 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 472 static inline void tm_reclaim_task(struct task_struct *tsk) 473 { 474 /* We have to work out if we're switching from/to a task that's in the 475 * middle of a transaction. 476 * 477 * In switching we need to maintain a 2nd register state as 478 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 479 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 480 * (current) FPRs into oldtask->thread.transact_fpr[]. 481 * 482 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 483 */ 484 struct thread_struct *thr = &tsk->thread; 485 486 if (!thr->regs) 487 return; 488 489 if (!MSR_TM_ACTIVE(thr->regs->msr)) 490 goto out_and_saveregs; 491 492 /* Stash the original thread MSR, as giveup_fpu et al will 493 * modify it. We hold onto it to see whether the task used 494 * FP & vector regs. 495 */ 496 thr->tm_orig_msr = thr->regs->msr; 497 498 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 499 "ccr=%lx, msr=%lx, trap=%lx)\n", 500 tsk->pid, thr->regs->nip, 501 thr->regs->ccr, thr->regs->msr, 502 thr->regs->trap); 503 504 tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED); 505 506 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 507 tsk->pid); 508 509 out_and_saveregs: 510 /* Always save the regs here, even if a transaction's not active. 511 * This context-switches a thread's TM info SPRs. We do it here to 512 * be consistent with the restore path (in recheckpoint) which 513 * cannot happen later in _switch(). 514 */ 515 tm_save_sprs(thr); 516 } 517 518 static inline void tm_recheckpoint_new_task(struct task_struct *new) 519 { 520 unsigned long msr; 521 522 if (!cpu_has_feature(CPU_FTR_TM)) 523 return; 524 525 /* Recheckpoint the registers of the thread we're about to switch to. 526 * 527 * If the task was using FP, we non-lazily reload both the original and 528 * the speculative FP register states. This is because the kernel 529 * doesn't see if/when a TM rollback occurs, so if we take an FP 530 * unavoidable later, we are unable to determine which set of FP regs 531 * need to be restored. 532 */ 533 if (!new->thread.regs) 534 return; 535 536 /* The TM SPRs are restored here, so that TEXASR.FS can be set 537 * before the trecheckpoint and no explosion occurs. 538 */ 539 tm_restore_sprs(&new->thread); 540 541 if (!MSR_TM_ACTIVE(new->thread.regs->msr)) 542 return; 543 msr = new->thread.tm_orig_msr; 544 /* Recheckpoint to restore original checkpointed register state. */ 545 TM_DEBUG("*** tm_recheckpoint of pid %d " 546 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 547 new->pid, new->thread.regs->msr, msr); 548 549 /* This loads the checkpointed FP/VEC state, if used */ 550 tm_recheckpoint(&new->thread, msr); 551 552 /* This loads the speculative FP/VEC state, if used */ 553 if (msr & MSR_FP) { 554 do_load_up_transact_fpu(&new->thread); 555 new->thread.regs->msr |= 556 (MSR_FP | new->thread.fpexc_mode); 557 } 558 if (msr & MSR_VEC) { 559 do_load_up_transact_altivec(&new->thread); 560 new->thread.regs->msr |= MSR_VEC; 561 } 562 /* We may as well turn on VSX too since all the state is restored now */ 563 if (msr & MSR_VSX) 564 new->thread.regs->msr |= MSR_VSX; 565 566 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 567 "(kernel msr 0x%lx)\n", 568 new->pid, mfmsr()); 569 } 570 571 static inline void __switch_to_tm(struct task_struct *prev) 572 { 573 if (cpu_has_feature(CPU_FTR_TM)) { 574 tm_enable(); 575 tm_reclaim_task(prev); 576 } 577 } 578 #else 579 #define tm_recheckpoint_new_task(new) 580 #define __switch_to_tm(prev) 581 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 582 583 struct task_struct *__switch_to(struct task_struct *prev, 584 struct task_struct *new) 585 { 586 struct thread_struct *new_thread, *old_thread; 587 unsigned long flags; 588 struct task_struct *last; 589 #ifdef CONFIG_PPC_BOOK3S_64 590 struct ppc64_tlb_batch *batch; 591 #endif 592 593 __switch_to_tm(prev); 594 595 #ifdef CONFIG_SMP 596 /* avoid complexity of lazy save/restore of fpu 597 * by just saving it every time we switch out if 598 * this task used the fpu during the last quantum. 599 * 600 * If it tries to use the fpu again, it'll trap and 601 * reload its fp regs. So we don't have to do a restore 602 * every switch, just a save. 603 * -- Cort 604 */ 605 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) 606 giveup_fpu(prev); 607 #ifdef CONFIG_ALTIVEC 608 /* 609 * If the previous thread used altivec in the last quantum 610 * (thus changing altivec regs) then save them. 611 * We used to check the VRSAVE register but not all apps 612 * set it, so we don't rely on it now (and in fact we need 613 * to save & restore VSCR even if VRSAVE == 0). -- paulus 614 * 615 * On SMP we always save/restore altivec regs just to avoid the 616 * complexity of changing processors. 617 * -- Cort 618 */ 619 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) 620 giveup_altivec(prev); 621 #endif /* CONFIG_ALTIVEC */ 622 #ifdef CONFIG_VSX 623 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) 624 /* VMX and FPU registers are already save here */ 625 __giveup_vsx(prev); 626 #endif /* CONFIG_VSX */ 627 #ifdef CONFIG_SPE 628 /* 629 * If the previous thread used spe in the last quantum 630 * (thus changing spe regs) then save them. 631 * 632 * On SMP we always save/restore spe regs just to avoid the 633 * complexity of changing processors. 634 */ 635 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) 636 giveup_spe(prev); 637 #endif /* CONFIG_SPE */ 638 639 #else /* CONFIG_SMP */ 640 #ifdef CONFIG_ALTIVEC 641 /* Avoid the trap. On smp this this never happens since 642 * we don't set last_task_used_altivec -- Cort 643 */ 644 if (new->thread.regs && last_task_used_altivec == new) 645 new->thread.regs->msr |= MSR_VEC; 646 #endif /* CONFIG_ALTIVEC */ 647 #ifdef CONFIG_VSX 648 if (new->thread.regs && last_task_used_vsx == new) 649 new->thread.regs->msr |= MSR_VSX; 650 #endif /* CONFIG_VSX */ 651 #ifdef CONFIG_SPE 652 /* Avoid the trap. On smp this this never happens since 653 * we don't set last_task_used_spe 654 */ 655 if (new->thread.regs && last_task_used_spe == new) 656 new->thread.regs->msr |= MSR_SPE; 657 #endif /* CONFIG_SPE */ 658 659 #endif /* CONFIG_SMP */ 660 661 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 662 switch_booke_debug_regs(&new->thread); 663 #else 664 /* 665 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 666 * schedule DABR 667 */ 668 #ifndef CONFIG_HAVE_HW_BREAKPOINT 669 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) 670 set_breakpoint(&new->thread.hw_brk); 671 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 672 #endif 673 674 675 new_thread = &new->thread; 676 old_thread = ¤t->thread; 677 678 #ifdef CONFIG_PPC64 679 /* 680 * Collect processor utilization data per process 681 */ 682 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 683 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); 684 long unsigned start_tb, current_tb; 685 start_tb = old_thread->start_tb; 686 cu->current_tb = current_tb = mfspr(SPRN_PURR); 687 old_thread->accum_tb += (current_tb - start_tb); 688 new_thread->start_tb = current_tb; 689 } 690 #endif /* CONFIG_PPC64 */ 691 692 #ifdef CONFIG_PPC_BOOK3S_64 693 batch = &__get_cpu_var(ppc64_tlb_batch); 694 if (batch->active) { 695 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 696 if (batch->index) 697 __flush_tlb_pending(batch); 698 batch->active = 0; 699 } 700 #endif /* CONFIG_PPC_BOOK3S_64 */ 701 702 local_irq_save(flags); 703 704 /* 705 * We can't take a PMU exception inside _switch() since there is a 706 * window where the kernel stack SLB and the kernel stack are out 707 * of sync. Hard disable here. 708 */ 709 hard_irq_disable(); 710 711 tm_recheckpoint_new_task(new); 712 713 last = _switch(old_thread, new_thread); 714 715 #ifdef CONFIG_PPC_BOOK3S_64 716 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 717 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 718 batch = &__get_cpu_var(ppc64_tlb_batch); 719 batch->active = 1; 720 } 721 #endif /* CONFIG_PPC_BOOK3S_64 */ 722 723 local_irq_restore(flags); 724 725 return last; 726 } 727 728 static int instructions_to_print = 16; 729 730 static void show_instructions(struct pt_regs *regs) 731 { 732 int i; 733 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 734 sizeof(int)); 735 736 printk("Instruction dump:"); 737 738 for (i = 0; i < instructions_to_print; i++) { 739 int instr; 740 741 if (!(i % 8)) 742 printk("\n"); 743 744 #if !defined(CONFIG_BOOKE) 745 /* If executing with the IMMU off, adjust pc rather 746 * than print XXXXXXXX. 747 */ 748 if (!(regs->msr & MSR_IR)) 749 pc = (unsigned long)phys_to_virt(pc); 750 #endif 751 752 /* We use __get_user here *only* to avoid an OOPS on a 753 * bad address because the pc *should* only be a 754 * kernel address. 755 */ 756 if (!__kernel_text_address(pc) || 757 __get_user(instr, (unsigned int __user *)pc)) { 758 printk(KERN_CONT "XXXXXXXX "); 759 } else { 760 if (regs->nip == pc) 761 printk(KERN_CONT "<%08x> ", instr); 762 else 763 printk(KERN_CONT "%08x ", instr); 764 } 765 766 pc += sizeof(int); 767 } 768 769 printk("\n"); 770 } 771 772 static struct regbit { 773 unsigned long bit; 774 const char *name; 775 } msr_bits[] = { 776 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 777 {MSR_SF, "SF"}, 778 {MSR_HV, "HV"}, 779 #endif 780 {MSR_VEC, "VEC"}, 781 {MSR_VSX, "VSX"}, 782 #ifdef CONFIG_BOOKE 783 {MSR_CE, "CE"}, 784 #endif 785 {MSR_EE, "EE"}, 786 {MSR_PR, "PR"}, 787 {MSR_FP, "FP"}, 788 {MSR_ME, "ME"}, 789 #ifdef CONFIG_BOOKE 790 {MSR_DE, "DE"}, 791 #else 792 {MSR_SE, "SE"}, 793 {MSR_BE, "BE"}, 794 #endif 795 {MSR_IR, "IR"}, 796 {MSR_DR, "DR"}, 797 {MSR_PMM, "PMM"}, 798 #ifndef CONFIG_BOOKE 799 {MSR_RI, "RI"}, 800 {MSR_LE, "LE"}, 801 #endif 802 {0, NULL} 803 }; 804 805 static void printbits(unsigned long val, struct regbit *bits) 806 { 807 const char *sep = ""; 808 809 printk("<"); 810 for (; bits->bit; ++bits) 811 if (val & bits->bit) { 812 printk("%s%s", sep, bits->name); 813 sep = ","; 814 } 815 printk(">"); 816 } 817 818 #ifdef CONFIG_PPC64 819 #define REG "%016lx" 820 #define REGS_PER_LINE 4 821 #define LAST_VOLATILE 13 822 #else 823 #define REG "%08lx" 824 #define REGS_PER_LINE 8 825 #define LAST_VOLATILE 12 826 #endif 827 828 void show_regs(struct pt_regs * regs) 829 { 830 int i, trap; 831 832 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 833 regs->nip, regs->link, regs->ctr); 834 printk("REGS: %p TRAP: %04lx %s (%s)\n", 835 regs, regs->trap, print_tainted(), init_utsname()->release); 836 printk("MSR: "REG" ", regs->msr); 837 printbits(regs->msr, msr_bits); 838 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 839 #ifdef CONFIG_PPC64 840 printk("SOFTE: %ld\n", regs->softe); 841 #endif 842 trap = TRAP(regs); 843 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 844 printk("CFAR: "REG"\n", regs->orig_gpr3); 845 if (trap == 0x300 || trap == 0x600) 846 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 847 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr); 848 #else 849 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr); 850 #endif 851 printk("TASK = %p[%d] '%s' THREAD: %p", 852 current, task_pid_nr(current), current->comm, task_thread_info(current)); 853 854 #ifdef CONFIG_SMP 855 printk(" CPU: %d", raw_smp_processor_id()); 856 #endif /* CONFIG_SMP */ 857 858 for (i = 0; i < 32; i++) { 859 if ((i % REGS_PER_LINE) == 0) 860 printk("\nGPR%02d: ", i); 861 printk(REG " ", regs->gpr[i]); 862 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 863 break; 864 } 865 printk("\n"); 866 #ifdef CONFIG_KALLSYMS 867 /* 868 * Lookup NIP late so we have the best change of getting the 869 * above info out without failing 870 */ 871 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 872 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 873 #endif 874 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 875 printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch); 876 #endif 877 show_stack(current, (unsigned long *) regs->gpr[1]); 878 if (!user_mode(regs)) 879 show_instructions(regs); 880 } 881 882 void exit_thread(void) 883 { 884 discard_lazy_cpu_state(); 885 } 886 887 void flush_thread(void) 888 { 889 discard_lazy_cpu_state(); 890 891 #ifdef CONFIG_HAVE_HW_BREAKPOINT 892 flush_ptrace_hw_breakpoint(current); 893 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 894 set_debug_reg_defaults(¤t->thread); 895 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 896 } 897 898 void 899 release_thread(struct task_struct *t) 900 { 901 } 902 903 /* 904 * this gets called so that we can store coprocessor state into memory and 905 * copy the current task into the new thread. 906 */ 907 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 908 { 909 flush_fp_to_thread(src); 910 flush_altivec_to_thread(src); 911 flush_vsx_to_thread(src); 912 flush_spe_to_thread(src); 913 #ifdef CONFIG_HAVE_HW_BREAKPOINT 914 flush_ptrace_hw_breakpoint(src); 915 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 916 917 *dst = *src; 918 return 0; 919 } 920 921 /* 922 * Copy a thread.. 923 */ 924 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */ 925 926 int copy_thread(unsigned long clone_flags, unsigned long usp, 927 unsigned long arg, struct task_struct *p) 928 { 929 struct pt_regs *childregs, *kregs; 930 extern void ret_from_fork(void); 931 extern void ret_from_kernel_thread(void); 932 void (*f)(void); 933 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 934 935 /* Copy registers */ 936 sp -= sizeof(struct pt_regs); 937 childregs = (struct pt_regs *) sp; 938 if (unlikely(p->flags & PF_KTHREAD)) { 939 struct thread_info *ti = (void *)task_stack_page(p); 940 memset(childregs, 0, sizeof(struct pt_regs)); 941 childregs->gpr[1] = sp + sizeof(struct pt_regs); 942 childregs->gpr[14] = usp; /* function */ 943 #ifdef CONFIG_PPC64 944 clear_tsk_thread_flag(p, TIF_32BIT); 945 childregs->softe = 1; 946 #endif 947 childregs->gpr[15] = arg; 948 p->thread.regs = NULL; /* no user register state */ 949 ti->flags |= _TIF_RESTOREALL; 950 f = ret_from_kernel_thread; 951 } else { 952 struct pt_regs *regs = current_pt_regs(); 953 CHECK_FULL_REGS(regs); 954 *childregs = *regs; 955 if (usp) 956 childregs->gpr[1] = usp; 957 p->thread.regs = childregs; 958 childregs->gpr[3] = 0; /* Result from fork() */ 959 if (clone_flags & CLONE_SETTLS) { 960 #ifdef CONFIG_PPC64 961 if (!is_32bit_task()) 962 childregs->gpr[13] = childregs->gpr[6]; 963 else 964 #endif 965 childregs->gpr[2] = childregs->gpr[6]; 966 } 967 968 f = ret_from_fork; 969 } 970 sp -= STACK_FRAME_OVERHEAD; 971 972 /* 973 * The way this works is that at some point in the future 974 * some task will call _switch to switch to the new task. 975 * That will pop off the stack frame created below and start 976 * the new task running at ret_from_fork. The new task will 977 * do some house keeping and then return from the fork or clone 978 * system call, using the stack frame created above. 979 */ 980 sp -= sizeof(struct pt_regs); 981 kregs = (struct pt_regs *) sp; 982 sp -= STACK_FRAME_OVERHEAD; 983 p->thread.ksp = sp; 984 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 985 _ALIGN_UP(sizeof(struct thread_info), 16); 986 987 #ifdef CONFIG_PPC_STD_MMU_64 988 if (mmu_has_feature(MMU_FTR_SLB)) { 989 unsigned long sp_vsid; 990 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 991 992 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 993 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 994 << SLB_VSID_SHIFT_1T; 995 else 996 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 997 << SLB_VSID_SHIFT; 998 sp_vsid |= SLB_VSID_KERNEL | llp; 999 p->thread.ksp_vsid = sp_vsid; 1000 } 1001 #endif /* CONFIG_PPC_STD_MMU_64 */ 1002 #ifdef CONFIG_PPC64 1003 if (cpu_has_feature(CPU_FTR_DSCR)) { 1004 p->thread.dscr_inherit = current->thread.dscr_inherit; 1005 p->thread.dscr = current->thread.dscr; 1006 } 1007 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1008 p->thread.ppr = INIT_PPR; 1009 #endif 1010 /* 1011 * The PPC64 ABI makes use of a TOC to contain function 1012 * pointers. The function (ret_from_except) is actually a pointer 1013 * to the TOC entry. The first entry is a pointer to the actual 1014 * function. 1015 */ 1016 #ifdef CONFIG_PPC64 1017 kregs->nip = *((unsigned long *)f); 1018 #else 1019 kregs->nip = (unsigned long)f; 1020 #endif 1021 return 0; 1022 } 1023 1024 /* 1025 * Set up a thread for executing a new program 1026 */ 1027 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1028 { 1029 #ifdef CONFIG_PPC64 1030 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1031 #endif 1032 1033 /* 1034 * If we exec out of a kernel thread then thread.regs will not be 1035 * set. Do it now. 1036 */ 1037 if (!current->thread.regs) { 1038 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1039 current->thread.regs = regs - 1; 1040 } 1041 1042 memset(regs->gpr, 0, sizeof(regs->gpr)); 1043 regs->ctr = 0; 1044 regs->link = 0; 1045 regs->xer = 0; 1046 regs->ccr = 0; 1047 regs->gpr[1] = sp; 1048 1049 /* 1050 * We have just cleared all the nonvolatile GPRs, so make 1051 * FULL_REGS(regs) return true. This is necessary to allow 1052 * ptrace to examine the thread immediately after exec. 1053 */ 1054 regs->trap &= ~1UL; 1055 1056 #ifdef CONFIG_PPC32 1057 regs->mq = 0; 1058 regs->nip = start; 1059 regs->msr = MSR_USER; 1060 #else 1061 if (!is_32bit_task()) { 1062 unsigned long entry, toc; 1063 1064 /* start is a relocated pointer to the function descriptor for 1065 * the elf _start routine. The first entry in the function 1066 * descriptor is the entry address of _start and the second 1067 * entry is the TOC value we need to use. 1068 */ 1069 __get_user(entry, (unsigned long __user *)start); 1070 __get_user(toc, (unsigned long __user *)start+1); 1071 1072 /* Check whether the e_entry function descriptor entries 1073 * need to be relocated before we can use them. 1074 */ 1075 if (load_addr != 0) { 1076 entry += load_addr; 1077 toc += load_addr; 1078 } 1079 regs->nip = entry; 1080 regs->gpr[2] = toc; 1081 regs->msr = MSR_USER64; 1082 } else { 1083 regs->nip = start; 1084 regs->gpr[2] = 0; 1085 regs->msr = MSR_USER32; 1086 } 1087 #endif 1088 discard_lazy_cpu_state(); 1089 #ifdef CONFIG_VSX 1090 current->thread.used_vsr = 0; 1091 #endif 1092 memset(current->thread.fpr, 0, sizeof(current->thread.fpr)); 1093 current->thread.fpscr.val = 0; 1094 #ifdef CONFIG_ALTIVEC 1095 memset(current->thread.vr, 0, sizeof(current->thread.vr)); 1096 memset(¤t->thread.vscr, 0, sizeof(current->thread.vscr)); 1097 current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1098 current->thread.vrsave = 0; 1099 current->thread.used_vr = 0; 1100 #endif /* CONFIG_ALTIVEC */ 1101 #ifdef CONFIG_SPE 1102 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1103 current->thread.acc = 0; 1104 current->thread.spefscr = 0; 1105 current->thread.used_spe = 0; 1106 #endif /* CONFIG_SPE */ 1107 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1108 if (cpu_has_feature(CPU_FTR_TM)) 1109 regs->msr |= MSR_TM; 1110 current->thread.tm_tfhar = 0; 1111 current->thread.tm_texasr = 0; 1112 current->thread.tm_tfiar = 0; 1113 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1114 } 1115 1116 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1117 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1118 1119 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1120 { 1121 struct pt_regs *regs = tsk->thread.regs; 1122 1123 /* This is a bit hairy. If we are an SPE enabled processor 1124 * (have embedded fp) we store the IEEE exception enable flags in 1125 * fpexc_mode. fpexc_mode is also used for setting FP exception 1126 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1127 if (val & PR_FP_EXC_SW_ENABLE) { 1128 #ifdef CONFIG_SPE 1129 if (cpu_has_feature(CPU_FTR_SPE)) { 1130 tsk->thread.fpexc_mode = val & 1131 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1132 return 0; 1133 } else { 1134 return -EINVAL; 1135 } 1136 #else 1137 return -EINVAL; 1138 #endif 1139 } 1140 1141 /* on a CONFIG_SPE this does not hurt us. The bits that 1142 * __pack_fe01 use do not overlap with bits used for 1143 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1144 * on CONFIG_SPE implementations are reserved so writing to 1145 * them does not change anything */ 1146 if (val > PR_FP_EXC_PRECISE) 1147 return -EINVAL; 1148 tsk->thread.fpexc_mode = __pack_fe01(val); 1149 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1150 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1151 | tsk->thread.fpexc_mode; 1152 return 0; 1153 } 1154 1155 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1156 { 1157 unsigned int val; 1158 1159 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1160 #ifdef CONFIG_SPE 1161 if (cpu_has_feature(CPU_FTR_SPE)) 1162 val = tsk->thread.fpexc_mode; 1163 else 1164 return -EINVAL; 1165 #else 1166 return -EINVAL; 1167 #endif 1168 else 1169 val = __unpack_fe01(tsk->thread.fpexc_mode); 1170 return put_user(val, (unsigned int __user *) adr); 1171 } 1172 1173 int set_endian(struct task_struct *tsk, unsigned int val) 1174 { 1175 struct pt_regs *regs = tsk->thread.regs; 1176 1177 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1178 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1179 return -EINVAL; 1180 1181 if (regs == NULL) 1182 return -EINVAL; 1183 1184 if (val == PR_ENDIAN_BIG) 1185 regs->msr &= ~MSR_LE; 1186 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1187 regs->msr |= MSR_LE; 1188 else 1189 return -EINVAL; 1190 1191 return 0; 1192 } 1193 1194 int get_endian(struct task_struct *tsk, unsigned long adr) 1195 { 1196 struct pt_regs *regs = tsk->thread.regs; 1197 unsigned int val; 1198 1199 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1200 !cpu_has_feature(CPU_FTR_REAL_LE)) 1201 return -EINVAL; 1202 1203 if (regs == NULL) 1204 return -EINVAL; 1205 1206 if (regs->msr & MSR_LE) { 1207 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1208 val = PR_ENDIAN_LITTLE; 1209 else 1210 val = PR_ENDIAN_PPC_LITTLE; 1211 } else 1212 val = PR_ENDIAN_BIG; 1213 1214 return put_user(val, (unsigned int __user *)adr); 1215 } 1216 1217 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1218 { 1219 tsk->thread.align_ctl = val; 1220 return 0; 1221 } 1222 1223 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1224 { 1225 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1226 } 1227 1228 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1229 unsigned long nbytes) 1230 { 1231 unsigned long stack_page; 1232 unsigned long cpu = task_cpu(p); 1233 1234 /* 1235 * Avoid crashing if the stack has overflowed and corrupted 1236 * task_cpu(p), which is in the thread_info struct. 1237 */ 1238 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1239 stack_page = (unsigned long) hardirq_ctx[cpu]; 1240 if (sp >= stack_page + sizeof(struct thread_struct) 1241 && sp <= stack_page + THREAD_SIZE - nbytes) 1242 return 1; 1243 1244 stack_page = (unsigned long) softirq_ctx[cpu]; 1245 if (sp >= stack_page + sizeof(struct thread_struct) 1246 && sp <= stack_page + THREAD_SIZE - nbytes) 1247 return 1; 1248 } 1249 return 0; 1250 } 1251 1252 int validate_sp(unsigned long sp, struct task_struct *p, 1253 unsigned long nbytes) 1254 { 1255 unsigned long stack_page = (unsigned long)task_stack_page(p); 1256 1257 if (sp >= stack_page + sizeof(struct thread_struct) 1258 && sp <= stack_page + THREAD_SIZE - nbytes) 1259 return 1; 1260 1261 return valid_irq_stack(sp, p, nbytes); 1262 } 1263 1264 EXPORT_SYMBOL(validate_sp); 1265 1266 unsigned long get_wchan(struct task_struct *p) 1267 { 1268 unsigned long ip, sp; 1269 int count = 0; 1270 1271 if (!p || p == current || p->state == TASK_RUNNING) 1272 return 0; 1273 1274 sp = p->thread.ksp; 1275 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1276 return 0; 1277 1278 do { 1279 sp = *(unsigned long *)sp; 1280 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1281 return 0; 1282 if (count > 0) { 1283 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1284 if (!in_sched_functions(ip)) 1285 return ip; 1286 } 1287 } while (count++ < 16); 1288 return 0; 1289 } 1290 1291 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1292 1293 void show_stack(struct task_struct *tsk, unsigned long *stack) 1294 { 1295 unsigned long sp, ip, lr, newsp; 1296 int count = 0; 1297 int firstframe = 1; 1298 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1299 int curr_frame = current->curr_ret_stack; 1300 extern void return_to_handler(void); 1301 unsigned long rth = (unsigned long)return_to_handler; 1302 unsigned long mrth = -1; 1303 #ifdef CONFIG_PPC64 1304 extern void mod_return_to_handler(void); 1305 rth = *(unsigned long *)rth; 1306 mrth = (unsigned long)mod_return_to_handler; 1307 mrth = *(unsigned long *)mrth; 1308 #endif 1309 #endif 1310 1311 sp = (unsigned long) stack; 1312 if (tsk == NULL) 1313 tsk = current; 1314 if (sp == 0) { 1315 if (tsk == current) 1316 asm("mr %0,1" : "=r" (sp)); 1317 else 1318 sp = tsk->thread.ksp; 1319 } 1320 1321 lr = 0; 1322 printk("Call Trace:\n"); 1323 do { 1324 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1325 return; 1326 1327 stack = (unsigned long *) sp; 1328 newsp = stack[0]; 1329 ip = stack[STACK_FRAME_LR_SAVE]; 1330 if (!firstframe || ip != lr) { 1331 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1332 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1333 if ((ip == rth || ip == mrth) && curr_frame >= 0) { 1334 printk(" (%pS)", 1335 (void *)current->ret_stack[curr_frame].ret); 1336 curr_frame--; 1337 } 1338 #endif 1339 if (firstframe) 1340 printk(" (unreliable)"); 1341 printk("\n"); 1342 } 1343 firstframe = 0; 1344 1345 /* 1346 * See if this is an exception frame. 1347 * We look for the "regshere" marker in the current frame. 1348 */ 1349 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1350 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1351 struct pt_regs *regs = (struct pt_regs *) 1352 (sp + STACK_FRAME_OVERHEAD); 1353 lr = regs->link; 1354 printk("--- Exception: %lx at %pS\n LR = %pS\n", 1355 regs->trap, (void *)regs->nip, (void *)lr); 1356 firstframe = 1; 1357 } 1358 1359 sp = newsp; 1360 } while (count++ < kstack_depth_to_print); 1361 } 1362 1363 void dump_stack(void) 1364 { 1365 show_stack(current, NULL); 1366 } 1367 EXPORT_SYMBOL(dump_stack); 1368 1369 #ifdef CONFIG_PPC64 1370 /* Called with hard IRQs off */ 1371 void __ppc64_runlatch_on(void) 1372 { 1373 struct thread_info *ti = current_thread_info(); 1374 unsigned long ctrl; 1375 1376 ctrl = mfspr(SPRN_CTRLF); 1377 ctrl |= CTRL_RUNLATCH; 1378 mtspr(SPRN_CTRLT, ctrl); 1379 1380 ti->local_flags |= _TLF_RUNLATCH; 1381 } 1382 1383 /* Called with hard IRQs off */ 1384 void __ppc64_runlatch_off(void) 1385 { 1386 struct thread_info *ti = current_thread_info(); 1387 unsigned long ctrl; 1388 1389 ti->local_flags &= ~_TLF_RUNLATCH; 1390 1391 ctrl = mfspr(SPRN_CTRLF); 1392 ctrl &= ~CTRL_RUNLATCH; 1393 mtspr(SPRN_CTRLT, ctrl); 1394 } 1395 #endif /* CONFIG_PPC64 */ 1396 1397 unsigned long arch_align_stack(unsigned long sp) 1398 { 1399 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1400 sp -= get_random_int() & ~PAGE_MASK; 1401 return sp & ~0xf; 1402 } 1403 1404 static inline unsigned long brk_rnd(void) 1405 { 1406 unsigned long rnd = 0; 1407 1408 /* 8MB for 32bit, 1GB for 64bit */ 1409 if (is_32bit_task()) 1410 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); 1411 else 1412 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); 1413 1414 return rnd << PAGE_SHIFT; 1415 } 1416 1417 unsigned long arch_randomize_brk(struct mm_struct *mm) 1418 { 1419 unsigned long base = mm->brk; 1420 unsigned long ret; 1421 1422 #ifdef CONFIG_PPC_STD_MMU_64 1423 /* 1424 * If we are using 1TB segments and we are allowed to randomise 1425 * the heap, we can put it above 1TB so it is backed by a 1TB 1426 * segment. Otherwise the heap will be in the bottom 1TB 1427 * which always uses 256MB segments and this may result in a 1428 * performance penalty. 1429 */ 1430 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1431 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1432 #endif 1433 1434 ret = PAGE_ALIGN(base + brk_rnd()); 1435 1436 if (ret < mm->brk) 1437 return mm->brk; 1438 1439 return ret; 1440 } 1441 1442 unsigned long randomize_et_dyn(unsigned long base) 1443 { 1444 unsigned long ret = PAGE_ALIGN(base + brk_rnd()); 1445 1446 if (ret < base) 1447 return base; 1448 1449 return ret; 1450 } 1451