1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/sched/debug.h> 20 #include <linux/sched/task.h> 21 #include <linux/sched/task_stack.h> 22 #include <linux/kernel.h> 23 #include <linux/mm.h> 24 #include <linux/smp.h> 25 #include <linux/stddef.h> 26 #include <linux/unistd.h> 27 #include <linux/ptrace.h> 28 #include <linux/slab.h> 29 #include <linux/user.h> 30 #include <linux/elf.h> 31 #include <linux/prctl.h> 32 #include <linux/init_task.h> 33 #include <linux/export.h> 34 #include <linux/kallsyms.h> 35 #include <linux/mqueue.h> 36 #include <linux/hardirq.h> 37 #include <linux/utsname.h> 38 #include <linux/ftrace.h> 39 #include <linux/kernel_stat.h> 40 #include <linux/personality.h> 41 #include <linux/random.h> 42 #include <linux/hw_breakpoint.h> 43 #include <linux/uaccess.h> 44 #include <linux/elf-randomize.h> 45 #include <linux/pkeys.h> 46 47 #include <asm/pgtable.h> 48 #include <asm/io.h> 49 #include <asm/processor.h> 50 #include <asm/mmu.h> 51 #include <asm/prom.h> 52 #include <asm/machdep.h> 53 #include <asm/time.h> 54 #include <asm/runlatch.h> 55 #include <asm/syscalls.h> 56 #include <asm/switch_to.h> 57 #include <asm/tm.h> 58 #include <asm/debug.h> 59 #ifdef CONFIG_PPC64 60 #include <asm/firmware.h> 61 #include <asm/hw_irq.h> 62 #endif 63 #include <asm/code-patching.h> 64 #include <asm/exec.h> 65 #include <asm/livepatch.h> 66 #include <asm/cpu_has_feature.h> 67 #include <asm/asm-prototypes.h> 68 69 #include <linux/kprobes.h> 70 #include <linux/kdebug.h> 71 72 /* Transactional Memory debug */ 73 #ifdef TM_DEBUG_SW 74 #define TM_DEBUG(x...) printk(KERN_INFO x) 75 #else 76 #define TM_DEBUG(x...) do { } while(0) 77 #endif 78 79 extern unsigned long _get_SP(void); 80 81 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 82 /* 83 * Are we running in "Suspend disabled" mode? If so we have to block any 84 * sigreturn that would get us into suspended state, and we also warn in some 85 * other paths that we should never reach with suspend disabled. 86 */ 87 bool tm_suspend_disabled __ro_after_init = false; 88 89 static void check_if_tm_restore_required(struct task_struct *tsk) 90 { 91 /* 92 * If we are saving the current thread's registers, and the 93 * thread is in a transactional state, set the TIF_RESTORE_TM 94 * bit so that we know to restore the registers before 95 * returning to userspace. 96 */ 97 if (tsk == current && tsk->thread.regs && 98 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 99 !test_thread_flag(TIF_RESTORE_TM)) { 100 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 101 set_thread_flag(TIF_RESTORE_TM); 102 } 103 } 104 105 static inline bool msr_tm_active(unsigned long msr) 106 { 107 return MSR_TM_ACTIVE(msr); 108 } 109 110 static bool tm_active_with_fp(struct task_struct *tsk) 111 { 112 return msr_tm_active(tsk->thread.regs->msr) && 113 (tsk->thread.ckpt_regs.msr & MSR_FP); 114 } 115 116 static bool tm_active_with_altivec(struct task_struct *tsk) 117 { 118 return msr_tm_active(tsk->thread.regs->msr) && 119 (tsk->thread.ckpt_regs.msr & MSR_VEC); 120 } 121 #else 122 static inline bool msr_tm_active(unsigned long msr) { return false; } 123 static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 124 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; } 125 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; } 126 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 127 128 bool strict_msr_control; 129 EXPORT_SYMBOL(strict_msr_control); 130 131 static int __init enable_strict_msr_control(char *str) 132 { 133 strict_msr_control = true; 134 pr_info("Enabling strict facility control\n"); 135 136 return 0; 137 } 138 early_param("ppc_strict_facility_enable", enable_strict_msr_control); 139 140 unsigned long msr_check_and_set(unsigned long bits) 141 { 142 unsigned long oldmsr = mfmsr(); 143 unsigned long newmsr; 144 145 newmsr = oldmsr | bits; 146 147 #ifdef CONFIG_VSX 148 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 149 newmsr |= MSR_VSX; 150 #endif 151 152 if (oldmsr != newmsr) 153 mtmsr_isync(newmsr); 154 155 return newmsr; 156 } 157 158 void __msr_check_and_clear(unsigned long bits) 159 { 160 unsigned long oldmsr = mfmsr(); 161 unsigned long newmsr; 162 163 newmsr = oldmsr & ~bits; 164 165 #ifdef CONFIG_VSX 166 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 167 newmsr &= ~MSR_VSX; 168 #endif 169 170 if (oldmsr != newmsr) 171 mtmsr_isync(newmsr); 172 } 173 EXPORT_SYMBOL(__msr_check_and_clear); 174 175 #ifdef CONFIG_PPC_FPU 176 void __giveup_fpu(struct task_struct *tsk) 177 { 178 unsigned long msr; 179 180 save_fpu(tsk); 181 msr = tsk->thread.regs->msr; 182 msr &= ~MSR_FP; 183 #ifdef CONFIG_VSX 184 if (cpu_has_feature(CPU_FTR_VSX)) 185 msr &= ~MSR_VSX; 186 #endif 187 tsk->thread.regs->msr = msr; 188 } 189 190 void giveup_fpu(struct task_struct *tsk) 191 { 192 check_if_tm_restore_required(tsk); 193 194 msr_check_and_set(MSR_FP); 195 __giveup_fpu(tsk); 196 msr_check_and_clear(MSR_FP); 197 } 198 EXPORT_SYMBOL(giveup_fpu); 199 200 /* 201 * Make sure the floating-point register state in the 202 * the thread_struct is up to date for task tsk. 203 */ 204 void flush_fp_to_thread(struct task_struct *tsk) 205 { 206 if (tsk->thread.regs) { 207 /* 208 * We need to disable preemption here because if we didn't, 209 * another process could get scheduled after the regs->msr 210 * test but before we have finished saving the FP registers 211 * to the thread_struct. That process could take over the 212 * FPU, and then when we get scheduled again we would store 213 * bogus values for the remaining FP registers. 214 */ 215 preempt_disable(); 216 if (tsk->thread.regs->msr & MSR_FP) { 217 /* 218 * This should only ever be called for current or 219 * for a stopped child process. Since we save away 220 * the FP register state on context switch, 221 * there is something wrong if a stopped child appears 222 * to still have its FP state in the CPU registers. 223 */ 224 BUG_ON(tsk != current); 225 giveup_fpu(tsk); 226 } 227 preempt_enable(); 228 } 229 } 230 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 231 232 void enable_kernel_fp(void) 233 { 234 unsigned long cpumsr; 235 236 WARN_ON(preemptible()); 237 238 cpumsr = msr_check_and_set(MSR_FP); 239 240 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 241 check_if_tm_restore_required(current); 242 /* 243 * If a thread has already been reclaimed then the 244 * checkpointed registers are on the CPU but have definitely 245 * been saved by the reclaim code. Don't need to and *cannot* 246 * giveup as this would save to the 'live' structure not the 247 * checkpointed structure. 248 */ 249 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 250 return; 251 __giveup_fpu(current); 252 } 253 } 254 EXPORT_SYMBOL(enable_kernel_fp); 255 256 static int restore_fp(struct task_struct *tsk) 257 { 258 if (tsk->thread.load_fp || tm_active_with_fp(tsk)) { 259 load_fp_state(¤t->thread.fp_state); 260 current->thread.load_fp++; 261 return 1; 262 } 263 return 0; 264 } 265 #else 266 static int restore_fp(struct task_struct *tsk) { return 0; } 267 #endif /* CONFIG_PPC_FPU */ 268 269 #ifdef CONFIG_ALTIVEC 270 #define loadvec(thr) ((thr).load_vec) 271 272 static void __giveup_altivec(struct task_struct *tsk) 273 { 274 unsigned long msr; 275 276 save_altivec(tsk); 277 msr = tsk->thread.regs->msr; 278 msr &= ~MSR_VEC; 279 #ifdef CONFIG_VSX 280 if (cpu_has_feature(CPU_FTR_VSX)) 281 msr &= ~MSR_VSX; 282 #endif 283 tsk->thread.regs->msr = msr; 284 } 285 286 void giveup_altivec(struct task_struct *tsk) 287 { 288 check_if_tm_restore_required(tsk); 289 290 msr_check_and_set(MSR_VEC); 291 __giveup_altivec(tsk); 292 msr_check_and_clear(MSR_VEC); 293 } 294 EXPORT_SYMBOL(giveup_altivec); 295 296 void enable_kernel_altivec(void) 297 { 298 unsigned long cpumsr; 299 300 WARN_ON(preemptible()); 301 302 cpumsr = msr_check_and_set(MSR_VEC); 303 304 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 305 check_if_tm_restore_required(current); 306 /* 307 * If a thread has already been reclaimed then the 308 * checkpointed registers are on the CPU but have definitely 309 * been saved by the reclaim code. Don't need to and *cannot* 310 * giveup as this would save to the 'live' structure not the 311 * checkpointed structure. 312 */ 313 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 314 return; 315 __giveup_altivec(current); 316 } 317 } 318 EXPORT_SYMBOL(enable_kernel_altivec); 319 320 /* 321 * Make sure the VMX/Altivec register state in the 322 * the thread_struct is up to date for task tsk. 323 */ 324 void flush_altivec_to_thread(struct task_struct *tsk) 325 { 326 if (tsk->thread.regs) { 327 preempt_disable(); 328 if (tsk->thread.regs->msr & MSR_VEC) { 329 BUG_ON(tsk != current); 330 giveup_altivec(tsk); 331 } 332 preempt_enable(); 333 } 334 } 335 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 336 337 static int restore_altivec(struct task_struct *tsk) 338 { 339 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 340 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) { 341 load_vr_state(&tsk->thread.vr_state); 342 tsk->thread.used_vr = 1; 343 tsk->thread.load_vec++; 344 345 return 1; 346 } 347 return 0; 348 } 349 #else 350 #define loadvec(thr) 0 351 static inline int restore_altivec(struct task_struct *tsk) { return 0; } 352 #endif /* CONFIG_ALTIVEC */ 353 354 #ifdef CONFIG_VSX 355 static void __giveup_vsx(struct task_struct *tsk) 356 { 357 unsigned long msr = tsk->thread.regs->msr; 358 359 /* 360 * We should never be ssetting MSR_VSX without also setting 361 * MSR_FP and MSR_VEC 362 */ 363 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 364 365 /* __giveup_fpu will clear MSR_VSX */ 366 if (msr & MSR_FP) 367 __giveup_fpu(tsk); 368 if (msr & MSR_VEC) 369 __giveup_altivec(tsk); 370 } 371 372 static void giveup_vsx(struct task_struct *tsk) 373 { 374 check_if_tm_restore_required(tsk); 375 376 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 377 __giveup_vsx(tsk); 378 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 379 } 380 381 void enable_kernel_vsx(void) 382 { 383 unsigned long cpumsr; 384 385 WARN_ON(preemptible()); 386 387 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 388 389 if (current->thread.regs && 390 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { 391 check_if_tm_restore_required(current); 392 /* 393 * If a thread has already been reclaimed then the 394 * checkpointed registers are on the CPU but have definitely 395 * been saved by the reclaim code. Don't need to and *cannot* 396 * giveup as this would save to the 'live' structure not the 397 * checkpointed structure. 398 */ 399 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) 400 return; 401 __giveup_vsx(current); 402 } 403 } 404 EXPORT_SYMBOL(enable_kernel_vsx); 405 406 void flush_vsx_to_thread(struct task_struct *tsk) 407 { 408 if (tsk->thread.regs) { 409 preempt_disable(); 410 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { 411 BUG_ON(tsk != current); 412 giveup_vsx(tsk); 413 } 414 preempt_enable(); 415 } 416 } 417 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 418 419 static int restore_vsx(struct task_struct *tsk) 420 { 421 if (cpu_has_feature(CPU_FTR_VSX)) { 422 tsk->thread.used_vsr = 1; 423 return 1; 424 } 425 426 return 0; 427 } 428 #else 429 static inline int restore_vsx(struct task_struct *tsk) { return 0; } 430 #endif /* CONFIG_VSX */ 431 432 #ifdef CONFIG_SPE 433 void giveup_spe(struct task_struct *tsk) 434 { 435 check_if_tm_restore_required(tsk); 436 437 msr_check_and_set(MSR_SPE); 438 __giveup_spe(tsk); 439 msr_check_and_clear(MSR_SPE); 440 } 441 EXPORT_SYMBOL(giveup_spe); 442 443 void enable_kernel_spe(void) 444 { 445 WARN_ON(preemptible()); 446 447 msr_check_and_set(MSR_SPE); 448 449 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 450 check_if_tm_restore_required(current); 451 __giveup_spe(current); 452 } 453 } 454 EXPORT_SYMBOL(enable_kernel_spe); 455 456 void flush_spe_to_thread(struct task_struct *tsk) 457 { 458 if (tsk->thread.regs) { 459 preempt_disable(); 460 if (tsk->thread.regs->msr & MSR_SPE) { 461 BUG_ON(tsk != current); 462 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 463 giveup_spe(tsk); 464 } 465 preempt_enable(); 466 } 467 } 468 #endif /* CONFIG_SPE */ 469 470 static unsigned long msr_all_available; 471 472 static int __init init_msr_all_available(void) 473 { 474 #ifdef CONFIG_PPC_FPU 475 msr_all_available |= MSR_FP; 476 #endif 477 #ifdef CONFIG_ALTIVEC 478 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 479 msr_all_available |= MSR_VEC; 480 #endif 481 #ifdef CONFIG_VSX 482 if (cpu_has_feature(CPU_FTR_VSX)) 483 msr_all_available |= MSR_VSX; 484 #endif 485 #ifdef CONFIG_SPE 486 if (cpu_has_feature(CPU_FTR_SPE)) 487 msr_all_available |= MSR_SPE; 488 #endif 489 490 return 0; 491 } 492 early_initcall(init_msr_all_available); 493 494 void giveup_all(struct task_struct *tsk) 495 { 496 unsigned long usermsr; 497 498 if (!tsk->thread.regs) 499 return; 500 501 usermsr = tsk->thread.regs->msr; 502 503 if ((usermsr & msr_all_available) == 0) 504 return; 505 506 msr_check_and_set(msr_all_available); 507 check_if_tm_restore_required(tsk); 508 509 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 510 511 #ifdef CONFIG_PPC_FPU 512 if (usermsr & MSR_FP) 513 __giveup_fpu(tsk); 514 #endif 515 #ifdef CONFIG_ALTIVEC 516 if (usermsr & MSR_VEC) 517 __giveup_altivec(tsk); 518 #endif 519 #ifdef CONFIG_SPE 520 if (usermsr & MSR_SPE) 521 __giveup_spe(tsk); 522 #endif 523 524 msr_check_and_clear(msr_all_available); 525 } 526 EXPORT_SYMBOL(giveup_all); 527 528 void restore_math(struct pt_regs *regs) 529 { 530 unsigned long msr; 531 532 if (!msr_tm_active(regs->msr) && 533 !current->thread.load_fp && !loadvec(current->thread)) 534 return; 535 536 msr = regs->msr; 537 msr_check_and_set(msr_all_available); 538 539 /* 540 * Only reload if the bit is not set in the user MSR, the bit BEING set 541 * indicates that the registers are hot 542 */ 543 if ((!(msr & MSR_FP)) && restore_fp(current)) 544 msr |= MSR_FP | current->thread.fpexc_mode; 545 546 if ((!(msr & MSR_VEC)) && restore_altivec(current)) 547 msr |= MSR_VEC; 548 549 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && 550 restore_vsx(current)) { 551 msr |= MSR_VSX; 552 } 553 554 msr_check_and_clear(msr_all_available); 555 556 regs->msr = msr; 557 } 558 559 void save_all(struct task_struct *tsk) 560 { 561 unsigned long usermsr; 562 563 if (!tsk->thread.regs) 564 return; 565 566 usermsr = tsk->thread.regs->msr; 567 568 if ((usermsr & msr_all_available) == 0) 569 return; 570 571 msr_check_and_set(msr_all_available); 572 573 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 574 575 if (usermsr & MSR_FP) 576 save_fpu(tsk); 577 578 if (usermsr & MSR_VEC) 579 save_altivec(tsk); 580 581 if (usermsr & MSR_SPE) 582 __giveup_spe(tsk); 583 584 msr_check_and_clear(msr_all_available); 585 } 586 587 void flush_all_to_thread(struct task_struct *tsk) 588 { 589 if (tsk->thread.regs) { 590 preempt_disable(); 591 BUG_ON(tsk != current); 592 save_all(tsk); 593 594 #ifdef CONFIG_SPE 595 if (tsk->thread.regs->msr & MSR_SPE) 596 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 597 #endif 598 599 preempt_enable(); 600 } 601 } 602 EXPORT_SYMBOL(flush_all_to_thread); 603 604 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 605 void do_send_trap(struct pt_regs *regs, unsigned long address, 606 unsigned long error_code, int breakpt) 607 { 608 current->thread.trap_nr = TRAP_HWBKPT; 609 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 610 11, SIGSEGV) == NOTIFY_STOP) 611 return; 612 613 /* Deliver the signal to userspace */ 614 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ 615 (void __user *)address); 616 } 617 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 618 void do_break (struct pt_regs *regs, unsigned long address, 619 unsigned long error_code) 620 { 621 siginfo_t info; 622 623 current->thread.trap_nr = TRAP_HWBKPT; 624 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 625 11, SIGSEGV) == NOTIFY_STOP) 626 return; 627 628 if (debugger_break_match(regs)) 629 return; 630 631 /* Clear the breakpoint */ 632 hw_breakpoint_disable(); 633 634 /* Deliver the signal to userspace */ 635 info.si_signo = SIGTRAP; 636 info.si_errno = 0; 637 info.si_code = TRAP_HWBKPT; 638 info.si_addr = (void __user *)address; 639 force_sig_info(SIGTRAP, &info, current); 640 } 641 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 642 643 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 644 645 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 646 /* 647 * Set the debug registers back to their default "safe" values. 648 */ 649 static void set_debug_reg_defaults(struct thread_struct *thread) 650 { 651 thread->debug.iac1 = thread->debug.iac2 = 0; 652 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 653 thread->debug.iac3 = thread->debug.iac4 = 0; 654 #endif 655 thread->debug.dac1 = thread->debug.dac2 = 0; 656 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 657 thread->debug.dvc1 = thread->debug.dvc2 = 0; 658 #endif 659 thread->debug.dbcr0 = 0; 660 #ifdef CONFIG_BOOKE 661 /* 662 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 663 */ 664 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 665 DBCR1_IAC3US | DBCR1_IAC4US; 666 /* 667 * Force Data Address Compare User/Supervisor bits to be User-only 668 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 669 */ 670 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 671 #else 672 thread->debug.dbcr1 = 0; 673 #endif 674 } 675 676 static void prime_debug_regs(struct debug_reg *debug) 677 { 678 /* 679 * We could have inherited MSR_DE from userspace, since 680 * it doesn't get cleared on exception entry. Make sure 681 * MSR_DE is clear before we enable any debug events. 682 */ 683 mtmsr(mfmsr() & ~MSR_DE); 684 685 mtspr(SPRN_IAC1, debug->iac1); 686 mtspr(SPRN_IAC2, debug->iac2); 687 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 688 mtspr(SPRN_IAC3, debug->iac3); 689 mtspr(SPRN_IAC4, debug->iac4); 690 #endif 691 mtspr(SPRN_DAC1, debug->dac1); 692 mtspr(SPRN_DAC2, debug->dac2); 693 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 694 mtspr(SPRN_DVC1, debug->dvc1); 695 mtspr(SPRN_DVC2, debug->dvc2); 696 #endif 697 mtspr(SPRN_DBCR0, debug->dbcr0); 698 mtspr(SPRN_DBCR1, debug->dbcr1); 699 #ifdef CONFIG_BOOKE 700 mtspr(SPRN_DBCR2, debug->dbcr2); 701 #endif 702 } 703 /* 704 * Unless neither the old or new thread are making use of the 705 * debug registers, set the debug registers from the values 706 * stored in the new thread. 707 */ 708 void switch_booke_debug_regs(struct debug_reg *new_debug) 709 { 710 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 711 || (new_debug->dbcr0 & DBCR0_IDM)) 712 prime_debug_regs(new_debug); 713 } 714 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 715 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 716 #ifndef CONFIG_HAVE_HW_BREAKPOINT 717 static void set_debug_reg_defaults(struct thread_struct *thread) 718 { 719 thread->hw_brk.address = 0; 720 thread->hw_brk.type = 0; 721 set_breakpoint(&thread->hw_brk); 722 } 723 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 724 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 725 726 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 727 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 728 { 729 mtspr(SPRN_DAC1, dabr); 730 #ifdef CONFIG_PPC_47x 731 isync(); 732 #endif 733 return 0; 734 } 735 #elif defined(CONFIG_PPC_BOOK3S) 736 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 737 { 738 mtspr(SPRN_DABR, dabr); 739 if (cpu_has_feature(CPU_FTR_DABRX)) 740 mtspr(SPRN_DABRX, dabrx); 741 return 0; 742 } 743 #elif defined(CONFIG_PPC_8xx) 744 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 745 { 746 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR; 747 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */ 748 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */ 749 750 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 751 lctrl1 |= 0xa0000; 752 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 753 lctrl1 |= 0xf0000; 754 else if ((dabr & HW_BRK_TYPE_RDWR) == 0) 755 lctrl2 = 0; 756 757 mtspr(SPRN_LCTRL2, 0); 758 mtspr(SPRN_CMPE, addr); 759 mtspr(SPRN_CMPF, addr + 4); 760 mtspr(SPRN_LCTRL1, lctrl1); 761 mtspr(SPRN_LCTRL2, lctrl2); 762 763 return 0; 764 } 765 #else 766 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 767 { 768 return -EINVAL; 769 } 770 #endif 771 772 static inline int set_dabr(struct arch_hw_breakpoint *brk) 773 { 774 unsigned long dabr, dabrx; 775 776 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 777 dabrx = ((brk->type >> 3) & 0x7); 778 779 if (ppc_md.set_dabr) 780 return ppc_md.set_dabr(dabr, dabrx); 781 782 return __set_dabr(dabr, dabrx); 783 } 784 785 static inline int set_dawr(struct arch_hw_breakpoint *brk) 786 { 787 unsigned long dawr, dawrx, mrd; 788 789 dawr = brk->address; 790 791 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 792 << (63 - 58); //* read/write bits */ 793 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 794 << (63 - 59); //* translate */ 795 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 796 >> 3; //* PRIM bits */ 797 /* dawr length is stored in field MDR bits 48:53. Matches range in 798 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 799 0b111111=64DW. 800 brk->len is in bytes. 801 This aligns up to double word size, shifts and does the bias. 802 */ 803 mrd = ((brk->len + 7) >> 3) - 1; 804 dawrx |= (mrd & 0x3f) << (63 - 53); 805 806 if (ppc_md.set_dawr) 807 return ppc_md.set_dawr(dawr, dawrx); 808 mtspr(SPRN_DAWR, dawr); 809 mtspr(SPRN_DAWRX, dawrx); 810 return 0; 811 } 812 813 void __set_breakpoint(struct arch_hw_breakpoint *brk) 814 { 815 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); 816 817 if (cpu_has_feature(CPU_FTR_DAWR)) 818 set_dawr(brk); 819 else 820 set_dabr(brk); 821 } 822 823 void set_breakpoint(struct arch_hw_breakpoint *brk) 824 { 825 preempt_disable(); 826 __set_breakpoint(brk); 827 preempt_enable(); 828 } 829 830 #ifdef CONFIG_PPC64 831 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 832 #endif 833 834 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 835 struct arch_hw_breakpoint *b) 836 { 837 if (a->address != b->address) 838 return false; 839 if (a->type != b->type) 840 return false; 841 if (a->len != b->len) 842 return false; 843 return true; 844 } 845 846 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 847 848 static inline bool tm_enabled(struct task_struct *tsk) 849 { 850 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 851 } 852 853 static void tm_reclaim_thread(struct thread_struct *thr, 854 struct thread_info *ti, uint8_t cause) 855 { 856 /* 857 * Use the current MSR TM suspended bit to track if we have 858 * checkpointed state outstanding. 859 * On signal delivery, we'd normally reclaim the checkpointed 860 * state to obtain stack pointer (see:get_tm_stackpointer()). 861 * This will then directly return to userspace without going 862 * through __switch_to(). However, if the stack frame is bad, 863 * we need to exit this thread which calls __switch_to() which 864 * will again attempt to reclaim the already saved tm state. 865 * Hence we need to check that we've not already reclaimed 866 * this state. 867 * We do this using the current MSR, rather tracking it in 868 * some specific thread_struct bit, as it has the additional 869 * benefit of checking for a potential TM bad thing exception. 870 */ 871 if (!MSR_TM_SUSPENDED(mfmsr())) 872 return; 873 874 giveup_all(container_of(thr, struct task_struct, thread)); 875 876 tm_reclaim(thr, cause); 877 878 /* 879 * If we are in a transaction and FP is off then we can't have 880 * used FP inside that transaction. Hence the checkpointed 881 * state is the same as the live state. We need to copy the 882 * live state to the checkpointed state so that when the 883 * transaction is restored, the checkpointed state is correct 884 * and the aborted transaction sees the correct state. We use 885 * ckpt_regs.msr here as that's what tm_reclaim will use to 886 * determine if it's going to write the checkpointed state or 887 * not. So either this will write the checkpointed registers, 888 * or reclaim will. Similarly for VMX. 889 */ 890 if ((thr->ckpt_regs.msr & MSR_FP) == 0) 891 memcpy(&thr->ckfp_state, &thr->fp_state, 892 sizeof(struct thread_fp_state)); 893 if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 894 memcpy(&thr->ckvr_state, &thr->vr_state, 895 sizeof(struct thread_vr_state)); 896 } 897 898 void tm_reclaim_current(uint8_t cause) 899 { 900 tm_enable(); 901 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 902 } 903 904 static inline void tm_reclaim_task(struct task_struct *tsk) 905 { 906 /* We have to work out if we're switching from/to a task that's in the 907 * middle of a transaction. 908 * 909 * In switching we need to maintain a 2nd register state as 910 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 911 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 912 * ckvr_state 913 * 914 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 915 */ 916 struct thread_struct *thr = &tsk->thread; 917 918 if (!thr->regs) 919 return; 920 921 if (!MSR_TM_ACTIVE(thr->regs->msr)) 922 goto out_and_saveregs; 923 924 WARN_ON(tm_suspend_disabled); 925 926 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 927 "ccr=%lx, msr=%lx, trap=%lx)\n", 928 tsk->pid, thr->regs->nip, 929 thr->regs->ccr, thr->regs->msr, 930 thr->regs->trap); 931 932 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 933 934 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 935 tsk->pid); 936 937 out_and_saveregs: 938 /* Always save the regs here, even if a transaction's not active. 939 * This context-switches a thread's TM info SPRs. We do it here to 940 * be consistent with the restore path (in recheckpoint) which 941 * cannot happen later in _switch(). 942 */ 943 tm_save_sprs(thr); 944 } 945 946 extern void __tm_recheckpoint(struct thread_struct *thread); 947 948 void tm_recheckpoint(struct thread_struct *thread) 949 { 950 unsigned long flags; 951 952 if (!(thread->regs->msr & MSR_TM)) 953 return; 954 955 /* We really can't be interrupted here as the TEXASR registers can't 956 * change and later in the trecheckpoint code, we have a userspace R1. 957 * So let's hard disable over this region. 958 */ 959 local_irq_save(flags); 960 hard_irq_disable(); 961 962 /* The TM SPRs are restored here, so that TEXASR.FS can be set 963 * before the trecheckpoint and no explosion occurs. 964 */ 965 tm_restore_sprs(thread); 966 967 __tm_recheckpoint(thread); 968 969 local_irq_restore(flags); 970 } 971 972 static inline void tm_recheckpoint_new_task(struct task_struct *new) 973 { 974 if (!cpu_has_feature(CPU_FTR_TM)) 975 return; 976 977 /* Recheckpoint the registers of the thread we're about to switch to. 978 * 979 * If the task was using FP, we non-lazily reload both the original and 980 * the speculative FP register states. This is because the kernel 981 * doesn't see if/when a TM rollback occurs, so if we take an FP 982 * unavailable later, we are unable to determine which set of FP regs 983 * need to be restored. 984 */ 985 if (!tm_enabled(new)) 986 return; 987 988 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 989 tm_restore_sprs(&new->thread); 990 return; 991 } 992 /* Recheckpoint to restore original checkpointed register state. */ 993 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", 994 new->pid, new->thread.regs->msr); 995 996 tm_recheckpoint(&new->thread); 997 998 /* 999 * The checkpointed state has been restored but the live state has 1000 * not, ensure all the math functionality is turned off to trigger 1001 * restore_math() to reload. 1002 */ 1003 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1004 1005 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1006 "(kernel msr 0x%lx)\n", 1007 new->pid, mfmsr()); 1008 } 1009 1010 static inline void __switch_to_tm(struct task_struct *prev, 1011 struct task_struct *new) 1012 { 1013 if (cpu_has_feature(CPU_FTR_TM)) { 1014 if (tm_enabled(prev) || tm_enabled(new)) 1015 tm_enable(); 1016 1017 if (tm_enabled(prev)) { 1018 prev->thread.load_tm++; 1019 tm_reclaim_task(prev); 1020 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 1021 prev->thread.regs->msr &= ~MSR_TM; 1022 } 1023 1024 tm_recheckpoint_new_task(new); 1025 } 1026 } 1027 1028 /* 1029 * This is called if we are on the way out to userspace and the 1030 * TIF_RESTORE_TM flag is set. It checks if we need to reload 1031 * FP and/or vector state and does so if necessary. 1032 * If userspace is inside a transaction (whether active or 1033 * suspended) and FP/VMX/VSX instructions have ever been enabled 1034 * inside that transaction, then we have to keep them enabled 1035 * and keep the FP/VMX/VSX state loaded while ever the transaction 1036 * continues. The reason is that if we didn't, and subsequently 1037 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1038 * we don't know whether it's the same transaction, and thus we 1039 * don't know which of the checkpointed state and the transactional 1040 * state to use. 1041 */ 1042 void restore_tm_state(struct pt_regs *regs) 1043 { 1044 unsigned long msr_diff; 1045 1046 /* 1047 * This is the only moment we should clear TIF_RESTORE_TM as 1048 * it is here that ckpt_regs.msr and pt_regs.msr become the same 1049 * again, anything else could lead to an incorrect ckpt_msr being 1050 * saved and therefore incorrect signal contexts. 1051 */ 1052 clear_thread_flag(TIF_RESTORE_TM); 1053 if (!MSR_TM_ACTIVE(regs->msr)) 1054 return; 1055 1056 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1057 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 1058 1059 /* Ensure that restore_math() will restore */ 1060 if (msr_diff & MSR_FP) 1061 current->thread.load_fp = 1; 1062 #ifdef CONFIG_ALTIVEC 1063 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1064 current->thread.load_vec = 1; 1065 #endif 1066 restore_math(regs); 1067 1068 regs->msr |= msr_diff; 1069 } 1070 1071 #else 1072 #define tm_recheckpoint_new_task(new) 1073 #define __switch_to_tm(prev, new) 1074 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1075 1076 static inline void save_sprs(struct thread_struct *t) 1077 { 1078 #ifdef CONFIG_ALTIVEC 1079 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1080 t->vrsave = mfspr(SPRN_VRSAVE); 1081 #endif 1082 #ifdef CONFIG_PPC_BOOK3S_64 1083 if (cpu_has_feature(CPU_FTR_DSCR)) 1084 t->dscr = mfspr(SPRN_DSCR); 1085 1086 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1087 t->bescr = mfspr(SPRN_BESCR); 1088 t->ebbhr = mfspr(SPRN_EBBHR); 1089 t->ebbrr = mfspr(SPRN_EBBRR); 1090 1091 t->fscr = mfspr(SPRN_FSCR); 1092 1093 /* 1094 * Note that the TAR is not available for use in the kernel. 1095 * (To provide this, the TAR should be backed up/restored on 1096 * exception entry/exit instead, and be in pt_regs. FIXME, 1097 * this should be in pt_regs anyway (for debug).) 1098 */ 1099 t->tar = mfspr(SPRN_TAR); 1100 } 1101 #endif 1102 1103 thread_pkey_regs_save(t); 1104 } 1105 1106 static inline void restore_sprs(struct thread_struct *old_thread, 1107 struct thread_struct *new_thread) 1108 { 1109 #ifdef CONFIG_ALTIVEC 1110 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1111 old_thread->vrsave != new_thread->vrsave) 1112 mtspr(SPRN_VRSAVE, new_thread->vrsave); 1113 #endif 1114 #ifdef CONFIG_PPC_BOOK3S_64 1115 if (cpu_has_feature(CPU_FTR_DSCR)) { 1116 u64 dscr = get_paca()->dscr_default; 1117 if (new_thread->dscr_inherit) 1118 dscr = new_thread->dscr; 1119 1120 if (old_thread->dscr != dscr) 1121 mtspr(SPRN_DSCR, dscr); 1122 } 1123 1124 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1125 if (old_thread->bescr != new_thread->bescr) 1126 mtspr(SPRN_BESCR, new_thread->bescr); 1127 if (old_thread->ebbhr != new_thread->ebbhr) 1128 mtspr(SPRN_EBBHR, new_thread->ebbhr); 1129 if (old_thread->ebbrr != new_thread->ebbrr) 1130 mtspr(SPRN_EBBRR, new_thread->ebbrr); 1131 1132 if (old_thread->fscr != new_thread->fscr) 1133 mtspr(SPRN_FSCR, new_thread->fscr); 1134 1135 if (old_thread->tar != new_thread->tar) 1136 mtspr(SPRN_TAR, new_thread->tar); 1137 } 1138 1139 if (cpu_has_feature(CPU_FTR_ARCH_300) && 1140 old_thread->tidr != new_thread->tidr) 1141 mtspr(SPRN_TIDR, new_thread->tidr); 1142 #endif 1143 1144 thread_pkey_regs_restore(new_thread, old_thread); 1145 } 1146 1147 #ifdef CONFIG_PPC_BOOK3S_64 1148 #define CP_SIZE 128 1149 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE))); 1150 #endif 1151 1152 struct task_struct *__switch_to(struct task_struct *prev, 1153 struct task_struct *new) 1154 { 1155 struct thread_struct *new_thread, *old_thread; 1156 struct task_struct *last; 1157 #ifdef CONFIG_PPC_BOOK3S_64 1158 struct ppc64_tlb_batch *batch; 1159 #endif 1160 1161 new_thread = &new->thread; 1162 old_thread = ¤t->thread; 1163 1164 WARN_ON(!irqs_disabled()); 1165 1166 #ifdef CONFIG_PPC64 1167 /* 1168 * Collect processor utilization data per process 1169 */ 1170 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 1171 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); 1172 long unsigned start_tb, current_tb; 1173 start_tb = old_thread->start_tb; 1174 cu->current_tb = current_tb = mfspr(SPRN_PURR); 1175 old_thread->accum_tb += (current_tb - start_tb); 1176 new_thread->start_tb = current_tb; 1177 } 1178 #endif /* CONFIG_PPC64 */ 1179 1180 #ifdef CONFIG_PPC_BOOK3S_64 1181 batch = this_cpu_ptr(&ppc64_tlb_batch); 1182 if (batch->active) { 1183 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1184 if (batch->index) 1185 __flush_tlb_pending(batch); 1186 batch->active = 0; 1187 } 1188 #endif /* CONFIG_PPC_BOOK3S_64 */ 1189 1190 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1191 switch_booke_debug_regs(&new->thread.debug); 1192 #else 1193 /* 1194 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1195 * schedule DABR 1196 */ 1197 #ifndef CONFIG_HAVE_HW_BREAKPOINT 1198 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) 1199 __set_breakpoint(&new->thread.hw_brk); 1200 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1201 #endif 1202 1203 /* 1204 * We need to save SPRs before treclaim/trecheckpoint as these will 1205 * change a number of them. 1206 */ 1207 save_sprs(&prev->thread); 1208 1209 /* Save FPU, Altivec, VSX and SPE state */ 1210 giveup_all(prev); 1211 1212 __switch_to_tm(prev, new); 1213 1214 if (!radix_enabled()) { 1215 /* 1216 * We can't take a PMU exception inside _switch() since there 1217 * is a window where the kernel stack SLB and the kernel stack 1218 * are out of sync. Hard disable here. 1219 */ 1220 hard_irq_disable(); 1221 } 1222 1223 /* 1224 * Call restore_sprs() before calling _switch(). If we move it after 1225 * _switch() then we miss out on calling it for new tasks. The reason 1226 * for this is we manually create a stack frame for new tasks that 1227 * directly returns through ret_from_fork() or 1228 * ret_from_kernel_thread(). See copy_thread() for details. 1229 */ 1230 restore_sprs(old_thread, new_thread); 1231 1232 last = _switch(old_thread, new_thread); 1233 1234 #ifdef CONFIG_PPC_BOOK3S_64 1235 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1236 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 1237 batch = this_cpu_ptr(&ppc64_tlb_batch); 1238 batch->active = 1; 1239 } 1240 1241 if (current_thread_info()->task->thread.regs) { 1242 restore_math(current_thread_info()->task->thread.regs); 1243 1244 /* 1245 * The copy-paste buffer can only store into foreign real 1246 * addresses, so unprivileged processes can not see the 1247 * data or use it in any way unless they have foreign real 1248 * mappings. If the new process has the foreign real address 1249 * mappings, we must issue a cp_abort to clear any state and 1250 * prevent snooping, corruption or a covert channel. 1251 * 1252 * DD1 allows paste into normal system memory so we do an 1253 * unpaired copy, rather than cp_abort, to clear the buffer, 1254 * since cp_abort is quite expensive. 1255 */ 1256 if (current_thread_info()->task->thread.used_vas) { 1257 asm volatile(PPC_CP_ABORT); 1258 } else if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 1259 asm volatile(PPC_COPY(%0, %1) 1260 : : "r"(dummy_copy_buffer), "r"(0)); 1261 } 1262 } 1263 #endif /* CONFIG_PPC_BOOK3S_64 */ 1264 1265 return last; 1266 } 1267 1268 static int instructions_to_print = 16; 1269 1270 static void show_instructions(struct pt_regs *regs) 1271 { 1272 int i; 1273 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 1274 sizeof(int)); 1275 1276 printk("Instruction dump:"); 1277 1278 for (i = 0; i < instructions_to_print; i++) { 1279 int instr; 1280 1281 if (!(i % 8)) 1282 pr_cont("\n"); 1283 1284 #if !defined(CONFIG_BOOKE) 1285 /* If executing with the IMMU off, adjust pc rather 1286 * than print XXXXXXXX. 1287 */ 1288 if (!(regs->msr & MSR_IR)) 1289 pc = (unsigned long)phys_to_virt(pc); 1290 #endif 1291 1292 if (!__kernel_text_address(pc) || 1293 probe_kernel_address((unsigned int __user *)pc, instr)) { 1294 pr_cont("XXXXXXXX "); 1295 } else { 1296 if (regs->nip == pc) 1297 pr_cont("<%08x> ", instr); 1298 else 1299 pr_cont("%08x ", instr); 1300 } 1301 1302 pc += sizeof(int); 1303 } 1304 1305 pr_cont("\n"); 1306 } 1307 1308 struct regbit { 1309 unsigned long bit; 1310 const char *name; 1311 }; 1312 1313 static struct regbit msr_bits[] = { 1314 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 1315 {MSR_SF, "SF"}, 1316 {MSR_HV, "HV"}, 1317 #endif 1318 {MSR_VEC, "VEC"}, 1319 {MSR_VSX, "VSX"}, 1320 #ifdef CONFIG_BOOKE 1321 {MSR_CE, "CE"}, 1322 #endif 1323 {MSR_EE, "EE"}, 1324 {MSR_PR, "PR"}, 1325 {MSR_FP, "FP"}, 1326 {MSR_ME, "ME"}, 1327 #ifdef CONFIG_BOOKE 1328 {MSR_DE, "DE"}, 1329 #else 1330 {MSR_SE, "SE"}, 1331 {MSR_BE, "BE"}, 1332 #endif 1333 {MSR_IR, "IR"}, 1334 {MSR_DR, "DR"}, 1335 {MSR_PMM, "PMM"}, 1336 #ifndef CONFIG_BOOKE 1337 {MSR_RI, "RI"}, 1338 {MSR_LE, "LE"}, 1339 #endif 1340 {0, NULL} 1341 }; 1342 1343 static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 1344 { 1345 const char *s = ""; 1346 1347 for (; bits->bit; ++bits) 1348 if (val & bits->bit) { 1349 pr_cont("%s%s", s, bits->name); 1350 s = sep; 1351 } 1352 } 1353 1354 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1355 static struct regbit msr_tm_bits[] = { 1356 {MSR_TS_T, "T"}, 1357 {MSR_TS_S, "S"}, 1358 {MSR_TM, "E"}, 1359 {0, NULL} 1360 }; 1361 1362 static void print_tm_bits(unsigned long val) 1363 { 1364 /* 1365 * This only prints something if at least one of the TM bit is set. 1366 * Inside the TM[], the output means: 1367 * E: Enabled (bit 32) 1368 * S: Suspended (bit 33) 1369 * T: Transactional (bit 34) 1370 */ 1371 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1372 pr_cont(",TM["); 1373 print_bits(val, msr_tm_bits, ""); 1374 pr_cont("]"); 1375 } 1376 } 1377 #else 1378 static void print_tm_bits(unsigned long val) {} 1379 #endif 1380 1381 static void print_msr_bits(unsigned long val) 1382 { 1383 pr_cont("<"); 1384 print_bits(val, msr_bits, ","); 1385 print_tm_bits(val); 1386 pr_cont(">"); 1387 } 1388 1389 #ifdef CONFIG_PPC64 1390 #define REG "%016lx" 1391 #define REGS_PER_LINE 4 1392 #define LAST_VOLATILE 13 1393 #else 1394 #define REG "%08lx" 1395 #define REGS_PER_LINE 8 1396 #define LAST_VOLATILE 12 1397 #endif 1398 1399 void show_regs(struct pt_regs * regs) 1400 { 1401 int i, trap; 1402 1403 show_regs_print_info(KERN_DEFAULT); 1404 1405 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 1406 regs->nip, regs->link, regs->ctr); 1407 printk("REGS: %px TRAP: %04lx %s (%s)\n", 1408 regs, regs->trap, print_tainted(), init_utsname()->release); 1409 printk("MSR: "REG" ", regs->msr); 1410 print_msr_bits(regs->msr); 1411 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1412 trap = TRAP(regs); 1413 if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1414 pr_cont("CFAR: "REG" ", regs->orig_gpr3); 1415 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1416 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1417 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1418 #else 1419 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1420 #endif 1421 #ifdef CONFIG_PPC64 1422 pr_cont("SOFTE: %ld ", regs->softe); 1423 #endif 1424 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1425 if (MSR_TM_ACTIVE(regs->msr)) 1426 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1427 #endif 1428 1429 for (i = 0; i < 32; i++) { 1430 if ((i % REGS_PER_LINE) == 0) 1431 pr_cont("\nGPR%02d: ", i); 1432 pr_cont(REG " ", regs->gpr[i]); 1433 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1434 break; 1435 } 1436 pr_cont("\n"); 1437 #ifdef CONFIG_KALLSYMS 1438 /* 1439 * Lookup NIP late so we have the best change of getting the 1440 * above info out without failing 1441 */ 1442 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1443 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1444 #endif 1445 show_stack(current, (unsigned long *) regs->gpr[1]); 1446 if (!user_mode(regs)) 1447 show_instructions(regs); 1448 } 1449 1450 void flush_thread(void) 1451 { 1452 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1453 flush_ptrace_hw_breakpoint(current); 1454 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1455 set_debug_reg_defaults(¤t->thread); 1456 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1457 } 1458 1459 int set_thread_uses_vas(void) 1460 { 1461 #ifdef CONFIG_PPC_BOOK3S_64 1462 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1463 return -EINVAL; 1464 1465 current->thread.used_vas = 1; 1466 1467 /* 1468 * Even a process that has no foreign real address mapping can use 1469 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT 1470 * to clear any pending COPY and prevent a covert channel. 1471 * 1472 * __switch_to() will issue CP_ABORT on future context switches. 1473 */ 1474 asm volatile(PPC_CP_ABORT); 1475 1476 #endif /* CONFIG_PPC_BOOK3S_64 */ 1477 return 0; 1478 } 1479 1480 #ifdef CONFIG_PPC64 1481 static DEFINE_SPINLOCK(vas_thread_id_lock); 1482 static DEFINE_IDA(vas_thread_ida); 1483 1484 /* 1485 * We need to assign a unique thread id to each thread in a process. 1486 * 1487 * This thread id, referred to as TIDR, and separate from the Linux's tgid, 1488 * is intended to be used to direct an ASB_Notify from the hardware to the 1489 * thread, when a suitable event occurs in the system. 1490 * 1491 * One such event is a "paste" instruction in the context of Fast Thread 1492 * Wakeup (aka Core-to-core wake up in the Virtual Accelerator Switchboard 1493 * (VAS) in POWER9. 1494 * 1495 * To get a unique TIDR per process we could simply reuse task_pid_nr() but 1496 * the problem is that task_pid_nr() is not yet available copy_thread() is 1497 * called. Fixing that would require changing more intrusive arch-neutral 1498 * code in code path in copy_process()?. 1499 * 1500 * Further, to assign unique TIDRs within each process, we need an atomic 1501 * field (or an IDR) in task_struct, which again intrudes into the arch- 1502 * neutral code. So try to assign globally unique TIDRs for now. 1503 * 1504 * NOTE: TIDR 0 indicates that the thread does not need a TIDR value. 1505 * For now, only threads that expect to be notified by the VAS 1506 * hardware need a TIDR value and we assign values > 0 for those. 1507 */ 1508 #define MAX_THREAD_CONTEXT ((1 << 16) - 1) 1509 static int assign_thread_tidr(void) 1510 { 1511 int index; 1512 int err; 1513 unsigned long flags; 1514 1515 again: 1516 if (!ida_pre_get(&vas_thread_ida, GFP_KERNEL)) 1517 return -ENOMEM; 1518 1519 spin_lock_irqsave(&vas_thread_id_lock, flags); 1520 err = ida_get_new_above(&vas_thread_ida, 1, &index); 1521 spin_unlock_irqrestore(&vas_thread_id_lock, flags); 1522 1523 if (err == -EAGAIN) 1524 goto again; 1525 else if (err) 1526 return err; 1527 1528 if (index > MAX_THREAD_CONTEXT) { 1529 spin_lock_irqsave(&vas_thread_id_lock, flags); 1530 ida_remove(&vas_thread_ida, index); 1531 spin_unlock_irqrestore(&vas_thread_id_lock, flags); 1532 return -ENOMEM; 1533 } 1534 1535 return index; 1536 } 1537 1538 static void free_thread_tidr(int id) 1539 { 1540 unsigned long flags; 1541 1542 spin_lock_irqsave(&vas_thread_id_lock, flags); 1543 ida_remove(&vas_thread_ida, id); 1544 spin_unlock_irqrestore(&vas_thread_id_lock, flags); 1545 } 1546 1547 /* 1548 * Clear any TIDR value assigned to this thread. 1549 */ 1550 void clear_thread_tidr(struct task_struct *t) 1551 { 1552 if (!t->thread.tidr) 1553 return; 1554 1555 if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1556 WARN_ON_ONCE(1); 1557 return; 1558 } 1559 1560 mtspr(SPRN_TIDR, 0); 1561 free_thread_tidr(t->thread.tidr); 1562 t->thread.tidr = 0; 1563 } 1564 1565 void arch_release_task_struct(struct task_struct *t) 1566 { 1567 clear_thread_tidr(t); 1568 } 1569 1570 /* 1571 * Assign a unique TIDR (thread id) for task @t and set it in the thread 1572 * structure. For now, we only support setting TIDR for 'current' task. 1573 */ 1574 int set_thread_tidr(struct task_struct *t) 1575 { 1576 int rc; 1577 1578 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1579 return -EINVAL; 1580 1581 if (t != current) 1582 return -EINVAL; 1583 1584 if (t->thread.tidr) 1585 return 0; 1586 1587 rc = assign_thread_tidr(); 1588 if (rc < 0) 1589 return rc; 1590 1591 t->thread.tidr = rc; 1592 mtspr(SPRN_TIDR, t->thread.tidr); 1593 1594 return 0; 1595 } 1596 EXPORT_SYMBOL_GPL(set_thread_tidr); 1597 1598 #endif /* CONFIG_PPC64 */ 1599 1600 void 1601 release_thread(struct task_struct *t) 1602 { 1603 } 1604 1605 /* 1606 * this gets called so that we can store coprocessor state into memory and 1607 * copy the current task into the new thread. 1608 */ 1609 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1610 { 1611 flush_all_to_thread(src); 1612 /* 1613 * Flush TM state out so we can copy it. __switch_to_tm() does this 1614 * flush but it removes the checkpointed state from the current CPU and 1615 * transitions the CPU out of TM mode. Hence we need to call 1616 * tm_recheckpoint_new_task() (on the same task) to restore the 1617 * checkpointed state back and the TM mode. 1618 * 1619 * Can't pass dst because it isn't ready. Doesn't matter, passing 1620 * dst is only important for __switch_to() 1621 */ 1622 __switch_to_tm(src, src); 1623 1624 *dst = *src; 1625 1626 clear_task_ebb(dst); 1627 1628 return 0; 1629 } 1630 1631 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1632 { 1633 #ifdef CONFIG_PPC_BOOK3S_64 1634 unsigned long sp_vsid; 1635 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1636 1637 if (radix_enabled()) 1638 return; 1639 1640 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1641 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1642 << SLB_VSID_SHIFT_1T; 1643 else 1644 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1645 << SLB_VSID_SHIFT; 1646 sp_vsid |= SLB_VSID_KERNEL | llp; 1647 p->thread.ksp_vsid = sp_vsid; 1648 #endif 1649 } 1650 1651 /* 1652 * Copy a thread.. 1653 */ 1654 1655 /* 1656 * Copy architecture-specific thread state 1657 */ 1658 int copy_thread(unsigned long clone_flags, unsigned long usp, 1659 unsigned long kthread_arg, struct task_struct *p) 1660 { 1661 struct pt_regs *childregs, *kregs; 1662 extern void ret_from_fork(void); 1663 extern void ret_from_kernel_thread(void); 1664 void (*f)(void); 1665 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1666 struct thread_info *ti = task_thread_info(p); 1667 1668 klp_init_thread_info(ti); 1669 1670 /* Copy registers */ 1671 sp -= sizeof(struct pt_regs); 1672 childregs = (struct pt_regs *) sp; 1673 if (unlikely(p->flags & PF_KTHREAD)) { 1674 /* kernel thread */ 1675 memset(childregs, 0, sizeof(struct pt_regs)); 1676 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1677 /* function */ 1678 if (usp) 1679 childregs->gpr[14] = ppc_function_entry((void *)usp); 1680 #ifdef CONFIG_PPC64 1681 clear_tsk_thread_flag(p, TIF_32BIT); 1682 childregs->softe = IRQS_ENABLED; 1683 #endif 1684 childregs->gpr[15] = kthread_arg; 1685 p->thread.regs = NULL; /* no user register state */ 1686 ti->flags |= _TIF_RESTOREALL; 1687 f = ret_from_kernel_thread; 1688 } else { 1689 /* user thread */ 1690 struct pt_regs *regs = current_pt_regs(); 1691 CHECK_FULL_REGS(regs); 1692 *childregs = *regs; 1693 if (usp) 1694 childregs->gpr[1] = usp; 1695 p->thread.regs = childregs; 1696 childregs->gpr[3] = 0; /* Result from fork() */ 1697 if (clone_flags & CLONE_SETTLS) { 1698 #ifdef CONFIG_PPC64 1699 if (!is_32bit_task()) 1700 childregs->gpr[13] = childregs->gpr[6]; 1701 else 1702 #endif 1703 childregs->gpr[2] = childregs->gpr[6]; 1704 } 1705 1706 f = ret_from_fork; 1707 } 1708 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 1709 sp -= STACK_FRAME_OVERHEAD; 1710 1711 /* 1712 * The way this works is that at some point in the future 1713 * some task will call _switch to switch to the new task. 1714 * That will pop off the stack frame created below and start 1715 * the new task running at ret_from_fork. The new task will 1716 * do some house keeping and then return from the fork or clone 1717 * system call, using the stack frame created above. 1718 */ 1719 ((unsigned long *)sp)[0] = 0; 1720 sp -= sizeof(struct pt_regs); 1721 kregs = (struct pt_regs *) sp; 1722 sp -= STACK_FRAME_OVERHEAD; 1723 p->thread.ksp = sp; 1724 #ifdef CONFIG_PPC32 1725 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1726 _ALIGN_UP(sizeof(struct thread_info), 16); 1727 #endif 1728 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1729 p->thread.ptrace_bps[0] = NULL; 1730 #endif 1731 1732 p->thread.fp_save_area = NULL; 1733 #ifdef CONFIG_ALTIVEC 1734 p->thread.vr_save_area = NULL; 1735 #endif 1736 1737 setup_ksp_vsid(p, sp); 1738 1739 #ifdef CONFIG_PPC64 1740 if (cpu_has_feature(CPU_FTR_DSCR)) { 1741 p->thread.dscr_inherit = current->thread.dscr_inherit; 1742 p->thread.dscr = mfspr(SPRN_DSCR); 1743 } 1744 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1745 p->thread.ppr = INIT_PPR; 1746 1747 p->thread.tidr = 0; 1748 #endif 1749 kregs->nip = ppc_function_entry(f); 1750 return 0; 1751 } 1752 1753 /* 1754 * Set up a thread for executing a new program 1755 */ 1756 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1757 { 1758 #ifdef CONFIG_PPC64 1759 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1760 #endif 1761 1762 /* 1763 * If we exec out of a kernel thread then thread.regs will not be 1764 * set. Do it now. 1765 */ 1766 if (!current->thread.regs) { 1767 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1768 current->thread.regs = regs - 1; 1769 } 1770 1771 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1772 /* 1773 * Clear any transactional state, we're exec()ing. The cause is 1774 * not important as there will never be a recheckpoint so it's not 1775 * user visible. 1776 */ 1777 if (MSR_TM_SUSPENDED(mfmsr())) 1778 tm_reclaim_current(0); 1779 #endif 1780 1781 memset(regs->gpr, 0, sizeof(regs->gpr)); 1782 regs->ctr = 0; 1783 regs->link = 0; 1784 regs->xer = 0; 1785 regs->ccr = 0; 1786 regs->gpr[1] = sp; 1787 1788 /* 1789 * We have just cleared all the nonvolatile GPRs, so make 1790 * FULL_REGS(regs) return true. This is necessary to allow 1791 * ptrace to examine the thread immediately after exec. 1792 */ 1793 regs->trap &= ~1UL; 1794 1795 #ifdef CONFIG_PPC32 1796 regs->mq = 0; 1797 regs->nip = start; 1798 regs->msr = MSR_USER; 1799 #else 1800 if (!is_32bit_task()) { 1801 unsigned long entry; 1802 1803 if (is_elf2_task()) { 1804 /* Look ma, no function descriptors! */ 1805 entry = start; 1806 1807 /* 1808 * Ulrich says: 1809 * The latest iteration of the ABI requires that when 1810 * calling a function (at its global entry point), 1811 * the caller must ensure r12 holds the entry point 1812 * address (so that the function can quickly 1813 * establish addressability). 1814 */ 1815 regs->gpr[12] = start; 1816 /* Make sure that's restored on entry to userspace. */ 1817 set_thread_flag(TIF_RESTOREALL); 1818 } else { 1819 unsigned long toc; 1820 1821 /* start is a relocated pointer to the function 1822 * descriptor for the elf _start routine. The first 1823 * entry in the function descriptor is the entry 1824 * address of _start and the second entry is the TOC 1825 * value we need to use. 1826 */ 1827 __get_user(entry, (unsigned long __user *)start); 1828 __get_user(toc, (unsigned long __user *)start+1); 1829 1830 /* Check whether the e_entry function descriptor entries 1831 * need to be relocated before we can use them. 1832 */ 1833 if (load_addr != 0) { 1834 entry += load_addr; 1835 toc += load_addr; 1836 } 1837 regs->gpr[2] = toc; 1838 } 1839 regs->nip = entry; 1840 regs->msr = MSR_USER64; 1841 } else { 1842 regs->nip = start; 1843 regs->gpr[2] = 0; 1844 regs->msr = MSR_USER32; 1845 } 1846 #endif 1847 #ifdef CONFIG_VSX 1848 current->thread.used_vsr = 0; 1849 #endif 1850 current->thread.load_fp = 0; 1851 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1852 current->thread.fp_save_area = NULL; 1853 #ifdef CONFIG_ALTIVEC 1854 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1855 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1856 current->thread.vr_save_area = NULL; 1857 current->thread.vrsave = 0; 1858 current->thread.used_vr = 0; 1859 current->thread.load_vec = 0; 1860 #endif /* CONFIG_ALTIVEC */ 1861 #ifdef CONFIG_SPE 1862 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1863 current->thread.acc = 0; 1864 current->thread.spefscr = 0; 1865 current->thread.used_spe = 0; 1866 #endif /* CONFIG_SPE */ 1867 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1868 current->thread.tm_tfhar = 0; 1869 current->thread.tm_texasr = 0; 1870 current->thread.tm_tfiar = 0; 1871 current->thread.load_tm = 0; 1872 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1873 1874 thread_pkey_regs_init(¤t->thread); 1875 } 1876 EXPORT_SYMBOL(start_thread); 1877 1878 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1879 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1880 1881 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1882 { 1883 struct pt_regs *regs = tsk->thread.regs; 1884 1885 /* This is a bit hairy. If we are an SPE enabled processor 1886 * (have embedded fp) we store the IEEE exception enable flags in 1887 * fpexc_mode. fpexc_mode is also used for setting FP exception 1888 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1889 if (val & PR_FP_EXC_SW_ENABLE) { 1890 #ifdef CONFIG_SPE 1891 if (cpu_has_feature(CPU_FTR_SPE)) { 1892 /* 1893 * When the sticky exception bits are set 1894 * directly by userspace, it must call prctl 1895 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1896 * in the existing prctl settings) or 1897 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1898 * the bits being set). <fenv.h> functions 1899 * saving and restoring the whole 1900 * floating-point environment need to do so 1901 * anyway to restore the prctl settings from 1902 * the saved environment. 1903 */ 1904 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1905 tsk->thread.fpexc_mode = val & 1906 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1907 return 0; 1908 } else { 1909 return -EINVAL; 1910 } 1911 #else 1912 return -EINVAL; 1913 #endif 1914 } 1915 1916 /* on a CONFIG_SPE this does not hurt us. The bits that 1917 * __pack_fe01 use do not overlap with bits used for 1918 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1919 * on CONFIG_SPE implementations are reserved so writing to 1920 * them does not change anything */ 1921 if (val > PR_FP_EXC_PRECISE) 1922 return -EINVAL; 1923 tsk->thread.fpexc_mode = __pack_fe01(val); 1924 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1925 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1926 | tsk->thread.fpexc_mode; 1927 return 0; 1928 } 1929 1930 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1931 { 1932 unsigned int val; 1933 1934 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1935 #ifdef CONFIG_SPE 1936 if (cpu_has_feature(CPU_FTR_SPE)) { 1937 /* 1938 * When the sticky exception bits are set 1939 * directly by userspace, it must call prctl 1940 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1941 * in the existing prctl settings) or 1942 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1943 * the bits being set). <fenv.h> functions 1944 * saving and restoring the whole 1945 * floating-point environment need to do so 1946 * anyway to restore the prctl settings from 1947 * the saved environment. 1948 */ 1949 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1950 val = tsk->thread.fpexc_mode; 1951 } else 1952 return -EINVAL; 1953 #else 1954 return -EINVAL; 1955 #endif 1956 else 1957 val = __unpack_fe01(tsk->thread.fpexc_mode); 1958 return put_user(val, (unsigned int __user *) adr); 1959 } 1960 1961 int set_endian(struct task_struct *tsk, unsigned int val) 1962 { 1963 struct pt_regs *regs = tsk->thread.regs; 1964 1965 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1966 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1967 return -EINVAL; 1968 1969 if (regs == NULL) 1970 return -EINVAL; 1971 1972 if (val == PR_ENDIAN_BIG) 1973 regs->msr &= ~MSR_LE; 1974 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1975 regs->msr |= MSR_LE; 1976 else 1977 return -EINVAL; 1978 1979 return 0; 1980 } 1981 1982 int get_endian(struct task_struct *tsk, unsigned long adr) 1983 { 1984 struct pt_regs *regs = tsk->thread.regs; 1985 unsigned int val; 1986 1987 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1988 !cpu_has_feature(CPU_FTR_REAL_LE)) 1989 return -EINVAL; 1990 1991 if (regs == NULL) 1992 return -EINVAL; 1993 1994 if (regs->msr & MSR_LE) { 1995 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1996 val = PR_ENDIAN_LITTLE; 1997 else 1998 val = PR_ENDIAN_PPC_LITTLE; 1999 } else 2000 val = PR_ENDIAN_BIG; 2001 2002 return put_user(val, (unsigned int __user *)adr); 2003 } 2004 2005 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 2006 { 2007 tsk->thread.align_ctl = val; 2008 return 0; 2009 } 2010 2011 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 2012 { 2013 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 2014 } 2015 2016 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 2017 unsigned long nbytes) 2018 { 2019 unsigned long stack_page; 2020 unsigned long cpu = task_cpu(p); 2021 2022 /* 2023 * Avoid crashing if the stack has overflowed and corrupted 2024 * task_cpu(p), which is in the thread_info struct. 2025 */ 2026 if (cpu < NR_CPUS && cpu_possible(cpu)) { 2027 stack_page = (unsigned long) hardirq_ctx[cpu]; 2028 if (sp >= stack_page + sizeof(struct thread_struct) 2029 && sp <= stack_page + THREAD_SIZE - nbytes) 2030 return 1; 2031 2032 stack_page = (unsigned long) softirq_ctx[cpu]; 2033 if (sp >= stack_page + sizeof(struct thread_struct) 2034 && sp <= stack_page + THREAD_SIZE - nbytes) 2035 return 1; 2036 } 2037 return 0; 2038 } 2039 2040 int validate_sp(unsigned long sp, struct task_struct *p, 2041 unsigned long nbytes) 2042 { 2043 unsigned long stack_page = (unsigned long)task_stack_page(p); 2044 2045 if (sp >= stack_page + sizeof(struct thread_struct) 2046 && sp <= stack_page + THREAD_SIZE - nbytes) 2047 return 1; 2048 2049 return valid_irq_stack(sp, p, nbytes); 2050 } 2051 2052 EXPORT_SYMBOL(validate_sp); 2053 2054 unsigned long get_wchan(struct task_struct *p) 2055 { 2056 unsigned long ip, sp; 2057 int count = 0; 2058 2059 if (!p || p == current || p->state == TASK_RUNNING) 2060 return 0; 2061 2062 sp = p->thread.ksp; 2063 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 2064 return 0; 2065 2066 do { 2067 sp = *(unsigned long *)sp; 2068 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || 2069 p->state == TASK_RUNNING) 2070 return 0; 2071 if (count > 0) { 2072 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 2073 if (!in_sched_functions(ip)) 2074 return ip; 2075 } 2076 } while (count++ < 16); 2077 return 0; 2078 } 2079 2080 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 2081 2082 void show_stack(struct task_struct *tsk, unsigned long *stack) 2083 { 2084 unsigned long sp, ip, lr, newsp; 2085 int count = 0; 2086 int firstframe = 1; 2087 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 2088 int curr_frame = current->curr_ret_stack; 2089 extern void return_to_handler(void); 2090 unsigned long rth = (unsigned long)return_to_handler; 2091 #endif 2092 2093 sp = (unsigned long) stack; 2094 if (tsk == NULL) 2095 tsk = current; 2096 if (sp == 0) { 2097 if (tsk == current) 2098 sp = current_stack_pointer(); 2099 else 2100 sp = tsk->thread.ksp; 2101 } 2102 2103 lr = 0; 2104 printk("Call Trace:\n"); 2105 do { 2106 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 2107 return; 2108 2109 stack = (unsigned long *) sp; 2110 newsp = stack[0]; 2111 ip = stack[STACK_FRAME_LR_SAVE]; 2112 if (!firstframe || ip != lr) { 2113 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 2114 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 2115 if ((ip == rth) && curr_frame >= 0) { 2116 pr_cont(" (%pS)", 2117 (void *)current->ret_stack[curr_frame].ret); 2118 curr_frame--; 2119 } 2120 #endif 2121 if (firstframe) 2122 pr_cont(" (unreliable)"); 2123 pr_cont("\n"); 2124 } 2125 firstframe = 0; 2126 2127 /* 2128 * See if this is an exception frame. 2129 * We look for the "regshere" marker in the current frame. 2130 */ 2131 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 2132 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 2133 struct pt_regs *regs = (struct pt_regs *) 2134 (sp + STACK_FRAME_OVERHEAD); 2135 lr = regs->link; 2136 printk("--- interrupt: %lx at %pS\n LR = %pS\n", 2137 regs->trap, (void *)regs->nip, (void *)lr); 2138 firstframe = 1; 2139 } 2140 2141 sp = newsp; 2142 } while (count++ < kstack_depth_to_print); 2143 } 2144 2145 #ifdef CONFIG_PPC64 2146 /* Called with hard IRQs off */ 2147 void notrace __ppc64_runlatch_on(void) 2148 { 2149 struct thread_info *ti = current_thread_info(); 2150 2151 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2152 /* 2153 * Least significant bit (RUN) is the only writable bit of 2154 * the CTRL register, so we can avoid mfspr. 2.06 is not the 2155 * earliest ISA where this is the case, but it's convenient. 2156 */ 2157 mtspr(SPRN_CTRLT, CTRL_RUNLATCH); 2158 } else { 2159 unsigned long ctrl; 2160 2161 /* 2162 * Some architectures (e.g., Cell) have writable fields other 2163 * than RUN, so do the read-modify-write. 2164 */ 2165 ctrl = mfspr(SPRN_CTRLF); 2166 ctrl |= CTRL_RUNLATCH; 2167 mtspr(SPRN_CTRLT, ctrl); 2168 } 2169 2170 ti->local_flags |= _TLF_RUNLATCH; 2171 } 2172 2173 /* Called with hard IRQs off */ 2174 void notrace __ppc64_runlatch_off(void) 2175 { 2176 struct thread_info *ti = current_thread_info(); 2177 2178 ti->local_flags &= ~_TLF_RUNLATCH; 2179 2180 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2181 mtspr(SPRN_CTRLT, 0); 2182 } else { 2183 unsigned long ctrl; 2184 2185 ctrl = mfspr(SPRN_CTRLF); 2186 ctrl &= ~CTRL_RUNLATCH; 2187 mtspr(SPRN_CTRLT, ctrl); 2188 } 2189 } 2190 #endif /* CONFIG_PPC64 */ 2191 2192 unsigned long arch_align_stack(unsigned long sp) 2193 { 2194 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2195 sp -= get_random_int() & ~PAGE_MASK; 2196 return sp & ~0xf; 2197 } 2198 2199 static inline unsigned long brk_rnd(void) 2200 { 2201 unsigned long rnd = 0; 2202 2203 /* 8MB for 32bit, 1GB for 64bit */ 2204 if (is_32bit_task()) 2205 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2206 else 2207 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2208 2209 return rnd << PAGE_SHIFT; 2210 } 2211 2212 unsigned long arch_randomize_brk(struct mm_struct *mm) 2213 { 2214 unsigned long base = mm->brk; 2215 unsigned long ret; 2216 2217 #ifdef CONFIG_PPC_BOOK3S_64 2218 /* 2219 * If we are using 1TB segments and we are allowed to randomise 2220 * the heap, we can put it above 1TB so it is backed by a 1TB 2221 * segment. Otherwise the heap will be in the bottom 1TB 2222 * which always uses 256MB segments and this may result in a 2223 * performance penalty. We don't need to worry about radix. For 2224 * radix, mmu_highuser_ssize remains unchanged from 256MB. 2225 */ 2226 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 2227 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 2228 #endif 2229 2230 ret = PAGE_ALIGN(base + brk_rnd()); 2231 2232 if (ret < mm->brk) 2233 return mm->brk; 2234 2235 return ret; 2236 } 2237 2238