xref: /openbmc/linux/arch/powerpc/kernel/process.c (revision 7b73a9c8)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Derived from "arch/i386/kernel/process.c"
4  *    Copyright (C) 1995  Linus Torvalds
5  *
6  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7  *  Paul Mackerras (paulus@cs.anu.edu.au)
8  *
9  *  PowerPC version
10  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11  */
12 
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/random.h>
38 #include <linux/hw_breakpoint.h>
39 #include <linux/uaccess.h>
40 #include <linux/elf-randomize.h>
41 #include <linux/pkeys.h>
42 #include <linux/seq_buf.h>
43 
44 #include <asm/pgtable.h>
45 #include <asm/io.h>
46 #include <asm/processor.h>
47 #include <asm/mmu.h>
48 #include <asm/prom.h>
49 #include <asm/machdep.h>
50 #include <asm/time.h>
51 #include <asm/runlatch.h>
52 #include <asm/syscalls.h>
53 #include <asm/switch_to.h>
54 #include <asm/tm.h>
55 #include <asm/debug.h>
56 #ifdef CONFIG_PPC64
57 #include <asm/firmware.h>
58 #include <asm/hw_irq.h>
59 #endif
60 #include <asm/code-patching.h>
61 #include <asm/exec.h>
62 #include <asm/livepatch.h>
63 #include <asm/cpu_has_feature.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/stacktrace.h>
66 #include <asm/hw_breakpoint.h>
67 
68 #include <linux/kprobes.h>
69 #include <linux/kdebug.h>
70 
71 /* Transactional Memory debug */
72 #ifdef TM_DEBUG_SW
73 #define TM_DEBUG(x...) printk(KERN_INFO x)
74 #else
75 #define TM_DEBUG(x...) do { } while(0)
76 #endif
77 
78 extern unsigned long _get_SP(void);
79 
80 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
81 /*
82  * Are we running in "Suspend disabled" mode? If so we have to block any
83  * sigreturn that would get us into suspended state, and we also warn in some
84  * other paths that we should never reach with suspend disabled.
85  */
86 bool tm_suspend_disabled __ro_after_init = false;
87 
88 static void check_if_tm_restore_required(struct task_struct *tsk)
89 {
90 	/*
91 	 * If we are saving the current thread's registers, and the
92 	 * thread is in a transactional state, set the TIF_RESTORE_TM
93 	 * bit so that we know to restore the registers before
94 	 * returning to userspace.
95 	 */
96 	if (tsk == current && tsk->thread.regs &&
97 	    MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
98 	    !test_thread_flag(TIF_RESTORE_TM)) {
99 		tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
100 		set_thread_flag(TIF_RESTORE_TM);
101 	}
102 }
103 
104 #else
105 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
106 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
107 
108 bool strict_msr_control;
109 EXPORT_SYMBOL(strict_msr_control);
110 
111 static int __init enable_strict_msr_control(char *str)
112 {
113 	strict_msr_control = true;
114 	pr_info("Enabling strict facility control\n");
115 
116 	return 0;
117 }
118 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
119 
120 /* notrace because it's called by restore_math */
121 unsigned long notrace msr_check_and_set(unsigned long bits)
122 {
123 	unsigned long oldmsr = mfmsr();
124 	unsigned long newmsr;
125 
126 	newmsr = oldmsr | bits;
127 
128 #ifdef CONFIG_VSX
129 	if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
130 		newmsr |= MSR_VSX;
131 #endif
132 
133 	if (oldmsr != newmsr)
134 		mtmsr_isync(newmsr);
135 
136 	return newmsr;
137 }
138 EXPORT_SYMBOL_GPL(msr_check_and_set);
139 
140 /* notrace because it's called by restore_math */
141 void notrace __msr_check_and_clear(unsigned long bits)
142 {
143 	unsigned long oldmsr = mfmsr();
144 	unsigned long newmsr;
145 
146 	newmsr = oldmsr & ~bits;
147 
148 #ifdef CONFIG_VSX
149 	if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
150 		newmsr &= ~MSR_VSX;
151 #endif
152 
153 	if (oldmsr != newmsr)
154 		mtmsr_isync(newmsr);
155 }
156 EXPORT_SYMBOL(__msr_check_and_clear);
157 
158 #ifdef CONFIG_PPC_FPU
159 static void __giveup_fpu(struct task_struct *tsk)
160 {
161 	unsigned long msr;
162 
163 	save_fpu(tsk);
164 	msr = tsk->thread.regs->msr;
165 	msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
166 #ifdef CONFIG_VSX
167 	if (cpu_has_feature(CPU_FTR_VSX))
168 		msr &= ~MSR_VSX;
169 #endif
170 	tsk->thread.regs->msr = msr;
171 }
172 
173 void giveup_fpu(struct task_struct *tsk)
174 {
175 	check_if_tm_restore_required(tsk);
176 
177 	msr_check_and_set(MSR_FP);
178 	__giveup_fpu(tsk);
179 	msr_check_and_clear(MSR_FP);
180 }
181 EXPORT_SYMBOL(giveup_fpu);
182 
183 /*
184  * Make sure the floating-point register state in the
185  * the thread_struct is up to date for task tsk.
186  */
187 void flush_fp_to_thread(struct task_struct *tsk)
188 {
189 	if (tsk->thread.regs) {
190 		/*
191 		 * We need to disable preemption here because if we didn't,
192 		 * another process could get scheduled after the regs->msr
193 		 * test but before we have finished saving the FP registers
194 		 * to the thread_struct.  That process could take over the
195 		 * FPU, and then when we get scheduled again we would store
196 		 * bogus values for the remaining FP registers.
197 		 */
198 		preempt_disable();
199 		if (tsk->thread.regs->msr & MSR_FP) {
200 			/*
201 			 * This should only ever be called for current or
202 			 * for a stopped child process.  Since we save away
203 			 * the FP register state on context switch,
204 			 * there is something wrong if a stopped child appears
205 			 * to still have its FP state in the CPU registers.
206 			 */
207 			BUG_ON(tsk != current);
208 			giveup_fpu(tsk);
209 		}
210 		preempt_enable();
211 	}
212 }
213 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
214 
215 void enable_kernel_fp(void)
216 {
217 	unsigned long cpumsr;
218 
219 	WARN_ON(preemptible());
220 
221 	cpumsr = msr_check_and_set(MSR_FP);
222 
223 	if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
224 		check_if_tm_restore_required(current);
225 		/*
226 		 * If a thread has already been reclaimed then the
227 		 * checkpointed registers are on the CPU but have definitely
228 		 * been saved by the reclaim code. Don't need to and *cannot*
229 		 * giveup as this would save  to the 'live' structure not the
230 		 * checkpointed structure.
231 		 */
232 		if (!MSR_TM_ACTIVE(cpumsr) &&
233 		     MSR_TM_ACTIVE(current->thread.regs->msr))
234 			return;
235 		__giveup_fpu(current);
236 	}
237 }
238 EXPORT_SYMBOL(enable_kernel_fp);
239 
240 static int restore_fp(struct task_struct *tsk)
241 {
242 	if (tsk->thread.load_fp) {
243 		load_fp_state(&current->thread.fp_state);
244 		current->thread.load_fp++;
245 		return 1;
246 	}
247 	return 0;
248 }
249 #else
250 static int restore_fp(struct task_struct *tsk) { return 0; }
251 #endif /* CONFIG_PPC_FPU */
252 
253 #ifdef CONFIG_ALTIVEC
254 #define loadvec(thr) ((thr).load_vec)
255 
256 static void __giveup_altivec(struct task_struct *tsk)
257 {
258 	unsigned long msr;
259 
260 	save_altivec(tsk);
261 	msr = tsk->thread.regs->msr;
262 	msr &= ~MSR_VEC;
263 #ifdef CONFIG_VSX
264 	if (cpu_has_feature(CPU_FTR_VSX))
265 		msr &= ~MSR_VSX;
266 #endif
267 	tsk->thread.regs->msr = msr;
268 }
269 
270 void giveup_altivec(struct task_struct *tsk)
271 {
272 	check_if_tm_restore_required(tsk);
273 
274 	msr_check_and_set(MSR_VEC);
275 	__giveup_altivec(tsk);
276 	msr_check_and_clear(MSR_VEC);
277 }
278 EXPORT_SYMBOL(giveup_altivec);
279 
280 void enable_kernel_altivec(void)
281 {
282 	unsigned long cpumsr;
283 
284 	WARN_ON(preemptible());
285 
286 	cpumsr = msr_check_and_set(MSR_VEC);
287 
288 	if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
289 		check_if_tm_restore_required(current);
290 		/*
291 		 * If a thread has already been reclaimed then the
292 		 * checkpointed registers are on the CPU but have definitely
293 		 * been saved by the reclaim code. Don't need to and *cannot*
294 		 * giveup as this would save  to the 'live' structure not the
295 		 * checkpointed structure.
296 		 */
297 		if (!MSR_TM_ACTIVE(cpumsr) &&
298 		     MSR_TM_ACTIVE(current->thread.regs->msr))
299 			return;
300 		__giveup_altivec(current);
301 	}
302 }
303 EXPORT_SYMBOL(enable_kernel_altivec);
304 
305 /*
306  * Make sure the VMX/Altivec register state in the
307  * the thread_struct is up to date for task tsk.
308  */
309 void flush_altivec_to_thread(struct task_struct *tsk)
310 {
311 	if (tsk->thread.regs) {
312 		preempt_disable();
313 		if (tsk->thread.regs->msr & MSR_VEC) {
314 			BUG_ON(tsk != current);
315 			giveup_altivec(tsk);
316 		}
317 		preempt_enable();
318 	}
319 }
320 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
321 
322 static int restore_altivec(struct task_struct *tsk)
323 {
324 	if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) {
325 		load_vr_state(&tsk->thread.vr_state);
326 		tsk->thread.used_vr = 1;
327 		tsk->thread.load_vec++;
328 
329 		return 1;
330 	}
331 	return 0;
332 }
333 #else
334 #define loadvec(thr) 0
335 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
336 #endif /* CONFIG_ALTIVEC */
337 
338 #ifdef CONFIG_VSX
339 static void __giveup_vsx(struct task_struct *tsk)
340 {
341 	unsigned long msr = tsk->thread.regs->msr;
342 
343 	/*
344 	 * We should never be ssetting MSR_VSX without also setting
345 	 * MSR_FP and MSR_VEC
346 	 */
347 	WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
348 
349 	/* __giveup_fpu will clear MSR_VSX */
350 	if (msr & MSR_FP)
351 		__giveup_fpu(tsk);
352 	if (msr & MSR_VEC)
353 		__giveup_altivec(tsk);
354 }
355 
356 static void giveup_vsx(struct task_struct *tsk)
357 {
358 	check_if_tm_restore_required(tsk);
359 
360 	msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
361 	__giveup_vsx(tsk);
362 	msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
363 }
364 
365 void enable_kernel_vsx(void)
366 {
367 	unsigned long cpumsr;
368 
369 	WARN_ON(preemptible());
370 
371 	cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
372 
373 	if (current->thread.regs &&
374 	    (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
375 		check_if_tm_restore_required(current);
376 		/*
377 		 * If a thread has already been reclaimed then the
378 		 * checkpointed registers are on the CPU but have definitely
379 		 * been saved by the reclaim code. Don't need to and *cannot*
380 		 * giveup as this would save  to the 'live' structure not the
381 		 * checkpointed structure.
382 		 */
383 		if (!MSR_TM_ACTIVE(cpumsr) &&
384 		     MSR_TM_ACTIVE(current->thread.regs->msr))
385 			return;
386 		__giveup_vsx(current);
387 	}
388 }
389 EXPORT_SYMBOL(enable_kernel_vsx);
390 
391 void flush_vsx_to_thread(struct task_struct *tsk)
392 {
393 	if (tsk->thread.regs) {
394 		preempt_disable();
395 		if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
396 			BUG_ON(tsk != current);
397 			giveup_vsx(tsk);
398 		}
399 		preempt_enable();
400 	}
401 }
402 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
403 
404 static int restore_vsx(struct task_struct *tsk)
405 {
406 	if (cpu_has_feature(CPU_FTR_VSX)) {
407 		tsk->thread.used_vsr = 1;
408 		return 1;
409 	}
410 
411 	return 0;
412 }
413 #else
414 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
415 #endif /* CONFIG_VSX */
416 
417 #ifdef CONFIG_SPE
418 void giveup_spe(struct task_struct *tsk)
419 {
420 	check_if_tm_restore_required(tsk);
421 
422 	msr_check_and_set(MSR_SPE);
423 	__giveup_spe(tsk);
424 	msr_check_and_clear(MSR_SPE);
425 }
426 EXPORT_SYMBOL(giveup_spe);
427 
428 void enable_kernel_spe(void)
429 {
430 	WARN_ON(preemptible());
431 
432 	msr_check_and_set(MSR_SPE);
433 
434 	if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
435 		check_if_tm_restore_required(current);
436 		__giveup_spe(current);
437 	}
438 }
439 EXPORT_SYMBOL(enable_kernel_spe);
440 
441 void flush_spe_to_thread(struct task_struct *tsk)
442 {
443 	if (tsk->thread.regs) {
444 		preempt_disable();
445 		if (tsk->thread.regs->msr & MSR_SPE) {
446 			BUG_ON(tsk != current);
447 			tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
448 			giveup_spe(tsk);
449 		}
450 		preempt_enable();
451 	}
452 }
453 #endif /* CONFIG_SPE */
454 
455 static unsigned long msr_all_available;
456 
457 static int __init init_msr_all_available(void)
458 {
459 #ifdef CONFIG_PPC_FPU
460 	msr_all_available |= MSR_FP;
461 #endif
462 #ifdef CONFIG_ALTIVEC
463 	if (cpu_has_feature(CPU_FTR_ALTIVEC))
464 		msr_all_available |= MSR_VEC;
465 #endif
466 #ifdef CONFIG_VSX
467 	if (cpu_has_feature(CPU_FTR_VSX))
468 		msr_all_available |= MSR_VSX;
469 #endif
470 #ifdef CONFIG_SPE
471 	if (cpu_has_feature(CPU_FTR_SPE))
472 		msr_all_available |= MSR_SPE;
473 #endif
474 
475 	return 0;
476 }
477 early_initcall(init_msr_all_available);
478 
479 void giveup_all(struct task_struct *tsk)
480 {
481 	unsigned long usermsr;
482 
483 	if (!tsk->thread.regs)
484 		return;
485 
486 	check_if_tm_restore_required(tsk);
487 
488 	usermsr = tsk->thread.regs->msr;
489 
490 	if ((usermsr & msr_all_available) == 0)
491 		return;
492 
493 	msr_check_and_set(msr_all_available);
494 
495 	WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
496 
497 #ifdef CONFIG_PPC_FPU
498 	if (usermsr & MSR_FP)
499 		__giveup_fpu(tsk);
500 #endif
501 #ifdef CONFIG_ALTIVEC
502 	if (usermsr & MSR_VEC)
503 		__giveup_altivec(tsk);
504 #endif
505 #ifdef CONFIG_SPE
506 	if (usermsr & MSR_SPE)
507 		__giveup_spe(tsk);
508 #endif
509 
510 	msr_check_and_clear(msr_all_available);
511 }
512 EXPORT_SYMBOL(giveup_all);
513 
514 /*
515  * The exception exit path calls restore_math() with interrupts hard disabled
516  * but the soft irq state not "reconciled". ftrace code that calls
517  * local_irq_save/restore causes warnings.
518  *
519  * Rather than complicate the exit path, just don't trace restore_math. This
520  * could be done by having ftrace entry code check for this un-reconciled
521  * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
522  * temporarily fix it up for the duration of the ftrace call.
523  */
524 void notrace restore_math(struct pt_regs *regs)
525 {
526 	unsigned long msr;
527 
528 	if (!MSR_TM_ACTIVE(regs->msr) &&
529 		!current->thread.load_fp && !loadvec(current->thread))
530 		return;
531 
532 	msr = regs->msr;
533 	msr_check_and_set(msr_all_available);
534 
535 	/*
536 	 * Only reload if the bit is not set in the user MSR, the bit BEING set
537 	 * indicates that the registers are hot
538 	 */
539 	if ((!(msr & MSR_FP)) && restore_fp(current))
540 		msr |= MSR_FP | current->thread.fpexc_mode;
541 
542 	if ((!(msr & MSR_VEC)) && restore_altivec(current))
543 		msr |= MSR_VEC;
544 
545 	if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
546 			restore_vsx(current)) {
547 		msr |= MSR_VSX;
548 	}
549 
550 	msr_check_and_clear(msr_all_available);
551 
552 	regs->msr = msr;
553 }
554 
555 static void save_all(struct task_struct *tsk)
556 {
557 	unsigned long usermsr;
558 
559 	if (!tsk->thread.regs)
560 		return;
561 
562 	usermsr = tsk->thread.regs->msr;
563 
564 	if ((usermsr & msr_all_available) == 0)
565 		return;
566 
567 	msr_check_and_set(msr_all_available);
568 
569 	WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
570 
571 	if (usermsr & MSR_FP)
572 		save_fpu(tsk);
573 
574 	if (usermsr & MSR_VEC)
575 		save_altivec(tsk);
576 
577 	if (usermsr & MSR_SPE)
578 		__giveup_spe(tsk);
579 
580 	msr_check_and_clear(msr_all_available);
581 	thread_pkey_regs_save(&tsk->thread);
582 }
583 
584 void flush_all_to_thread(struct task_struct *tsk)
585 {
586 	if (tsk->thread.regs) {
587 		preempt_disable();
588 		BUG_ON(tsk != current);
589 #ifdef CONFIG_SPE
590 		if (tsk->thread.regs->msr & MSR_SPE)
591 			tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
592 #endif
593 		save_all(tsk);
594 
595 		preempt_enable();
596 	}
597 }
598 EXPORT_SYMBOL(flush_all_to_thread);
599 
600 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
601 void do_send_trap(struct pt_regs *regs, unsigned long address,
602 		  unsigned long error_code, int breakpt)
603 {
604 	current->thread.trap_nr = TRAP_HWBKPT;
605 	if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
606 			11, SIGSEGV) == NOTIFY_STOP)
607 		return;
608 
609 	/* Deliver the signal to userspace */
610 	force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
611 				    (void __user *)address);
612 }
613 #else	/* !CONFIG_PPC_ADV_DEBUG_REGS */
614 void do_break (struct pt_regs *regs, unsigned long address,
615 		    unsigned long error_code)
616 {
617 	current->thread.trap_nr = TRAP_HWBKPT;
618 	if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
619 			11, SIGSEGV) == NOTIFY_STOP)
620 		return;
621 
622 	if (debugger_break_match(regs))
623 		return;
624 
625 	/* Clear the breakpoint */
626 	hw_breakpoint_disable();
627 
628 	/* Deliver the signal to userspace */
629 	force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address);
630 }
631 #endif	/* CONFIG_PPC_ADV_DEBUG_REGS */
632 
633 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
634 
635 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
636 /*
637  * Set the debug registers back to their default "safe" values.
638  */
639 static void set_debug_reg_defaults(struct thread_struct *thread)
640 {
641 	thread->debug.iac1 = thread->debug.iac2 = 0;
642 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
643 	thread->debug.iac3 = thread->debug.iac4 = 0;
644 #endif
645 	thread->debug.dac1 = thread->debug.dac2 = 0;
646 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
647 	thread->debug.dvc1 = thread->debug.dvc2 = 0;
648 #endif
649 	thread->debug.dbcr0 = 0;
650 #ifdef CONFIG_BOOKE
651 	/*
652 	 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
653 	 */
654 	thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
655 			DBCR1_IAC3US | DBCR1_IAC4US;
656 	/*
657 	 * Force Data Address Compare User/Supervisor bits to be User-only
658 	 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
659 	 */
660 	thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
661 #else
662 	thread->debug.dbcr1 = 0;
663 #endif
664 }
665 
666 static void prime_debug_regs(struct debug_reg *debug)
667 {
668 	/*
669 	 * We could have inherited MSR_DE from userspace, since
670 	 * it doesn't get cleared on exception entry.  Make sure
671 	 * MSR_DE is clear before we enable any debug events.
672 	 */
673 	mtmsr(mfmsr() & ~MSR_DE);
674 
675 	mtspr(SPRN_IAC1, debug->iac1);
676 	mtspr(SPRN_IAC2, debug->iac2);
677 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
678 	mtspr(SPRN_IAC3, debug->iac3);
679 	mtspr(SPRN_IAC4, debug->iac4);
680 #endif
681 	mtspr(SPRN_DAC1, debug->dac1);
682 	mtspr(SPRN_DAC2, debug->dac2);
683 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
684 	mtspr(SPRN_DVC1, debug->dvc1);
685 	mtspr(SPRN_DVC2, debug->dvc2);
686 #endif
687 	mtspr(SPRN_DBCR0, debug->dbcr0);
688 	mtspr(SPRN_DBCR1, debug->dbcr1);
689 #ifdef CONFIG_BOOKE
690 	mtspr(SPRN_DBCR2, debug->dbcr2);
691 #endif
692 }
693 /*
694  * Unless neither the old or new thread are making use of the
695  * debug registers, set the debug registers from the values
696  * stored in the new thread.
697  */
698 void switch_booke_debug_regs(struct debug_reg *new_debug)
699 {
700 	if ((current->thread.debug.dbcr0 & DBCR0_IDM)
701 		|| (new_debug->dbcr0 & DBCR0_IDM))
702 			prime_debug_regs(new_debug);
703 }
704 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
705 #else	/* !CONFIG_PPC_ADV_DEBUG_REGS */
706 #ifndef CONFIG_HAVE_HW_BREAKPOINT
707 static void set_breakpoint(struct arch_hw_breakpoint *brk)
708 {
709 	preempt_disable();
710 	__set_breakpoint(brk);
711 	preempt_enable();
712 }
713 
714 static void set_debug_reg_defaults(struct thread_struct *thread)
715 {
716 	thread->hw_brk.address = 0;
717 	thread->hw_brk.type = 0;
718 	thread->hw_brk.len = 0;
719 	thread->hw_brk.hw_len = 0;
720 	if (ppc_breakpoint_available())
721 		set_breakpoint(&thread->hw_brk);
722 }
723 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
724 #endif	/* CONFIG_PPC_ADV_DEBUG_REGS */
725 
726 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
727 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
728 {
729 	mtspr(SPRN_DAC1, dabr);
730 #ifdef CONFIG_PPC_47x
731 	isync();
732 #endif
733 	return 0;
734 }
735 #elif defined(CONFIG_PPC_BOOK3S)
736 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
737 {
738 	mtspr(SPRN_DABR, dabr);
739 	if (cpu_has_feature(CPU_FTR_DABRX))
740 		mtspr(SPRN_DABRX, dabrx);
741 	return 0;
742 }
743 #elif defined(CONFIG_PPC_8xx)
744 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
745 {
746 	unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
747 	unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
748 	unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
749 
750 	if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
751 		lctrl1 |= 0xa0000;
752 	else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
753 		lctrl1 |= 0xf0000;
754 	else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
755 		lctrl2 = 0;
756 
757 	mtspr(SPRN_LCTRL2, 0);
758 	mtspr(SPRN_CMPE, addr);
759 	mtspr(SPRN_CMPF, addr + 4);
760 	mtspr(SPRN_LCTRL1, lctrl1);
761 	mtspr(SPRN_LCTRL2, lctrl2);
762 
763 	return 0;
764 }
765 #else
766 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
767 {
768 	return -EINVAL;
769 }
770 #endif
771 
772 static inline int set_dabr(struct arch_hw_breakpoint *brk)
773 {
774 	unsigned long dabr, dabrx;
775 
776 	dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
777 	dabrx = ((brk->type >> 3) & 0x7);
778 
779 	if (ppc_md.set_dabr)
780 		return ppc_md.set_dabr(dabr, dabrx);
781 
782 	return __set_dabr(dabr, dabrx);
783 }
784 
785 void __set_breakpoint(struct arch_hw_breakpoint *brk)
786 {
787 	memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
788 
789 	if (dawr_enabled())
790 		// Power8 or later
791 		set_dawr(brk);
792 	else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
793 		// Power7 or earlier
794 		set_dabr(brk);
795 	else
796 		// Shouldn't happen due to higher level checks
797 		WARN_ON_ONCE(1);
798 }
799 
800 /* Check if we have DAWR or DABR hardware */
801 bool ppc_breakpoint_available(void)
802 {
803 	if (dawr_enabled())
804 		return true; /* POWER8 DAWR or POWER9 forced DAWR */
805 	if (cpu_has_feature(CPU_FTR_ARCH_207S))
806 		return false; /* POWER9 with DAWR disabled */
807 	/* DABR: Everything but POWER8 and POWER9 */
808 	return true;
809 }
810 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
811 
812 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
813 			      struct arch_hw_breakpoint *b)
814 {
815 	if (a->address != b->address)
816 		return false;
817 	if (a->type != b->type)
818 		return false;
819 	if (a->len != b->len)
820 		return false;
821 	/* no need to check hw_len. it's calculated from address and len */
822 	return true;
823 }
824 
825 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
826 
827 static inline bool tm_enabled(struct task_struct *tsk)
828 {
829 	return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
830 }
831 
832 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
833 {
834 	/*
835 	 * Use the current MSR TM suspended bit to track if we have
836 	 * checkpointed state outstanding.
837 	 * On signal delivery, we'd normally reclaim the checkpointed
838 	 * state to obtain stack pointer (see:get_tm_stackpointer()).
839 	 * This will then directly return to userspace without going
840 	 * through __switch_to(). However, if the stack frame is bad,
841 	 * we need to exit this thread which calls __switch_to() which
842 	 * will again attempt to reclaim the already saved tm state.
843 	 * Hence we need to check that we've not already reclaimed
844 	 * this state.
845 	 * We do this using the current MSR, rather tracking it in
846 	 * some specific thread_struct bit, as it has the additional
847 	 * benefit of checking for a potential TM bad thing exception.
848 	 */
849 	if (!MSR_TM_SUSPENDED(mfmsr()))
850 		return;
851 
852 	giveup_all(container_of(thr, struct task_struct, thread));
853 
854 	tm_reclaim(thr, cause);
855 
856 	/*
857 	 * If we are in a transaction and FP is off then we can't have
858 	 * used FP inside that transaction. Hence the checkpointed
859 	 * state is the same as the live state. We need to copy the
860 	 * live state to the checkpointed state so that when the
861 	 * transaction is restored, the checkpointed state is correct
862 	 * and the aborted transaction sees the correct state. We use
863 	 * ckpt_regs.msr here as that's what tm_reclaim will use to
864 	 * determine if it's going to write the checkpointed state or
865 	 * not. So either this will write the checkpointed registers,
866 	 * or reclaim will. Similarly for VMX.
867 	 */
868 	if ((thr->ckpt_regs.msr & MSR_FP) == 0)
869 		memcpy(&thr->ckfp_state, &thr->fp_state,
870 		       sizeof(struct thread_fp_state));
871 	if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
872 		memcpy(&thr->ckvr_state, &thr->vr_state,
873 		       sizeof(struct thread_vr_state));
874 }
875 
876 void tm_reclaim_current(uint8_t cause)
877 {
878 	tm_enable();
879 	tm_reclaim_thread(&current->thread, cause);
880 }
881 
882 static inline void tm_reclaim_task(struct task_struct *tsk)
883 {
884 	/* We have to work out if we're switching from/to a task that's in the
885 	 * middle of a transaction.
886 	 *
887 	 * In switching we need to maintain a 2nd register state as
888 	 * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
889 	 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
890 	 * ckvr_state
891 	 *
892 	 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
893 	 */
894 	struct thread_struct *thr = &tsk->thread;
895 
896 	if (!thr->regs)
897 		return;
898 
899 	if (!MSR_TM_ACTIVE(thr->regs->msr))
900 		goto out_and_saveregs;
901 
902 	WARN_ON(tm_suspend_disabled);
903 
904 	TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
905 		 "ccr=%lx, msr=%lx, trap=%lx)\n",
906 		 tsk->pid, thr->regs->nip,
907 		 thr->regs->ccr, thr->regs->msr,
908 		 thr->regs->trap);
909 
910 	tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
911 
912 	TM_DEBUG("--- tm_reclaim on pid %d complete\n",
913 		 tsk->pid);
914 
915 out_and_saveregs:
916 	/* Always save the regs here, even if a transaction's not active.
917 	 * This context-switches a thread's TM info SPRs.  We do it here to
918 	 * be consistent with the restore path (in recheckpoint) which
919 	 * cannot happen later in _switch().
920 	 */
921 	tm_save_sprs(thr);
922 }
923 
924 extern void __tm_recheckpoint(struct thread_struct *thread);
925 
926 void tm_recheckpoint(struct thread_struct *thread)
927 {
928 	unsigned long flags;
929 
930 	if (!(thread->regs->msr & MSR_TM))
931 		return;
932 
933 	/* We really can't be interrupted here as the TEXASR registers can't
934 	 * change and later in the trecheckpoint code, we have a userspace R1.
935 	 * So let's hard disable over this region.
936 	 */
937 	local_irq_save(flags);
938 	hard_irq_disable();
939 
940 	/* The TM SPRs are restored here, so that TEXASR.FS can be set
941 	 * before the trecheckpoint and no explosion occurs.
942 	 */
943 	tm_restore_sprs(thread);
944 
945 	__tm_recheckpoint(thread);
946 
947 	local_irq_restore(flags);
948 }
949 
950 static inline void tm_recheckpoint_new_task(struct task_struct *new)
951 {
952 	if (!cpu_has_feature(CPU_FTR_TM))
953 		return;
954 
955 	/* Recheckpoint the registers of the thread we're about to switch to.
956 	 *
957 	 * If the task was using FP, we non-lazily reload both the original and
958 	 * the speculative FP register states.  This is because the kernel
959 	 * doesn't see if/when a TM rollback occurs, so if we take an FP
960 	 * unavailable later, we are unable to determine which set of FP regs
961 	 * need to be restored.
962 	 */
963 	if (!tm_enabled(new))
964 		return;
965 
966 	if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
967 		tm_restore_sprs(&new->thread);
968 		return;
969 	}
970 	/* Recheckpoint to restore original checkpointed register state. */
971 	TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
972 		 new->pid, new->thread.regs->msr);
973 
974 	tm_recheckpoint(&new->thread);
975 
976 	/*
977 	 * The checkpointed state has been restored but the live state has
978 	 * not, ensure all the math functionality is turned off to trigger
979 	 * restore_math() to reload.
980 	 */
981 	new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
982 
983 	TM_DEBUG("*** tm_recheckpoint of pid %d complete "
984 		 "(kernel msr 0x%lx)\n",
985 		 new->pid, mfmsr());
986 }
987 
988 static inline void __switch_to_tm(struct task_struct *prev,
989 		struct task_struct *new)
990 {
991 	if (cpu_has_feature(CPU_FTR_TM)) {
992 		if (tm_enabled(prev) || tm_enabled(new))
993 			tm_enable();
994 
995 		if (tm_enabled(prev)) {
996 			prev->thread.load_tm++;
997 			tm_reclaim_task(prev);
998 			if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
999 				prev->thread.regs->msr &= ~MSR_TM;
1000 		}
1001 
1002 		tm_recheckpoint_new_task(new);
1003 	}
1004 }
1005 
1006 /*
1007  * This is called if we are on the way out to userspace and the
1008  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1009  * FP and/or vector state and does so if necessary.
1010  * If userspace is inside a transaction (whether active or
1011  * suspended) and FP/VMX/VSX instructions have ever been enabled
1012  * inside that transaction, then we have to keep them enabled
1013  * and keep the FP/VMX/VSX state loaded while ever the transaction
1014  * continues.  The reason is that if we didn't, and subsequently
1015  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1016  * we don't know whether it's the same transaction, and thus we
1017  * don't know which of the checkpointed state and the transactional
1018  * state to use.
1019  */
1020 void restore_tm_state(struct pt_regs *regs)
1021 {
1022 	unsigned long msr_diff;
1023 
1024 	/*
1025 	 * This is the only moment we should clear TIF_RESTORE_TM as
1026 	 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1027 	 * again, anything else could lead to an incorrect ckpt_msr being
1028 	 * saved and therefore incorrect signal contexts.
1029 	 */
1030 	clear_thread_flag(TIF_RESTORE_TM);
1031 	if (!MSR_TM_ACTIVE(regs->msr))
1032 		return;
1033 
1034 	msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1035 	msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1036 
1037 	/* Ensure that restore_math() will restore */
1038 	if (msr_diff & MSR_FP)
1039 		current->thread.load_fp = 1;
1040 #ifdef CONFIG_ALTIVEC
1041 	if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1042 		current->thread.load_vec = 1;
1043 #endif
1044 	restore_math(regs);
1045 
1046 	regs->msr |= msr_diff;
1047 }
1048 
1049 #else
1050 #define tm_recheckpoint_new_task(new)
1051 #define __switch_to_tm(prev, new)
1052 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1053 
1054 static inline void save_sprs(struct thread_struct *t)
1055 {
1056 #ifdef CONFIG_ALTIVEC
1057 	if (cpu_has_feature(CPU_FTR_ALTIVEC))
1058 		t->vrsave = mfspr(SPRN_VRSAVE);
1059 #endif
1060 #ifdef CONFIG_PPC_BOOK3S_64
1061 	if (cpu_has_feature(CPU_FTR_DSCR))
1062 		t->dscr = mfspr(SPRN_DSCR);
1063 
1064 	if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1065 		t->bescr = mfspr(SPRN_BESCR);
1066 		t->ebbhr = mfspr(SPRN_EBBHR);
1067 		t->ebbrr = mfspr(SPRN_EBBRR);
1068 
1069 		t->fscr = mfspr(SPRN_FSCR);
1070 
1071 		/*
1072 		 * Note that the TAR is not available for use in the kernel.
1073 		 * (To provide this, the TAR should be backed up/restored on
1074 		 * exception entry/exit instead, and be in pt_regs.  FIXME,
1075 		 * this should be in pt_regs anyway (for debug).)
1076 		 */
1077 		t->tar = mfspr(SPRN_TAR);
1078 	}
1079 #endif
1080 
1081 	thread_pkey_regs_save(t);
1082 }
1083 
1084 static inline void restore_sprs(struct thread_struct *old_thread,
1085 				struct thread_struct *new_thread)
1086 {
1087 #ifdef CONFIG_ALTIVEC
1088 	if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1089 	    old_thread->vrsave != new_thread->vrsave)
1090 		mtspr(SPRN_VRSAVE, new_thread->vrsave);
1091 #endif
1092 #ifdef CONFIG_PPC_BOOK3S_64
1093 	if (cpu_has_feature(CPU_FTR_DSCR)) {
1094 		u64 dscr = get_paca()->dscr_default;
1095 		if (new_thread->dscr_inherit)
1096 			dscr = new_thread->dscr;
1097 
1098 		if (old_thread->dscr != dscr)
1099 			mtspr(SPRN_DSCR, dscr);
1100 	}
1101 
1102 	if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1103 		if (old_thread->bescr != new_thread->bescr)
1104 			mtspr(SPRN_BESCR, new_thread->bescr);
1105 		if (old_thread->ebbhr != new_thread->ebbhr)
1106 			mtspr(SPRN_EBBHR, new_thread->ebbhr);
1107 		if (old_thread->ebbrr != new_thread->ebbrr)
1108 			mtspr(SPRN_EBBRR, new_thread->ebbrr);
1109 
1110 		if (old_thread->fscr != new_thread->fscr)
1111 			mtspr(SPRN_FSCR, new_thread->fscr);
1112 
1113 		if (old_thread->tar != new_thread->tar)
1114 			mtspr(SPRN_TAR, new_thread->tar);
1115 	}
1116 
1117 	if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1118 	    old_thread->tidr != new_thread->tidr)
1119 		mtspr(SPRN_TIDR, new_thread->tidr);
1120 #endif
1121 
1122 	thread_pkey_regs_restore(new_thread, old_thread);
1123 }
1124 
1125 struct task_struct *__switch_to(struct task_struct *prev,
1126 	struct task_struct *new)
1127 {
1128 	struct thread_struct *new_thread, *old_thread;
1129 	struct task_struct *last;
1130 #ifdef CONFIG_PPC_BOOK3S_64
1131 	struct ppc64_tlb_batch *batch;
1132 #endif
1133 
1134 	new_thread = &new->thread;
1135 	old_thread = &current->thread;
1136 
1137 	WARN_ON(!irqs_disabled());
1138 
1139 #ifdef CONFIG_PPC_BOOK3S_64
1140 	batch = this_cpu_ptr(&ppc64_tlb_batch);
1141 	if (batch->active) {
1142 		current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1143 		if (batch->index)
1144 			__flush_tlb_pending(batch);
1145 		batch->active = 0;
1146 	}
1147 #endif /* CONFIG_PPC_BOOK3S_64 */
1148 
1149 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1150 	switch_booke_debug_regs(&new->thread.debug);
1151 #else
1152 /*
1153  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1154  * schedule DABR
1155  */
1156 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1157 	if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1158 		__set_breakpoint(&new->thread.hw_brk);
1159 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1160 #endif
1161 
1162 	/*
1163 	 * We need to save SPRs before treclaim/trecheckpoint as these will
1164 	 * change a number of them.
1165 	 */
1166 	save_sprs(&prev->thread);
1167 
1168 	/* Save FPU, Altivec, VSX and SPE state */
1169 	giveup_all(prev);
1170 
1171 	__switch_to_tm(prev, new);
1172 
1173 	if (!radix_enabled()) {
1174 		/*
1175 		 * We can't take a PMU exception inside _switch() since there
1176 		 * is a window where the kernel stack SLB and the kernel stack
1177 		 * are out of sync. Hard disable here.
1178 		 */
1179 		hard_irq_disable();
1180 	}
1181 
1182 	/*
1183 	 * Call restore_sprs() before calling _switch(). If we move it after
1184 	 * _switch() then we miss out on calling it for new tasks. The reason
1185 	 * for this is we manually create a stack frame for new tasks that
1186 	 * directly returns through ret_from_fork() or
1187 	 * ret_from_kernel_thread(). See copy_thread() for details.
1188 	 */
1189 	restore_sprs(old_thread, new_thread);
1190 
1191 	last = _switch(old_thread, new_thread);
1192 
1193 #ifdef CONFIG_PPC_BOOK3S_64
1194 	if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1195 		current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1196 		batch = this_cpu_ptr(&ppc64_tlb_batch);
1197 		batch->active = 1;
1198 	}
1199 
1200 	if (current->thread.regs) {
1201 		restore_math(current->thread.regs);
1202 
1203 		/*
1204 		 * The copy-paste buffer can only store into foreign real
1205 		 * addresses, so unprivileged processes can not see the
1206 		 * data or use it in any way unless they have foreign real
1207 		 * mappings. If the new process has the foreign real address
1208 		 * mappings, we must issue a cp_abort to clear any state and
1209 		 * prevent snooping, corruption or a covert channel.
1210 		 */
1211 		if (current->thread.used_vas)
1212 			asm volatile(PPC_CP_ABORT);
1213 	}
1214 #endif /* CONFIG_PPC_BOOK3S_64 */
1215 
1216 	return last;
1217 }
1218 
1219 #define NR_INSN_TO_PRINT	16
1220 
1221 static void show_instructions(struct pt_regs *regs)
1222 {
1223 	int i;
1224 	unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1225 
1226 	printk("Instruction dump:");
1227 
1228 	for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1229 		int instr;
1230 
1231 		if (!(i % 8))
1232 			pr_cont("\n");
1233 
1234 #if !defined(CONFIG_BOOKE)
1235 		/* If executing with the IMMU off, adjust pc rather
1236 		 * than print XXXXXXXX.
1237 		 */
1238 		if (!(regs->msr & MSR_IR))
1239 			pc = (unsigned long)phys_to_virt(pc);
1240 #endif
1241 
1242 		if (!__kernel_text_address(pc) ||
1243 		    probe_kernel_address((const void *)pc, instr)) {
1244 			pr_cont("XXXXXXXX ");
1245 		} else {
1246 			if (regs->nip == pc)
1247 				pr_cont("<%08x> ", instr);
1248 			else
1249 				pr_cont("%08x ", instr);
1250 		}
1251 
1252 		pc += sizeof(int);
1253 	}
1254 
1255 	pr_cont("\n");
1256 }
1257 
1258 void show_user_instructions(struct pt_regs *regs)
1259 {
1260 	unsigned long pc;
1261 	int n = NR_INSN_TO_PRINT;
1262 	struct seq_buf s;
1263 	char buf[96]; /* enough for 8 times 9 + 2 chars */
1264 
1265 	pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1266 
1267 	/*
1268 	 * Make sure the NIP points at userspace, not kernel text/data or
1269 	 * elsewhere.
1270 	 */
1271 	if (!__access_ok(pc, NR_INSN_TO_PRINT * sizeof(int), USER_DS)) {
1272 		pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1273 			current->comm, current->pid);
1274 		return;
1275 	}
1276 
1277 	seq_buf_init(&s, buf, sizeof(buf));
1278 
1279 	while (n) {
1280 		int i;
1281 
1282 		seq_buf_clear(&s);
1283 
1284 		for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1285 			int instr;
1286 
1287 			if (probe_kernel_address((const void *)pc, instr)) {
1288 				seq_buf_printf(&s, "XXXXXXXX ");
1289 				continue;
1290 			}
1291 			seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1292 		}
1293 
1294 		if (!seq_buf_has_overflowed(&s))
1295 			pr_info("%s[%d]: code: %s\n", current->comm,
1296 				current->pid, s.buffer);
1297 	}
1298 }
1299 
1300 struct regbit {
1301 	unsigned long bit;
1302 	const char *name;
1303 };
1304 
1305 static struct regbit msr_bits[] = {
1306 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1307 	{MSR_SF,	"SF"},
1308 	{MSR_HV,	"HV"},
1309 #endif
1310 	{MSR_VEC,	"VEC"},
1311 	{MSR_VSX,	"VSX"},
1312 #ifdef CONFIG_BOOKE
1313 	{MSR_CE,	"CE"},
1314 #endif
1315 	{MSR_EE,	"EE"},
1316 	{MSR_PR,	"PR"},
1317 	{MSR_FP,	"FP"},
1318 	{MSR_ME,	"ME"},
1319 #ifdef CONFIG_BOOKE
1320 	{MSR_DE,	"DE"},
1321 #else
1322 	{MSR_SE,	"SE"},
1323 	{MSR_BE,	"BE"},
1324 #endif
1325 	{MSR_IR,	"IR"},
1326 	{MSR_DR,	"DR"},
1327 	{MSR_PMM,	"PMM"},
1328 #ifndef CONFIG_BOOKE
1329 	{MSR_RI,	"RI"},
1330 	{MSR_LE,	"LE"},
1331 #endif
1332 	{0,		NULL}
1333 };
1334 
1335 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1336 {
1337 	const char *s = "";
1338 
1339 	for (; bits->bit; ++bits)
1340 		if (val & bits->bit) {
1341 			pr_cont("%s%s", s, bits->name);
1342 			s = sep;
1343 		}
1344 }
1345 
1346 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1347 static struct regbit msr_tm_bits[] = {
1348 	{MSR_TS_T,	"T"},
1349 	{MSR_TS_S,	"S"},
1350 	{MSR_TM,	"E"},
1351 	{0,		NULL}
1352 };
1353 
1354 static void print_tm_bits(unsigned long val)
1355 {
1356 /*
1357  * This only prints something if at least one of the TM bit is set.
1358  * Inside the TM[], the output means:
1359  *   E: Enabled		(bit 32)
1360  *   S: Suspended	(bit 33)
1361  *   T: Transactional	(bit 34)
1362  */
1363 	if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1364 		pr_cont(",TM[");
1365 		print_bits(val, msr_tm_bits, "");
1366 		pr_cont("]");
1367 	}
1368 }
1369 #else
1370 static void print_tm_bits(unsigned long val) {}
1371 #endif
1372 
1373 static void print_msr_bits(unsigned long val)
1374 {
1375 	pr_cont("<");
1376 	print_bits(val, msr_bits, ",");
1377 	print_tm_bits(val);
1378 	pr_cont(">");
1379 }
1380 
1381 #ifdef CONFIG_PPC64
1382 #define REG		"%016lx"
1383 #define REGS_PER_LINE	4
1384 #define LAST_VOLATILE	13
1385 #else
1386 #define REG		"%08lx"
1387 #define REGS_PER_LINE	8
1388 #define LAST_VOLATILE	12
1389 #endif
1390 
1391 void show_regs(struct pt_regs * regs)
1392 {
1393 	int i, trap;
1394 
1395 	show_regs_print_info(KERN_DEFAULT);
1396 
1397 	printk("NIP:  "REG" LR: "REG" CTR: "REG"\n",
1398 	       regs->nip, regs->link, regs->ctr);
1399 	printk("REGS: %px TRAP: %04lx   %s  (%s)\n",
1400 	       regs, regs->trap, print_tainted(), init_utsname()->release);
1401 	printk("MSR:  "REG" ", regs->msr);
1402 	print_msr_bits(regs->msr);
1403 	pr_cont("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1404 	trap = TRAP(regs);
1405 	if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1406 		pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1407 	if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1408 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1409 		pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1410 #else
1411 		pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1412 #endif
1413 #ifdef CONFIG_PPC64
1414 	pr_cont("IRQMASK: %lx ", regs->softe);
1415 #endif
1416 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1417 	if (MSR_TM_ACTIVE(regs->msr))
1418 		pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1419 #endif
1420 
1421 	for (i = 0;  i < 32;  i++) {
1422 		if ((i % REGS_PER_LINE) == 0)
1423 			pr_cont("\nGPR%02d: ", i);
1424 		pr_cont(REG " ", regs->gpr[i]);
1425 		if (i == LAST_VOLATILE && !FULL_REGS(regs))
1426 			break;
1427 	}
1428 	pr_cont("\n");
1429 #ifdef CONFIG_KALLSYMS
1430 	/*
1431 	 * Lookup NIP late so we have the best change of getting the
1432 	 * above info out without failing
1433 	 */
1434 	printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1435 	printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1436 #endif
1437 	show_stack(current, (unsigned long *) regs->gpr[1]);
1438 	if (!user_mode(regs))
1439 		show_instructions(regs);
1440 }
1441 
1442 void flush_thread(void)
1443 {
1444 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1445 	flush_ptrace_hw_breakpoint(current);
1446 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1447 	set_debug_reg_defaults(&current->thread);
1448 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1449 }
1450 
1451 #ifdef CONFIG_PPC_BOOK3S_64
1452 void arch_setup_new_exec(void)
1453 {
1454 	if (radix_enabled())
1455 		return;
1456 	hash__setup_new_exec();
1457 }
1458 #endif
1459 
1460 int set_thread_uses_vas(void)
1461 {
1462 #ifdef CONFIG_PPC_BOOK3S_64
1463 	if (!cpu_has_feature(CPU_FTR_ARCH_300))
1464 		return -EINVAL;
1465 
1466 	current->thread.used_vas = 1;
1467 
1468 	/*
1469 	 * Even a process that has no foreign real address mapping can use
1470 	 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1471 	 * to clear any pending COPY and prevent a covert channel.
1472 	 *
1473 	 * __switch_to() will issue CP_ABORT on future context switches.
1474 	 */
1475 	asm volatile(PPC_CP_ABORT);
1476 
1477 #endif /* CONFIG_PPC_BOOK3S_64 */
1478 	return 0;
1479 }
1480 
1481 #ifdef CONFIG_PPC64
1482 /**
1483  * Assign a TIDR (thread ID) for task @t and set it in the thread
1484  * structure. For now, we only support setting TIDR for 'current' task.
1485  *
1486  * Since the TID value is a truncated form of it PID, it is possible
1487  * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1488  * that 2 threads share the same TID and are waiting, one of the following
1489  * cases will happen:
1490  *
1491  * 1. The correct thread is running, the wrong thread is not
1492  * In this situation, the correct thread is woken and proceeds to pass it's
1493  * condition check.
1494  *
1495  * 2. Neither threads are running
1496  * In this situation, neither thread will be woken. When scheduled, the waiting
1497  * threads will execute either a wait, which will return immediately, followed
1498  * by a condition check, which will pass for the correct thread and fail
1499  * for the wrong thread, or they will execute the condition check immediately.
1500  *
1501  * 3. The wrong thread is running, the correct thread is not
1502  * The wrong thread will be woken, but will fail it's condition check and
1503  * re-execute wait. The correct thread, when scheduled, will execute either
1504  * it's condition check (which will pass), or wait, which returns immediately
1505  * when called the first time after the thread is scheduled, followed by it's
1506  * condition check (which will pass).
1507  *
1508  * 4. Both threads are running
1509  * Both threads will be woken. The wrong thread will fail it's condition check
1510  * and execute another wait, while the correct thread will pass it's condition
1511  * check.
1512  *
1513  * @t: the task to set the thread ID for
1514  */
1515 int set_thread_tidr(struct task_struct *t)
1516 {
1517 	if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1518 		return -EINVAL;
1519 
1520 	if (t != current)
1521 		return -EINVAL;
1522 
1523 	if (t->thread.tidr)
1524 		return 0;
1525 
1526 	t->thread.tidr = (u16)task_pid_nr(t);
1527 	mtspr(SPRN_TIDR, t->thread.tidr);
1528 
1529 	return 0;
1530 }
1531 EXPORT_SYMBOL_GPL(set_thread_tidr);
1532 
1533 #endif /* CONFIG_PPC64 */
1534 
1535 void
1536 release_thread(struct task_struct *t)
1537 {
1538 }
1539 
1540 /*
1541  * this gets called so that we can store coprocessor state into memory and
1542  * copy the current task into the new thread.
1543  */
1544 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1545 {
1546 	flush_all_to_thread(src);
1547 	/*
1548 	 * Flush TM state out so we can copy it.  __switch_to_tm() does this
1549 	 * flush but it removes the checkpointed state from the current CPU and
1550 	 * transitions the CPU out of TM mode.  Hence we need to call
1551 	 * tm_recheckpoint_new_task() (on the same task) to restore the
1552 	 * checkpointed state back and the TM mode.
1553 	 *
1554 	 * Can't pass dst because it isn't ready. Doesn't matter, passing
1555 	 * dst is only important for __switch_to()
1556 	 */
1557 	__switch_to_tm(src, src);
1558 
1559 	*dst = *src;
1560 
1561 	clear_task_ebb(dst);
1562 
1563 	return 0;
1564 }
1565 
1566 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1567 {
1568 #ifdef CONFIG_PPC_BOOK3S_64
1569 	unsigned long sp_vsid;
1570 	unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1571 
1572 	if (radix_enabled())
1573 		return;
1574 
1575 	if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1576 		sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1577 			<< SLB_VSID_SHIFT_1T;
1578 	else
1579 		sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1580 			<< SLB_VSID_SHIFT;
1581 	sp_vsid |= SLB_VSID_KERNEL | llp;
1582 	p->thread.ksp_vsid = sp_vsid;
1583 #endif
1584 }
1585 
1586 /*
1587  * Copy a thread..
1588  */
1589 
1590 /*
1591  * Copy architecture-specific thread state
1592  */
1593 int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
1594 		unsigned long kthread_arg, struct task_struct *p,
1595 		unsigned long tls)
1596 {
1597 	struct pt_regs *childregs, *kregs;
1598 	extern void ret_from_fork(void);
1599 	extern void ret_from_kernel_thread(void);
1600 	void (*f)(void);
1601 	unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1602 	struct thread_info *ti = task_thread_info(p);
1603 
1604 	klp_init_thread_info(p);
1605 
1606 	/* Copy registers */
1607 	sp -= sizeof(struct pt_regs);
1608 	childregs = (struct pt_regs *) sp;
1609 	if (unlikely(p->flags & PF_KTHREAD)) {
1610 		/* kernel thread */
1611 		memset(childregs, 0, sizeof(struct pt_regs));
1612 		childregs->gpr[1] = sp + sizeof(struct pt_regs);
1613 		/* function */
1614 		if (usp)
1615 			childregs->gpr[14] = ppc_function_entry((void *)usp);
1616 #ifdef CONFIG_PPC64
1617 		clear_tsk_thread_flag(p, TIF_32BIT);
1618 		childregs->softe = IRQS_ENABLED;
1619 #endif
1620 		childregs->gpr[15] = kthread_arg;
1621 		p->thread.regs = NULL;	/* no user register state */
1622 		ti->flags |= _TIF_RESTOREALL;
1623 		f = ret_from_kernel_thread;
1624 	} else {
1625 		/* user thread */
1626 		struct pt_regs *regs = current_pt_regs();
1627 		CHECK_FULL_REGS(regs);
1628 		*childregs = *regs;
1629 		if (usp)
1630 			childregs->gpr[1] = usp;
1631 		p->thread.regs = childregs;
1632 		childregs->gpr[3] = 0;  /* Result from fork() */
1633 		if (clone_flags & CLONE_SETTLS) {
1634 #ifdef CONFIG_PPC64
1635 			if (!is_32bit_task())
1636 				childregs->gpr[13] = tls;
1637 			else
1638 #endif
1639 				childregs->gpr[2] = tls;
1640 		}
1641 
1642 		f = ret_from_fork;
1643 	}
1644 	childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1645 	sp -= STACK_FRAME_OVERHEAD;
1646 
1647 	/*
1648 	 * The way this works is that at some point in the future
1649 	 * some task will call _switch to switch to the new task.
1650 	 * That will pop off the stack frame created below and start
1651 	 * the new task running at ret_from_fork.  The new task will
1652 	 * do some house keeping and then return from the fork or clone
1653 	 * system call, using the stack frame created above.
1654 	 */
1655 	((unsigned long *)sp)[0] = 0;
1656 	sp -= sizeof(struct pt_regs);
1657 	kregs = (struct pt_regs *) sp;
1658 	sp -= STACK_FRAME_OVERHEAD;
1659 	p->thread.ksp = sp;
1660 #ifdef CONFIG_PPC32
1661 	p->thread.ksp_limit = (unsigned long)end_of_stack(p);
1662 #endif
1663 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1664 	p->thread.ptrace_bps[0] = NULL;
1665 #endif
1666 
1667 	p->thread.fp_save_area = NULL;
1668 #ifdef CONFIG_ALTIVEC
1669 	p->thread.vr_save_area = NULL;
1670 #endif
1671 
1672 	setup_ksp_vsid(p, sp);
1673 
1674 #ifdef CONFIG_PPC64
1675 	if (cpu_has_feature(CPU_FTR_DSCR)) {
1676 		p->thread.dscr_inherit = current->thread.dscr_inherit;
1677 		p->thread.dscr = mfspr(SPRN_DSCR);
1678 	}
1679 	if (cpu_has_feature(CPU_FTR_HAS_PPR))
1680 		childregs->ppr = DEFAULT_PPR;
1681 
1682 	p->thread.tidr = 0;
1683 #endif
1684 	kregs->nip = ppc_function_entry(f);
1685 	return 0;
1686 }
1687 
1688 void preload_new_slb_context(unsigned long start, unsigned long sp);
1689 
1690 /*
1691  * Set up a thread for executing a new program
1692  */
1693 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1694 {
1695 #ifdef CONFIG_PPC64
1696 	unsigned long load_addr = regs->gpr[2];	/* saved by ELF_PLAT_INIT */
1697 
1698 #ifdef CONFIG_PPC_BOOK3S_64
1699 	if (!radix_enabled())
1700 		preload_new_slb_context(start, sp);
1701 #endif
1702 #endif
1703 
1704 	/*
1705 	 * If we exec out of a kernel thread then thread.regs will not be
1706 	 * set.  Do it now.
1707 	 */
1708 	if (!current->thread.regs) {
1709 		struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1710 		current->thread.regs = regs - 1;
1711 	}
1712 
1713 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1714 	/*
1715 	 * Clear any transactional state, we're exec()ing. The cause is
1716 	 * not important as there will never be a recheckpoint so it's not
1717 	 * user visible.
1718 	 */
1719 	if (MSR_TM_SUSPENDED(mfmsr()))
1720 		tm_reclaim_current(0);
1721 #endif
1722 
1723 	memset(regs->gpr, 0, sizeof(regs->gpr));
1724 	regs->ctr = 0;
1725 	regs->link = 0;
1726 	regs->xer = 0;
1727 	regs->ccr = 0;
1728 	regs->gpr[1] = sp;
1729 
1730 	/*
1731 	 * We have just cleared all the nonvolatile GPRs, so make
1732 	 * FULL_REGS(regs) return true.  This is necessary to allow
1733 	 * ptrace to examine the thread immediately after exec.
1734 	 */
1735 	regs->trap &= ~1UL;
1736 
1737 #ifdef CONFIG_PPC32
1738 	regs->mq = 0;
1739 	regs->nip = start;
1740 	regs->msr = MSR_USER;
1741 #else
1742 	if (!is_32bit_task()) {
1743 		unsigned long entry;
1744 
1745 		if (is_elf2_task()) {
1746 			/* Look ma, no function descriptors! */
1747 			entry = start;
1748 
1749 			/*
1750 			 * Ulrich says:
1751 			 *   The latest iteration of the ABI requires that when
1752 			 *   calling a function (at its global entry point),
1753 			 *   the caller must ensure r12 holds the entry point
1754 			 *   address (so that the function can quickly
1755 			 *   establish addressability).
1756 			 */
1757 			regs->gpr[12] = start;
1758 			/* Make sure that's restored on entry to userspace. */
1759 			set_thread_flag(TIF_RESTOREALL);
1760 		} else {
1761 			unsigned long toc;
1762 
1763 			/* start is a relocated pointer to the function
1764 			 * descriptor for the elf _start routine.  The first
1765 			 * entry in the function descriptor is the entry
1766 			 * address of _start and the second entry is the TOC
1767 			 * value we need to use.
1768 			 */
1769 			__get_user(entry, (unsigned long __user *)start);
1770 			__get_user(toc, (unsigned long __user *)start+1);
1771 
1772 			/* Check whether the e_entry function descriptor entries
1773 			 * need to be relocated before we can use them.
1774 			 */
1775 			if (load_addr != 0) {
1776 				entry += load_addr;
1777 				toc   += load_addr;
1778 			}
1779 			regs->gpr[2] = toc;
1780 		}
1781 		regs->nip = entry;
1782 		regs->msr = MSR_USER64;
1783 	} else {
1784 		regs->nip = start;
1785 		regs->gpr[2] = 0;
1786 		regs->msr = MSR_USER32;
1787 	}
1788 #endif
1789 #ifdef CONFIG_VSX
1790 	current->thread.used_vsr = 0;
1791 #endif
1792 	current->thread.load_slb = 0;
1793 	current->thread.load_fp = 0;
1794 	memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1795 	current->thread.fp_save_area = NULL;
1796 #ifdef CONFIG_ALTIVEC
1797 	memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1798 	current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1799 	current->thread.vr_save_area = NULL;
1800 	current->thread.vrsave = 0;
1801 	current->thread.used_vr = 0;
1802 	current->thread.load_vec = 0;
1803 #endif /* CONFIG_ALTIVEC */
1804 #ifdef CONFIG_SPE
1805 	memset(current->thread.evr, 0, sizeof(current->thread.evr));
1806 	current->thread.acc = 0;
1807 	current->thread.spefscr = 0;
1808 	current->thread.used_spe = 0;
1809 #endif /* CONFIG_SPE */
1810 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1811 	current->thread.tm_tfhar = 0;
1812 	current->thread.tm_texasr = 0;
1813 	current->thread.tm_tfiar = 0;
1814 	current->thread.load_tm = 0;
1815 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1816 
1817 	thread_pkey_regs_init(&current->thread);
1818 }
1819 EXPORT_SYMBOL(start_thread);
1820 
1821 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1822 		| PR_FP_EXC_RES | PR_FP_EXC_INV)
1823 
1824 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1825 {
1826 	struct pt_regs *regs = tsk->thread.regs;
1827 
1828 	/* This is a bit hairy.  If we are an SPE enabled  processor
1829 	 * (have embedded fp) we store the IEEE exception enable flags in
1830 	 * fpexc_mode.  fpexc_mode is also used for setting FP exception
1831 	 * mode (asyn, precise, disabled) for 'Classic' FP. */
1832 	if (val & PR_FP_EXC_SW_ENABLE) {
1833 #ifdef CONFIG_SPE
1834 		if (cpu_has_feature(CPU_FTR_SPE)) {
1835 			/*
1836 			 * When the sticky exception bits are set
1837 			 * directly by userspace, it must call prctl
1838 			 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1839 			 * in the existing prctl settings) or
1840 			 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1841 			 * the bits being set).  <fenv.h> functions
1842 			 * saving and restoring the whole
1843 			 * floating-point environment need to do so
1844 			 * anyway to restore the prctl settings from
1845 			 * the saved environment.
1846 			 */
1847 			tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1848 			tsk->thread.fpexc_mode = val &
1849 				(PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1850 			return 0;
1851 		} else {
1852 			return -EINVAL;
1853 		}
1854 #else
1855 		return -EINVAL;
1856 #endif
1857 	}
1858 
1859 	/* on a CONFIG_SPE this does not hurt us.  The bits that
1860 	 * __pack_fe01 use do not overlap with bits used for
1861 	 * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1862 	 * on CONFIG_SPE implementations are reserved so writing to
1863 	 * them does not change anything */
1864 	if (val > PR_FP_EXC_PRECISE)
1865 		return -EINVAL;
1866 	tsk->thread.fpexc_mode = __pack_fe01(val);
1867 	if (regs != NULL && (regs->msr & MSR_FP) != 0)
1868 		regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1869 			| tsk->thread.fpexc_mode;
1870 	return 0;
1871 }
1872 
1873 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1874 {
1875 	unsigned int val;
1876 
1877 	if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1878 #ifdef CONFIG_SPE
1879 		if (cpu_has_feature(CPU_FTR_SPE)) {
1880 			/*
1881 			 * When the sticky exception bits are set
1882 			 * directly by userspace, it must call prctl
1883 			 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1884 			 * in the existing prctl settings) or
1885 			 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1886 			 * the bits being set).  <fenv.h> functions
1887 			 * saving and restoring the whole
1888 			 * floating-point environment need to do so
1889 			 * anyway to restore the prctl settings from
1890 			 * the saved environment.
1891 			 */
1892 			tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1893 			val = tsk->thread.fpexc_mode;
1894 		} else
1895 			return -EINVAL;
1896 #else
1897 		return -EINVAL;
1898 #endif
1899 	else
1900 		val = __unpack_fe01(tsk->thread.fpexc_mode);
1901 	return put_user(val, (unsigned int __user *) adr);
1902 }
1903 
1904 int set_endian(struct task_struct *tsk, unsigned int val)
1905 {
1906 	struct pt_regs *regs = tsk->thread.regs;
1907 
1908 	if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1909 	    (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1910 		return -EINVAL;
1911 
1912 	if (regs == NULL)
1913 		return -EINVAL;
1914 
1915 	if (val == PR_ENDIAN_BIG)
1916 		regs->msr &= ~MSR_LE;
1917 	else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1918 		regs->msr |= MSR_LE;
1919 	else
1920 		return -EINVAL;
1921 
1922 	return 0;
1923 }
1924 
1925 int get_endian(struct task_struct *tsk, unsigned long adr)
1926 {
1927 	struct pt_regs *regs = tsk->thread.regs;
1928 	unsigned int val;
1929 
1930 	if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1931 	    !cpu_has_feature(CPU_FTR_REAL_LE))
1932 		return -EINVAL;
1933 
1934 	if (regs == NULL)
1935 		return -EINVAL;
1936 
1937 	if (regs->msr & MSR_LE) {
1938 		if (cpu_has_feature(CPU_FTR_REAL_LE))
1939 			val = PR_ENDIAN_LITTLE;
1940 		else
1941 			val = PR_ENDIAN_PPC_LITTLE;
1942 	} else
1943 		val = PR_ENDIAN_BIG;
1944 
1945 	return put_user(val, (unsigned int __user *)adr);
1946 }
1947 
1948 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1949 {
1950 	tsk->thread.align_ctl = val;
1951 	return 0;
1952 }
1953 
1954 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1955 {
1956 	return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1957 }
1958 
1959 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1960 				  unsigned long nbytes)
1961 {
1962 	unsigned long stack_page;
1963 	unsigned long cpu = task_cpu(p);
1964 
1965 	stack_page = (unsigned long)hardirq_ctx[cpu];
1966 	if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1967 		return 1;
1968 
1969 	stack_page = (unsigned long)softirq_ctx[cpu];
1970 	if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1971 		return 1;
1972 
1973 	return 0;
1974 }
1975 
1976 int validate_sp(unsigned long sp, struct task_struct *p,
1977 		       unsigned long nbytes)
1978 {
1979 	unsigned long stack_page = (unsigned long)task_stack_page(p);
1980 
1981 	if (sp < THREAD_SIZE)
1982 		return 0;
1983 
1984 	if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1985 		return 1;
1986 
1987 	return valid_irq_stack(sp, p, nbytes);
1988 }
1989 
1990 EXPORT_SYMBOL(validate_sp);
1991 
1992 static unsigned long __get_wchan(struct task_struct *p)
1993 {
1994 	unsigned long ip, sp;
1995 	int count = 0;
1996 
1997 	if (!p || p == current || p->state == TASK_RUNNING)
1998 		return 0;
1999 
2000 	sp = p->thread.ksp;
2001 	if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2002 		return 0;
2003 
2004 	do {
2005 		sp = *(unsigned long *)sp;
2006 		if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2007 		    p->state == TASK_RUNNING)
2008 			return 0;
2009 		if (count > 0) {
2010 			ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2011 			if (!in_sched_functions(ip))
2012 				return ip;
2013 		}
2014 	} while (count++ < 16);
2015 	return 0;
2016 }
2017 
2018 unsigned long get_wchan(struct task_struct *p)
2019 {
2020 	unsigned long ret;
2021 
2022 	if (!try_get_task_stack(p))
2023 		return 0;
2024 
2025 	ret = __get_wchan(p);
2026 
2027 	put_task_stack(p);
2028 
2029 	return ret;
2030 }
2031 
2032 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2033 
2034 void show_stack(struct task_struct *tsk, unsigned long *stack)
2035 {
2036 	unsigned long sp, ip, lr, newsp;
2037 	int count = 0;
2038 	int firstframe = 1;
2039 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2040 	unsigned long ret_addr;
2041 	int ftrace_idx = 0;
2042 #endif
2043 
2044 	if (tsk == NULL)
2045 		tsk = current;
2046 
2047 	if (!try_get_task_stack(tsk))
2048 		return;
2049 
2050 	sp = (unsigned long) stack;
2051 	if (sp == 0) {
2052 		if (tsk == current)
2053 			sp = current_stack_pointer();
2054 		else
2055 			sp = tsk->thread.ksp;
2056 	}
2057 
2058 	lr = 0;
2059 	printk("Call Trace:\n");
2060 	do {
2061 		if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2062 			break;
2063 
2064 		stack = (unsigned long *) sp;
2065 		newsp = stack[0];
2066 		ip = stack[STACK_FRAME_LR_SAVE];
2067 		if (!firstframe || ip != lr) {
2068 			printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2069 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2070 			ret_addr = ftrace_graph_ret_addr(current,
2071 						&ftrace_idx, ip, stack);
2072 			if (ret_addr != ip)
2073 				pr_cont(" (%pS)", (void *)ret_addr);
2074 #endif
2075 			if (firstframe)
2076 				pr_cont(" (unreliable)");
2077 			pr_cont("\n");
2078 		}
2079 		firstframe = 0;
2080 
2081 		/*
2082 		 * See if this is an exception frame.
2083 		 * We look for the "regshere" marker in the current frame.
2084 		 */
2085 		if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2086 		    && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2087 			struct pt_regs *regs = (struct pt_regs *)
2088 				(sp + STACK_FRAME_OVERHEAD);
2089 			lr = regs->link;
2090 			printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
2091 			       regs->trap, (void *)regs->nip, (void *)lr);
2092 			firstframe = 1;
2093 		}
2094 
2095 		sp = newsp;
2096 	} while (count++ < kstack_depth_to_print);
2097 
2098 	put_task_stack(tsk);
2099 }
2100 
2101 #ifdef CONFIG_PPC64
2102 /* Called with hard IRQs off */
2103 void notrace __ppc64_runlatch_on(void)
2104 {
2105 	struct thread_info *ti = current_thread_info();
2106 
2107 	if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2108 		/*
2109 		 * Least significant bit (RUN) is the only writable bit of
2110 		 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2111 		 * earliest ISA where this is the case, but it's convenient.
2112 		 */
2113 		mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2114 	} else {
2115 		unsigned long ctrl;
2116 
2117 		/*
2118 		 * Some architectures (e.g., Cell) have writable fields other
2119 		 * than RUN, so do the read-modify-write.
2120 		 */
2121 		ctrl = mfspr(SPRN_CTRLF);
2122 		ctrl |= CTRL_RUNLATCH;
2123 		mtspr(SPRN_CTRLT, ctrl);
2124 	}
2125 
2126 	ti->local_flags |= _TLF_RUNLATCH;
2127 }
2128 
2129 /* Called with hard IRQs off */
2130 void notrace __ppc64_runlatch_off(void)
2131 {
2132 	struct thread_info *ti = current_thread_info();
2133 
2134 	ti->local_flags &= ~_TLF_RUNLATCH;
2135 
2136 	if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2137 		mtspr(SPRN_CTRLT, 0);
2138 	} else {
2139 		unsigned long ctrl;
2140 
2141 		ctrl = mfspr(SPRN_CTRLF);
2142 		ctrl &= ~CTRL_RUNLATCH;
2143 		mtspr(SPRN_CTRLT, ctrl);
2144 	}
2145 }
2146 #endif /* CONFIG_PPC64 */
2147 
2148 unsigned long arch_align_stack(unsigned long sp)
2149 {
2150 	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2151 		sp -= get_random_int() & ~PAGE_MASK;
2152 	return sp & ~0xf;
2153 }
2154 
2155 static inline unsigned long brk_rnd(void)
2156 {
2157         unsigned long rnd = 0;
2158 
2159 	/* 8MB for 32bit, 1GB for 64bit */
2160 	if (is_32bit_task())
2161 		rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2162 	else
2163 		rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2164 
2165 	return rnd << PAGE_SHIFT;
2166 }
2167 
2168 unsigned long arch_randomize_brk(struct mm_struct *mm)
2169 {
2170 	unsigned long base = mm->brk;
2171 	unsigned long ret;
2172 
2173 #ifdef CONFIG_PPC_BOOK3S_64
2174 	/*
2175 	 * If we are using 1TB segments and we are allowed to randomise
2176 	 * the heap, we can put it above 1TB so it is backed by a 1TB
2177 	 * segment. Otherwise the heap will be in the bottom 1TB
2178 	 * which always uses 256MB segments and this may result in a
2179 	 * performance penalty. We don't need to worry about radix. For
2180 	 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2181 	 */
2182 	if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2183 		base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2184 #endif
2185 
2186 	ret = PAGE_ALIGN(base + brk_rnd());
2187 
2188 	if (ret < mm->brk)
2189 		return mm->brk;
2190 
2191 	return ret;
2192 }
2193 
2194