1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 6 * Paul Mackerras (paulus@cs.anu.edu.au) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/prctl.h> 29 #include <linux/init_task.h> 30 #include <linux/export.h> 31 #include <linux/kallsyms.h> 32 #include <linux/mqueue.h> 33 #include <linux/hardirq.h> 34 #include <linux/utsname.h> 35 #include <linux/ftrace.h> 36 #include <linux/kernel_stat.h> 37 #include <linux/personality.h> 38 #include <linux/random.h> 39 #include <linux/hw_breakpoint.h> 40 41 #include <asm/pgtable.h> 42 #include <asm/uaccess.h> 43 #include <asm/io.h> 44 #include <asm/processor.h> 45 #include <asm/mmu.h> 46 #include <asm/prom.h> 47 #include <asm/machdep.h> 48 #include <asm/time.h> 49 #include <asm/runlatch.h> 50 #include <asm/syscalls.h> 51 #include <asm/switch_to.h> 52 #include <asm/tm.h> 53 #include <asm/debug.h> 54 #ifdef CONFIG_PPC64 55 #include <asm/firmware.h> 56 #endif 57 #include <asm/code-patching.h> 58 #include <linux/kprobes.h> 59 #include <linux/kdebug.h> 60 61 /* Transactional Memory debug */ 62 #ifdef TM_DEBUG_SW 63 #define TM_DEBUG(x...) printk(KERN_INFO x) 64 #else 65 #define TM_DEBUG(x...) do { } while(0) 66 #endif 67 68 extern unsigned long _get_SP(void); 69 70 #ifndef CONFIG_SMP 71 struct task_struct *last_task_used_math = NULL; 72 struct task_struct *last_task_used_altivec = NULL; 73 struct task_struct *last_task_used_vsx = NULL; 74 struct task_struct *last_task_used_spe = NULL; 75 #endif 76 77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 78 void giveup_fpu_maybe_transactional(struct task_struct *tsk) 79 { 80 /* 81 * If we are saving the current thread's registers, and the 82 * thread is in a transactional state, set the TIF_RESTORE_TM 83 * bit so that we know to restore the registers before 84 * returning to userspace. 85 */ 86 if (tsk == current && tsk->thread.regs && 87 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 88 !test_thread_flag(TIF_RESTORE_TM)) { 89 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; 90 set_thread_flag(TIF_RESTORE_TM); 91 } 92 93 giveup_fpu(tsk); 94 } 95 96 void giveup_altivec_maybe_transactional(struct task_struct *tsk) 97 { 98 /* 99 * If we are saving the current thread's registers, and the 100 * thread is in a transactional state, set the TIF_RESTORE_TM 101 * bit so that we know to restore the registers before 102 * returning to userspace. 103 */ 104 if (tsk == current && tsk->thread.regs && 105 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 106 !test_thread_flag(TIF_RESTORE_TM)) { 107 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; 108 set_thread_flag(TIF_RESTORE_TM); 109 } 110 111 giveup_altivec(tsk); 112 } 113 114 #else 115 #define giveup_fpu_maybe_transactional(tsk) giveup_fpu(tsk) 116 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk) 117 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 118 119 #ifdef CONFIG_PPC_FPU 120 /* 121 * Make sure the floating-point register state in the 122 * the thread_struct is up to date for task tsk. 123 */ 124 void flush_fp_to_thread(struct task_struct *tsk) 125 { 126 if (tsk->thread.regs) { 127 /* 128 * We need to disable preemption here because if we didn't, 129 * another process could get scheduled after the regs->msr 130 * test but before we have finished saving the FP registers 131 * to the thread_struct. That process could take over the 132 * FPU, and then when we get scheduled again we would store 133 * bogus values for the remaining FP registers. 134 */ 135 preempt_disable(); 136 if (tsk->thread.regs->msr & MSR_FP) { 137 #ifdef CONFIG_SMP 138 /* 139 * This should only ever be called for current or 140 * for a stopped child process. Since we save away 141 * the FP register state on context switch on SMP, 142 * there is something wrong if a stopped child appears 143 * to still have its FP state in the CPU registers. 144 */ 145 BUG_ON(tsk != current); 146 #endif 147 giveup_fpu_maybe_transactional(tsk); 148 } 149 preempt_enable(); 150 } 151 } 152 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 153 #endif /* CONFIG_PPC_FPU */ 154 155 void enable_kernel_fp(void) 156 { 157 WARN_ON(preemptible()); 158 159 #ifdef CONFIG_SMP 160 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) 161 giveup_fpu_maybe_transactional(current); 162 else 163 giveup_fpu(NULL); /* just enables FP for kernel */ 164 #else 165 giveup_fpu_maybe_transactional(last_task_used_math); 166 #endif /* CONFIG_SMP */ 167 } 168 EXPORT_SYMBOL(enable_kernel_fp); 169 170 #ifdef CONFIG_ALTIVEC 171 void enable_kernel_altivec(void) 172 { 173 WARN_ON(preemptible()); 174 175 #ifdef CONFIG_SMP 176 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) 177 giveup_altivec_maybe_transactional(current); 178 else 179 giveup_altivec_notask(); 180 #else 181 giveup_altivec_maybe_transactional(last_task_used_altivec); 182 #endif /* CONFIG_SMP */ 183 } 184 EXPORT_SYMBOL(enable_kernel_altivec); 185 186 /* 187 * Make sure the VMX/Altivec register state in the 188 * the thread_struct is up to date for task tsk. 189 */ 190 void flush_altivec_to_thread(struct task_struct *tsk) 191 { 192 if (tsk->thread.regs) { 193 preempt_disable(); 194 if (tsk->thread.regs->msr & MSR_VEC) { 195 #ifdef CONFIG_SMP 196 BUG_ON(tsk != current); 197 #endif 198 giveup_altivec_maybe_transactional(tsk); 199 } 200 preempt_enable(); 201 } 202 } 203 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 204 #endif /* CONFIG_ALTIVEC */ 205 206 #ifdef CONFIG_VSX 207 #if 0 208 /* not currently used, but some crazy RAID module might want to later */ 209 void enable_kernel_vsx(void) 210 { 211 WARN_ON(preemptible()); 212 213 #ifdef CONFIG_SMP 214 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) 215 giveup_vsx(current); 216 else 217 giveup_vsx(NULL); /* just enable vsx for kernel - force */ 218 #else 219 giveup_vsx(last_task_used_vsx); 220 #endif /* CONFIG_SMP */ 221 } 222 EXPORT_SYMBOL(enable_kernel_vsx); 223 #endif 224 225 void giveup_vsx(struct task_struct *tsk) 226 { 227 giveup_fpu_maybe_transactional(tsk); 228 giveup_altivec_maybe_transactional(tsk); 229 __giveup_vsx(tsk); 230 } 231 232 void flush_vsx_to_thread(struct task_struct *tsk) 233 { 234 if (tsk->thread.regs) { 235 preempt_disable(); 236 if (tsk->thread.regs->msr & MSR_VSX) { 237 #ifdef CONFIG_SMP 238 BUG_ON(tsk != current); 239 #endif 240 giveup_vsx(tsk); 241 } 242 preempt_enable(); 243 } 244 } 245 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 246 #endif /* CONFIG_VSX */ 247 248 #ifdef CONFIG_SPE 249 250 void enable_kernel_spe(void) 251 { 252 WARN_ON(preemptible()); 253 254 #ifdef CONFIG_SMP 255 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) 256 giveup_spe(current); 257 else 258 giveup_spe(NULL); /* just enable SPE for kernel - force */ 259 #else 260 giveup_spe(last_task_used_spe); 261 #endif /* __SMP __ */ 262 } 263 EXPORT_SYMBOL(enable_kernel_spe); 264 265 void flush_spe_to_thread(struct task_struct *tsk) 266 { 267 if (tsk->thread.regs) { 268 preempt_disable(); 269 if (tsk->thread.regs->msr & MSR_SPE) { 270 #ifdef CONFIG_SMP 271 BUG_ON(tsk != current); 272 #endif 273 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 274 giveup_spe(tsk); 275 } 276 preempt_enable(); 277 } 278 } 279 #endif /* CONFIG_SPE */ 280 281 #ifndef CONFIG_SMP 282 /* 283 * If we are doing lazy switching of CPU state (FP, altivec or SPE), 284 * and the current task has some state, discard it. 285 */ 286 void discard_lazy_cpu_state(void) 287 { 288 preempt_disable(); 289 if (last_task_used_math == current) 290 last_task_used_math = NULL; 291 #ifdef CONFIG_ALTIVEC 292 if (last_task_used_altivec == current) 293 last_task_used_altivec = NULL; 294 #endif /* CONFIG_ALTIVEC */ 295 #ifdef CONFIG_VSX 296 if (last_task_used_vsx == current) 297 last_task_used_vsx = NULL; 298 #endif /* CONFIG_VSX */ 299 #ifdef CONFIG_SPE 300 if (last_task_used_spe == current) 301 last_task_used_spe = NULL; 302 #endif 303 preempt_enable(); 304 } 305 #endif /* CONFIG_SMP */ 306 307 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 308 void do_send_trap(struct pt_regs *regs, unsigned long address, 309 unsigned long error_code, int signal_code, int breakpt) 310 { 311 siginfo_t info; 312 313 current->thread.trap_nr = signal_code; 314 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 315 11, SIGSEGV) == NOTIFY_STOP) 316 return; 317 318 /* Deliver the signal to userspace */ 319 info.si_signo = SIGTRAP; 320 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 321 info.si_code = signal_code; 322 info.si_addr = (void __user *)address; 323 force_sig_info(SIGTRAP, &info, current); 324 } 325 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 326 void do_break (struct pt_regs *regs, unsigned long address, 327 unsigned long error_code) 328 { 329 siginfo_t info; 330 331 current->thread.trap_nr = TRAP_HWBKPT; 332 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 333 11, SIGSEGV) == NOTIFY_STOP) 334 return; 335 336 if (debugger_break_match(regs)) 337 return; 338 339 /* Clear the breakpoint */ 340 hw_breakpoint_disable(); 341 342 /* Deliver the signal to userspace */ 343 info.si_signo = SIGTRAP; 344 info.si_errno = 0; 345 info.si_code = TRAP_HWBKPT; 346 info.si_addr = (void __user *)address; 347 force_sig_info(SIGTRAP, &info, current); 348 } 349 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 350 351 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 352 353 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 354 /* 355 * Set the debug registers back to their default "safe" values. 356 */ 357 static void set_debug_reg_defaults(struct thread_struct *thread) 358 { 359 thread->debug.iac1 = thread->debug.iac2 = 0; 360 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 361 thread->debug.iac3 = thread->debug.iac4 = 0; 362 #endif 363 thread->debug.dac1 = thread->debug.dac2 = 0; 364 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 365 thread->debug.dvc1 = thread->debug.dvc2 = 0; 366 #endif 367 thread->debug.dbcr0 = 0; 368 #ifdef CONFIG_BOOKE 369 /* 370 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 371 */ 372 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 373 DBCR1_IAC3US | DBCR1_IAC4US; 374 /* 375 * Force Data Address Compare User/Supervisor bits to be User-only 376 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 377 */ 378 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 379 #else 380 thread->debug.dbcr1 = 0; 381 #endif 382 } 383 384 static void prime_debug_regs(struct debug_reg *debug) 385 { 386 /* 387 * We could have inherited MSR_DE from userspace, since 388 * it doesn't get cleared on exception entry. Make sure 389 * MSR_DE is clear before we enable any debug events. 390 */ 391 mtmsr(mfmsr() & ~MSR_DE); 392 393 mtspr(SPRN_IAC1, debug->iac1); 394 mtspr(SPRN_IAC2, debug->iac2); 395 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 396 mtspr(SPRN_IAC3, debug->iac3); 397 mtspr(SPRN_IAC4, debug->iac4); 398 #endif 399 mtspr(SPRN_DAC1, debug->dac1); 400 mtspr(SPRN_DAC2, debug->dac2); 401 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 402 mtspr(SPRN_DVC1, debug->dvc1); 403 mtspr(SPRN_DVC2, debug->dvc2); 404 #endif 405 mtspr(SPRN_DBCR0, debug->dbcr0); 406 mtspr(SPRN_DBCR1, debug->dbcr1); 407 #ifdef CONFIG_BOOKE 408 mtspr(SPRN_DBCR2, debug->dbcr2); 409 #endif 410 } 411 /* 412 * Unless neither the old or new thread are making use of the 413 * debug registers, set the debug registers from the values 414 * stored in the new thread. 415 */ 416 void switch_booke_debug_regs(struct debug_reg *new_debug) 417 { 418 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 419 || (new_debug->dbcr0 & DBCR0_IDM)) 420 prime_debug_regs(new_debug); 421 } 422 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 423 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 424 #ifndef CONFIG_HAVE_HW_BREAKPOINT 425 static void set_debug_reg_defaults(struct thread_struct *thread) 426 { 427 thread->hw_brk.address = 0; 428 thread->hw_brk.type = 0; 429 set_breakpoint(&thread->hw_brk); 430 } 431 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 432 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 433 434 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 435 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 436 { 437 mtspr(SPRN_DAC1, dabr); 438 #ifdef CONFIG_PPC_47x 439 isync(); 440 #endif 441 return 0; 442 } 443 #elif defined(CONFIG_PPC_BOOK3S) 444 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 445 { 446 mtspr(SPRN_DABR, dabr); 447 if (cpu_has_feature(CPU_FTR_DABRX)) 448 mtspr(SPRN_DABRX, dabrx); 449 return 0; 450 } 451 #else 452 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 453 { 454 return -EINVAL; 455 } 456 #endif 457 458 static inline int set_dabr(struct arch_hw_breakpoint *brk) 459 { 460 unsigned long dabr, dabrx; 461 462 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 463 dabrx = ((brk->type >> 3) & 0x7); 464 465 if (ppc_md.set_dabr) 466 return ppc_md.set_dabr(dabr, dabrx); 467 468 return __set_dabr(dabr, dabrx); 469 } 470 471 static inline int set_dawr(struct arch_hw_breakpoint *brk) 472 { 473 unsigned long dawr, dawrx, mrd; 474 475 dawr = brk->address; 476 477 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 478 << (63 - 58); //* read/write bits */ 479 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 480 << (63 - 59); //* translate */ 481 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 482 >> 3; //* PRIM bits */ 483 /* dawr length is stored in field MDR bits 48:53. Matches range in 484 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 485 0b111111=64DW. 486 brk->len is in bytes. 487 This aligns up to double word size, shifts and does the bias. 488 */ 489 mrd = ((brk->len + 7) >> 3) - 1; 490 dawrx |= (mrd & 0x3f) << (63 - 53); 491 492 if (ppc_md.set_dawr) 493 return ppc_md.set_dawr(dawr, dawrx); 494 mtspr(SPRN_DAWR, dawr); 495 mtspr(SPRN_DAWRX, dawrx); 496 return 0; 497 } 498 499 void __set_breakpoint(struct arch_hw_breakpoint *brk) 500 { 501 __get_cpu_var(current_brk) = *brk; 502 503 if (cpu_has_feature(CPU_FTR_DAWR)) 504 set_dawr(brk); 505 else 506 set_dabr(brk); 507 } 508 509 void set_breakpoint(struct arch_hw_breakpoint *brk) 510 { 511 preempt_disable(); 512 __set_breakpoint(brk); 513 preempt_enable(); 514 } 515 516 #ifdef CONFIG_PPC64 517 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 518 #endif 519 520 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 521 struct arch_hw_breakpoint *b) 522 { 523 if (a->address != b->address) 524 return false; 525 if (a->type != b->type) 526 return false; 527 if (a->len != b->len) 528 return false; 529 return true; 530 } 531 532 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 533 static void tm_reclaim_thread(struct thread_struct *thr, 534 struct thread_info *ti, uint8_t cause) 535 { 536 unsigned long msr_diff = 0; 537 538 /* 539 * If FP/VSX registers have been already saved to the 540 * thread_struct, move them to the transact_fp array. 541 * We clear the TIF_RESTORE_TM bit since after the reclaim 542 * the thread will no longer be transactional. 543 */ 544 if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { 545 msr_diff = thr->tm_orig_msr & ~thr->regs->msr; 546 if (msr_diff & MSR_FP) 547 memcpy(&thr->transact_fp, &thr->fp_state, 548 sizeof(struct thread_fp_state)); 549 if (msr_diff & MSR_VEC) 550 memcpy(&thr->transact_vr, &thr->vr_state, 551 sizeof(struct thread_vr_state)); 552 clear_ti_thread_flag(ti, TIF_RESTORE_TM); 553 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; 554 } 555 556 tm_reclaim(thr, thr->regs->msr, cause); 557 558 /* Having done the reclaim, we now have the checkpointed 559 * FP/VSX values in the registers. These might be valid 560 * even if we have previously called enable_kernel_fp() or 561 * flush_fp_to_thread(), so update thr->regs->msr to 562 * indicate their current validity. 563 */ 564 thr->regs->msr |= msr_diff; 565 } 566 567 void tm_reclaim_current(uint8_t cause) 568 { 569 tm_enable(); 570 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 571 } 572 573 static inline void tm_reclaim_task(struct task_struct *tsk) 574 { 575 /* We have to work out if we're switching from/to a task that's in the 576 * middle of a transaction. 577 * 578 * In switching we need to maintain a 2nd register state as 579 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 580 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 581 * (current) FPRs into oldtask->thread.transact_fpr[]. 582 * 583 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 584 */ 585 struct thread_struct *thr = &tsk->thread; 586 587 if (!thr->regs) 588 return; 589 590 if (!MSR_TM_ACTIVE(thr->regs->msr)) 591 goto out_and_saveregs; 592 593 /* Stash the original thread MSR, as giveup_fpu et al will 594 * modify it. We hold onto it to see whether the task used 595 * FP & vector regs. If the TIF_RESTORE_TM flag is set, 596 * tm_orig_msr is already set. 597 */ 598 if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) 599 thr->tm_orig_msr = thr->regs->msr; 600 601 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 602 "ccr=%lx, msr=%lx, trap=%lx)\n", 603 tsk->pid, thr->regs->nip, 604 thr->regs->ccr, thr->regs->msr, 605 thr->regs->trap); 606 607 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 608 609 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 610 tsk->pid); 611 612 out_and_saveregs: 613 /* Always save the regs here, even if a transaction's not active. 614 * This context-switches a thread's TM info SPRs. We do it here to 615 * be consistent with the restore path (in recheckpoint) which 616 * cannot happen later in _switch(). 617 */ 618 tm_save_sprs(thr); 619 } 620 621 extern void __tm_recheckpoint(struct thread_struct *thread, 622 unsigned long orig_msr); 623 624 void tm_recheckpoint(struct thread_struct *thread, 625 unsigned long orig_msr) 626 { 627 unsigned long flags; 628 629 /* We really can't be interrupted here as the TEXASR registers can't 630 * change and later in the trecheckpoint code, we have a userspace R1. 631 * So let's hard disable over this region. 632 */ 633 local_irq_save(flags); 634 hard_irq_disable(); 635 636 /* The TM SPRs are restored here, so that TEXASR.FS can be set 637 * before the trecheckpoint and no explosion occurs. 638 */ 639 tm_restore_sprs(thread); 640 641 __tm_recheckpoint(thread, orig_msr); 642 643 local_irq_restore(flags); 644 } 645 646 static inline void tm_recheckpoint_new_task(struct task_struct *new) 647 { 648 unsigned long msr; 649 650 if (!cpu_has_feature(CPU_FTR_TM)) 651 return; 652 653 /* Recheckpoint the registers of the thread we're about to switch to. 654 * 655 * If the task was using FP, we non-lazily reload both the original and 656 * the speculative FP register states. This is because the kernel 657 * doesn't see if/when a TM rollback occurs, so if we take an FP 658 * unavoidable later, we are unable to determine which set of FP regs 659 * need to be restored. 660 */ 661 if (!new->thread.regs) 662 return; 663 664 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 665 tm_restore_sprs(&new->thread); 666 return; 667 } 668 msr = new->thread.tm_orig_msr; 669 /* Recheckpoint to restore original checkpointed register state. */ 670 TM_DEBUG("*** tm_recheckpoint of pid %d " 671 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 672 new->pid, new->thread.regs->msr, msr); 673 674 /* This loads the checkpointed FP/VEC state, if used */ 675 tm_recheckpoint(&new->thread, msr); 676 677 /* This loads the speculative FP/VEC state, if used */ 678 if (msr & MSR_FP) { 679 do_load_up_transact_fpu(&new->thread); 680 new->thread.regs->msr |= 681 (MSR_FP | new->thread.fpexc_mode); 682 } 683 #ifdef CONFIG_ALTIVEC 684 if (msr & MSR_VEC) { 685 do_load_up_transact_altivec(&new->thread); 686 new->thread.regs->msr |= MSR_VEC; 687 } 688 #endif 689 /* We may as well turn on VSX too since all the state is restored now */ 690 if (msr & MSR_VSX) 691 new->thread.regs->msr |= MSR_VSX; 692 693 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 694 "(kernel msr 0x%lx)\n", 695 new->pid, mfmsr()); 696 } 697 698 static inline void __switch_to_tm(struct task_struct *prev) 699 { 700 if (cpu_has_feature(CPU_FTR_TM)) { 701 tm_enable(); 702 tm_reclaim_task(prev); 703 } 704 } 705 706 /* 707 * This is called if we are on the way out to userspace and the 708 * TIF_RESTORE_TM flag is set. It checks if we need to reload 709 * FP and/or vector state and does so if necessary. 710 * If userspace is inside a transaction (whether active or 711 * suspended) and FP/VMX/VSX instructions have ever been enabled 712 * inside that transaction, then we have to keep them enabled 713 * and keep the FP/VMX/VSX state loaded while ever the transaction 714 * continues. The reason is that if we didn't, and subsequently 715 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 716 * we don't know whether it's the same transaction, and thus we 717 * don't know which of the checkpointed state and the transactional 718 * state to use. 719 */ 720 void restore_tm_state(struct pt_regs *regs) 721 { 722 unsigned long msr_diff; 723 724 clear_thread_flag(TIF_RESTORE_TM); 725 if (!MSR_TM_ACTIVE(regs->msr)) 726 return; 727 728 msr_diff = current->thread.tm_orig_msr & ~regs->msr; 729 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 730 if (msr_diff & MSR_FP) { 731 fp_enable(); 732 load_fp_state(¤t->thread.fp_state); 733 regs->msr |= current->thread.fpexc_mode; 734 } 735 if (msr_diff & MSR_VEC) { 736 vec_enable(); 737 load_vr_state(¤t->thread.vr_state); 738 } 739 regs->msr |= msr_diff; 740 } 741 742 #else 743 #define tm_recheckpoint_new_task(new) 744 #define __switch_to_tm(prev) 745 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 746 747 struct task_struct *__switch_to(struct task_struct *prev, 748 struct task_struct *new) 749 { 750 struct thread_struct *new_thread, *old_thread; 751 struct task_struct *last; 752 #ifdef CONFIG_PPC_BOOK3S_64 753 struct ppc64_tlb_batch *batch; 754 #endif 755 756 WARN_ON(!irqs_disabled()); 757 758 /* Back up the TAR and DSCR across context switches. 759 * Note that the TAR is not available for use in the kernel. (To 760 * provide this, the TAR should be backed up/restored on exception 761 * entry/exit instead, and be in pt_regs. FIXME, this should be in 762 * pt_regs anyway (for debug).) 763 * Save the TAR and DSCR here before we do treclaim/trecheckpoint as 764 * these will change them. 765 */ 766 save_early_sprs(&prev->thread); 767 768 __switch_to_tm(prev); 769 770 #ifdef CONFIG_SMP 771 /* avoid complexity of lazy save/restore of fpu 772 * by just saving it every time we switch out if 773 * this task used the fpu during the last quantum. 774 * 775 * If it tries to use the fpu again, it'll trap and 776 * reload its fp regs. So we don't have to do a restore 777 * every switch, just a save. 778 * -- Cort 779 */ 780 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) 781 giveup_fpu(prev); 782 #ifdef CONFIG_ALTIVEC 783 /* 784 * If the previous thread used altivec in the last quantum 785 * (thus changing altivec regs) then save them. 786 * We used to check the VRSAVE register but not all apps 787 * set it, so we don't rely on it now (and in fact we need 788 * to save & restore VSCR even if VRSAVE == 0). -- paulus 789 * 790 * On SMP we always save/restore altivec regs just to avoid the 791 * complexity of changing processors. 792 * -- Cort 793 */ 794 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) 795 giveup_altivec(prev); 796 #endif /* CONFIG_ALTIVEC */ 797 #ifdef CONFIG_VSX 798 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) 799 /* VMX and FPU registers are already save here */ 800 __giveup_vsx(prev); 801 #endif /* CONFIG_VSX */ 802 #ifdef CONFIG_SPE 803 /* 804 * If the previous thread used spe in the last quantum 805 * (thus changing spe regs) then save them. 806 * 807 * On SMP we always save/restore spe regs just to avoid the 808 * complexity of changing processors. 809 */ 810 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) 811 giveup_spe(prev); 812 #endif /* CONFIG_SPE */ 813 814 #else /* CONFIG_SMP */ 815 #ifdef CONFIG_ALTIVEC 816 /* Avoid the trap. On smp this this never happens since 817 * we don't set last_task_used_altivec -- Cort 818 */ 819 if (new->thread.regs && last_task_used_altivec == new) 820 new->thread.regs->msr |= MSR_VEC; 821 #endif /* CONFIG_ALTIVEC */ 822 #ifdef CONFIG_VSX 823 if (new->thread.regs && last_task_used_vsx == new) 824 new->thread.regs->msr |= MSR_VSX; 825 #endif /* CONFIG_VSX */ 826 #ifdef CONFIG_SPE 827 /* Avoid the trap. On smp this this never happens since 828 * we don't set last_task_used_spe 829 */ 830 if (new->thread.regs && last_task_used_spe == new) 831 new->thread.regs->msr |= MSR_SPE; 832 #endif /* CONFIG_SPE */ 833 834 #endif /* CONFIG_SMP */ 835 836 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 837 switch_booke_debug_regs(&new->thread.debug); 838 #else 839 /* 840 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 841 * schedule DABR 842 */ 843 #ifndef CONFIG_HAVE_HW_BREAKPOINT 844 if (unlikely(!hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) 845 __set_breakpoint(&new->thread.hw_brk); 846 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 847 #endif 848 849 850 new_thread = &new->thread; 851 old_thread = ¤t->thread; 852 853 #ifdef CONFIG_PPC64 854 /* 855 * Collect processor utilization data per process 856 */ 857 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 858 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); 859 long unsigned start_tb, current_tb; 860 start_tb = old_thread->start_tb; 861 cu->current_tb = current_tb = mfspr(SPRN_PURR); 862 old_thread->accum_tb += (current_tb - start_tb); 863 new_thread->start_tb = current_tb; 864 } 865 #endif /* CONFIG_PPC64 */ 866 867 #ifdef CONFIG_PPC_BOOK3S_64 868 batch = &__get_cpu_var(ppc64_tlb_batch); 869 if (batch->active) { 870 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 871 if (batch->index) 872 __flush_tlb_pending(batch); 873 batch->active = 0; 874 } 875 #endif /* CONFIG_PPC_BOOK3S_64 */ 876 877 /* 878 * We can't take a PMU exception inside _switch() since there is a 879 * window where the kernel stack SLB and the kernel stack are out 880 * of sync. Hard disable here. 881 */ 882 hard_irq_disable(); 883 884 tm_recheckpoint_new_task(new); 885 886 last = _switch(old_thread, new_thread); 887 888 #ifdef CONFIG_PPC_BOOK3S_64 889 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 890 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 891 batch = &__get_cpu_var(ppc64_tlb_batch); 892 batch->active = 1; 893 } 894 #endif /* CONFIG_PPC_BOOK3S_64 */ 895 896 return last; 897 } 898 899 static int instructions_to_print = 16; 900 901 static void show_instructions(struct pt_regs *regs) 902 { 903 int i; 904 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 905 sizeof(int)); 906 907 printk("Instruction dump:"); 908 909 for (i = 0; i < instructions_to_print; i++) { 910 int instr; 911 912 if (!(i % 8)) 913 printk("\n"); 914 915 #if !defined(CONFIG_BOOKE) 916 /* If executing with the IMMU off, adjust pc rather 917 * than print XXXXXXXX. 918 */ 919 if (!(regs->msr & MSR_IR)) 920 pc = (unsigned long)phys_to_virt(pc); 921 #endif 922 923 /* We use __get_user here *only* to avoid an OOPS on a 924 * bad address because the pc *should* only be a 925 * kernel address. 926 */ 927 if (!__kernel_text_address(pc) || 928 __get_user(instr, (unsigned int __user *)pc)) { 929 printk(KERN_CONT "XXXXXXXX "); 930 } else { 931 if (regs->nip == pc) 932 printk(KERN_CONT "<%08x> ", instr); 933 else 934 printk(KERN_CONT "%08x ", instr); 935 } 936 937 pc += sizeof(int); 938 } 939 940 printk("\n"); 941 } 942 943 static struct regbit { 944 unsigned long bit; 945 const char *name; 946 } msr_bits[] = { 947 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 948 {MSR_SF, "SF"}, 949 {MSR_HV, "HV"}, 950 #endif 951 {MSR_VEC, "VEC"}, 952 {MSR_VSX, "VSX"}, 953 #ifdef CONFIG_BOOKE 954 {MSR_CE, "CE"}, 955 #endif 956 {MSR_EE, "EE"}, 957 {MSR_PR, "PR"}, 958 {MSR_FP, "FP"}, 959 {MSR_ME, "ME"}, 960 #ifdef CONFIG_BOOKE 961 {MSR_DE, "DE"}, 962 #else 963 {MSR_SE, "SE"}, 964 {MSR_BE, "BE"}, 965 #endif 966 {MSR_IR, "IR"}, 967 {MSR_DR, "DR"}, 968 {MSR_PMM, "PMM"}, 969 #ifndef CONFIG_BOOKE 970 {MSR_RI, "RI"}, 971 {MSR_LE, "LE"}, 972 #endif 973 {0, NULL} 974 }; 975 976 static void printbits(unsigned long val, struct regbit *bits) 977 { 978 const char *sep = ""; 979 980 printk("<"); 981 for (; bits->bit; ++bits) 982 if (val & bits->bit) { 983 printk("%s%s", sep, bits->name); 984 sep = ","; 985 } 986 printk(">"); 987 } 988 989 #ifdef CONFIG_PPC64 990 #define REG "%016lx" 991 #define REGS_PER_LINE 4 992 #define LAST_VOLATILE 13 993 #else 994 #define REG "%08lx" 995 #define REGS_PER_LINE 8 996 #define LAST_VOLATILE 12 997 #endif 998 999 void show_regs(struct pt_regs * regs) 1000 { 1001 int i, trap; 1002 1003 show_regs_print_info(KERN_DEFAULT); 1004 1005 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 1006 regs->nip, regs->link, regs->ctr); 1007 printk("REGS: %p TRAP: %04lx %s (%s)\n", 1008 regs, regs->trap, print_tainted(), init_utsname()->release); 1009 printk("MSR: "REG" ", regs->msr); 1010 printbits(regs->msr, msr_bits); 1011 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1012 trap = TRAP(regs); 1013 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1014 printk("CFAR: "REG" ", regs->orig_gpr3); 1015 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1016 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1017 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1018 #else 1019 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1020 #endif 1021 #ifdef CONFIG_PPC64 1022 printk("SOFTE: %ld ", regs->softe); 1023 #endif 1024 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1025 if (MSR_TM_ACTIVE(regs->msr)) 1026 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1027 #endif 1028 1029 for (i = 0; i < 32; i++) { 1030 if ((i % REGS_PER_LINE) == 0) 1031 printk("\nGPR%02d: ", i); 1032 printk(REG " ", regs->gpr[i]); 1033 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1034 break; 1035 } 1036 printk("\n"); 1037 #ifdef CONFIG_KALLSYMS 1038 /* 1039 * Lookup NIP late so we have the best change of getting the 1040 * above info out without failing 1041 */ 1042 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1043 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1044 #endif 1045 show_stack(current, (unsigned long *) regs->gpr[1]); 1046 if (!user_mode(regs)) 1047 show_instructions(regs); 1048 } 1049 1050 void exit_thread(void) 1051 { 1052 discard_lazy_cpu_state(); 1053 } 1054 1055 void flush_thread(void) 1056 { 1057 discard_lazy_cpu_state(); 1058 1059 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1060 flush_ptrace_hw_breakpoint(current); 1061 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1062 set_debug_reg_defaults(¤t->thread); 1063 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1064 } 1065 1066 void 1067 release_thread(struct task_struct *t) 1068 { 1069 } 1070 1071 /* 1072 * this gets called so that we can store coprocessor state into memory and 1073 * copy the current task into the new thread. 1074 */ 1075 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1076 { 1077 flush_fp_to_thread(src); 1078 flush_altivec_to_thread(src); 1079 flush_vsx_to_thread(src); 1080 flush_spe_to_thread(src); 1081 /* 1082 * Flush TM state out so we can copy it. __switch_to_tm() does this 1083 * flush but it removes the checkpointed state from the current CPU and 1084 * transitions the CPU out of TM mode. Hence we need to call 1085 * tm_recheckpoint_new_task() (on the same task) to restore the 1086 * checkpointed state back and the TM mode. 1087 */ 1088 __switch_to_tm(src); 1089 tm_recheckpoint_new_task(src); 1090 1091 *dst = *src; 1092 1093 clear_task_ebb(dst); 1094 1095 return 0; 1096 } 1097 1098 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1099 { 1100 #ifdef CONFIG_PPC_STD_MMU_64 1101 unsigned long sp_vsid; 1102 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1103 1104 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1105 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1106 << SLB_VSID_SHIFT_1T; 1107 else 1108 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1109 << SLB_VSID_SHIFT; 1110 sp_vsid |= SLB_VSID_KERNEL | llp; 1111 p->thread.ksp_vsid = sp_vsid; 1112 #endif 1113 } 1114 1115 /* 1116 * Copy a thread.. 1117 */ 1118 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */ 1119 1120 int copy_thread(unsigned long clone_flags, unsigned long usp, 1121 unsigned long arg, struct task_struct *p) 1122 { 1123 struct pt_regs *childregs, *kregs; 1124 extern void ret_from_fork(void); 1125 extern void ret_from_kernel_thread(void); 1126 void (*f)(void); 1127 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1128 1129 /* Copy registers */ 1130 sp -= sizeof(struct pt_regs); 1131 childregs = (struct pt_regs *) sp; 1132 if (unlikely(p->flags & PF_KTHREAD)) { 1133 struct thread_info *ti = (void *)task_stack_page(p); 1134 memset(childregs, 0, sizeof(struct pt_regs)); 1135 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1136 /* function */ 1137 if (usp) 1138 childregs->gpr[14] = ppc_function_entry((void *)usp); 1139 #ifdef CONFIG_PPC64 1140 clear_tsk_thread_flag(p, TIF_32BIT); 1141 childregs->softe = 1; 1142 #endif 1143 childregs->gpr[15] = arg; 1144 p->thread.regs = NULL; /* no user register state */ 1145 ti->flags |= _TIF_RESTOREALL; 1146 f = ret_from_kernel_thread; 1147 } else { 1148 struct pt_regs *regs = current_pt_regs(); 1149 CHECK_FULL_REGS(regs); 1150 *childregs = *regs; 1151 if (usp) 1152 childregs->gpr[1] = usp; 1153 p->thread.regs = childregs; 1154 childregs->gpr[3] = 0; /* Result from fork() */ 1155 if (clone_flags & CLONE_SETTLS) { 1156 #ifdef CONFIG_PPC64 1157 if (!is_32bit_task()) 1158 childregs->gpr[13] = childregs->gpr[6]; 1159 else 1160 #endif 1161 childregs->gpr[2] = childregs->gpr[6]; 1162 } 1163 1164 f = ret_from_fork; 1165 } 1166 sp -= STACK_FRAME_OVERHEAD; 1167 1168 /* 1169 * The way this works is that at some point in the future 1170 * some task will call _switch to switch to the new task. 1171 * That will pop off the stack frame created below and start 1172 * the new task running at ret_from_fork. The new task will 1173 * do some house keeping and then return from the fork or clone 1174 * system call, using the stack frame created above. 1175 */ 1176 ((unsigned long *)sp)[0] = 0; 1177 sp -= sizeof(struct pt_regs); 1178 kregs = (struct pt_regs *) sp; 1179 sp -= STACK_FRAME_OVERHEAD; 1180 p->thread.ksp = sp; 1181 #ifdef CONFIG_PPC32 1182 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1183 _ALIGN_UP(sizeof(struct thread_info), 16); 1184 #endif 1185 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1186 p->thread.ptrace_bps[0] = NULL; 1187 #endif 1188 1189 p->thread.fp_save_area = NULL; 1190 #ifdef CONFIG_ALTIVEC 1191 p->thread.vr_save_area = NULL; 1192 #endif 1193 1194 setup_ksp_vsid(p, sp); 1195 1196 #ifdef CONFIG_PPC64 1197 if (cpu_has_feature(CPU_FTR_DSCR)) { 1198 p->thread.dscr_inherit = current->thread.dscr_inherit; 1199 p->thread.dscr = current->thread.dscr; 1200 } 1201 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1202 p->thread.ppr = INIT_PPR; 1203 #endif 1204 kregs->nip = ppc_function_entry(f); 1205 return 0; 1206 } 1207 1208 /* 1209 * Set up a thread for executing a new program 1210 */ 1211 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1212 { 1213 #ifdef CONFIG_PPC64 1214 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1215 #endif 1216 1217 /* 1218 * If we exec out of a kernel thread then thread.regs will not be 1219 * set. Do it now. 1220 */ 1221 if (!current->thread.regs) { 1222 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1223 current->thread.regs = regs - 1; 1224 } 1225 1226 memset(regs->gpr, 0, sizeof(regs->gpr)); 1227 regs->ctr = 0; 1228 regs->link = 0; 1229 regs->xer = 0; 1230 regs->ccr = 0; 1231 regs->gpr[1] = sp; 1232 1233 /* 1234 * We have just cleared all the nonvolatile GPRs, so make 1235 * FULL_REGS(regs) return true. This is necessary to allow 1236 * ptrace to examine the thread immediately after exec. 1237 */ 1238 regs->trap &= ~1UL; 1239 1240 #ifdef CONFIG_PPC32 1241 regs->mq = 0; 1242 regs->nip = start; 1243 regs->msr = MSR_USER; 1244 #else 1245 if (!is_32bit_task()) { 1246 unsigned long entry; 1247 1248 if (is_elf2_task()) { 1249 /* Look ma, no function descriptors! */ 1250 entry = start; 1251 1252 /* 1253 * Ulrich says: 1254 * The latest iteration of the ABI requires that when 1255 * calling a function (at its global entry point), 1256 * the caller must ensure r12 holds the entry point 1257 * address (so that the function can quickly 1258 * establish addressability). 1259 */ 1260 regs->gpr[12] = start; 1261 /* Make sure that's restored on entry to userspace. */ 1262 set_thread_flag(TIF_RESTOREALL); 1263 } else { 1264 unsigned long toc; 1265 1266 /* start is a relocated pointer to the function 1267 * descriptor for the elf _start routine. The first 1268 * entry in the function descriptor is the entry 1269 * address of _start and the second entry is the TOC 1270 * value we need to use. 1271 */ 1272 __get_user(entry, (unsigned long __user *)start); 1273 __get_user(toc, (unsigned long __user *)start+1); 1274 1275 /* Check whether the e_entry function descriptor entries 1276 * need to be relocated before we can use them. 1277 */ 1278 if (load_addr != 0) { 1279 entry += load_addr; 1280 toc += load_addr; 1281 } 1282 regs->gpr[2] = toc; 1283 } 1284 regs->nip = entry; 1285 regs->msr = MSR_USER64; 1286 } else { 1287 regs->nip = start; 1288 regs->gpr[2] = 0; 1289 regs->msr = MSR_USER32; 1290 } 1291 #endif 1292 discard_lazy_cpu_state(); 1293 #ifdef CONFIG_VSX 1294 current->thread.used_vsr = 0; 1295 #endif 1296 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1297 current->thread.fp_save_area = NULL; 1298 #ifdef CONFIG_ALTIVEC 1299 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1300 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1301 current->thread.vr_save_area = NULL; 1302 current->thread.vrsave = 0; 1303 current->thread.used_vr = 0; 1304 #endif /* CONFIG_ALTIVEC */ 1305 #ifdef CONFIG_SPE 1306 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1307 current->thread.acc = 0; 1308 current->thread.spefscr = 0; 1309 current->thread.used_spe = 0; 1310 #endif /* CONFIG_SPE */ 1311 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1312 if (cpu_has_feature(CPU_FTR_TM)) 1313 regs->msr |= MSR_TM; 1314 current->thread.tm_tfhar = 0; 1315 current->thread.tm_texasr = 0; 1316 current->thread.tm_tfiar = 0; 1317 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1318 } 1319 1320 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1321 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1322 1323 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1324 { 1325 struct pt_regs *regs = tsk->thread.regs; 1326 1327 /* This is a bit hairy. If we are an SPE enabled processor 1328 * (have embedded fp) we store the IEEE exception enable flags in 1329 * fpexc_mode. fpexc_mode is also used for setting FP exception 1330 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1331 if (val & PR_FP_EXC_SW_ENABLE) { 1332 #ifdef CONFIG_SPE 1333 if (cpu_has_feature(CPU_FTR_SPE)) { 1334 /* 1335 * When the sticky exception bits are set 1336 * directly by userspace, it must call prctl 1337 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1338 * in the existing prctl settings) or 1339 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1340 * the bits being set). <fenv.h> functions 1341 * saving and restoring the whole 1342 * floating-point environment need to do so 1343 * anyway to restore the prctl settings from 1344 * the saved environment. 1345 */ 1346 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1347 tsk->thread.fpexc_mode = val & 1348 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1349 return 0; 1350 } else { 1351 return -EINVAL; 1352 } 1353 #else 1354 return -EINVAL; 1355 #endif 1356 } 1357 1358 /* on a CONFIG_SPE this does not hurt us. The bits that 1359 * __pack_fe01 use do not overlap with bits used for 1360 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1361 * on CONFIG_SPE implementations are reserved so writing to 1362 * them does not change anything */ 1363 if (val > PR_FP_EXC_PRECISE) 1364 return -EINVAL; 1365 tsk->thread.fpexc_mode = __pack_fe01(val); 1366 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1367 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1368 | tsk->thread.fpexc_mode; 1369 return 0; 1370 } 1371 1372 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1373 { 1374 unsigned int val; 1375 1376 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1377 #ifdef CONFIG_SPE 1378 if (cpu_has_feature(CPU_FTR_SPE)) { 1379 /* 1380 * When the sticky exception bits are set 1381 * directly by userspace, it must call prctl 1382 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1383 * in the existing prctl settings) or 1384 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1385 * the bits being set). <fenv.h> functions 1386 * saving and restoring the whole 1387 * floating-point environment need to do so 1388 * anyway to restore the prctl settings from 1389 * the saved environment. 1390 */ 1391 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1392 val = tsk->thread.fpexc_mode; 1393 } else 1394 return -EINVAL; 1395 #else 1396 return -EINVAL; 1397 #endif 1398 else 1399 val = __unpack_fe01(tsk->thread.fpexc_mode); 1400 return put_user(val, (unsigned int __user *) adr); 1401 } 1402 1403 int set_endian(struct task_struct *tsk, unsigned int val) 1404 { 1405 struct pt_regs *regs = tsk->thread.regs; 1406 1407 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1408 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1409 return -EINVAL; 1410 1411 if (regs == NULL) 1412 return -EINVAL; 1413 1414 if (val == PR_ENDIAN_BIG) 1415 regs->msr &= ~MSR_LE; 1416 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1417 regs->msr |= MSR_LE; 1418 else 1419 return -EINVAL; 1420 1421 return 0; 1422 } 1423 1424 int get_endian(struct task_struct *tsk, unsigned long adr) 1425 { 1426 struct pt_regs *regs = tsk->thread.regs; 1427 unsigned int val; 1428 1429 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1430 !cpu_has_feature(CPU_FTR_REAL_LE)) 1431 return -EINVAL; 1432 1433 if (regs == NULL) 1434 return -EINVAL; 1435 1436 if (regs->msr & MSR_LE) { 1437 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1438 val = PR_ENDIAN_LITTLE; 1439 else 1440 val = PR_ENDIAN_PPC_LITTLE; 1441 } else 1442 val = PR_ENDIAN_BIG; 1443 1444 return put_user(val, (unsigned int __user *)adr); 1445 } 1446 1447 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1448 { 1449 tsk->thread.align_ctl = val; 1450 return 0; 1451 } 1452 1453 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1454 { 1455 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1456 } 1457 1458 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1459 unsigned long nbytes) 1460 { 1461 unsigned long stack_page; 1462 unsigned long cpu = task_cpu(p); 1463 1464 /* 1465 * Avoid crashing if the stack has overflowed and corrupted 1466 * task_cpu(p), which is in the thread_info struct. 1467 */ 1468 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1469 stack_page = (unsigned long) hardirq_ctx[cpu]; 1470 if (sp >= stack_page + sizeof(struct thread_struct) 1471 && sp <= stack_page + THREAD_SIZE - nbytes) 1472 return 1; 1473 1474 stack_page = (unsigned long) softirq_ctx[cpu]; 1475 if (sp >= stack_page + sizeof(struct thread_struct) 1476 && sp <= stack_page + THREAD_SIZE - nbytes) 1477 return 1; 1478 } 1479 return 0; 1480 } 1481 1482 int validate_sp(unsigned long sp, struct task_struct *p, 1483 unsigned long nbytes) 1484 { 1485 unsigned long stack_page = (unsigned long)task_stack_page(p); 1486 1487 if (sp >= stack_page + sizeof(struct thread_struct) 1488 && sp <= stack_page + THREAD_SIZE - nbytes) 1489 return 1; 1490 1491 return valid_irq_stack(sp, p, nbytes); 1492 } 1493 1494 EXPORT_SYMBOL(validate_sp); 1495 1496 unsigned long get_wchan(struct task_struct *p) 1497 { 1498 unsigned long ip, sp; 1499 int count = 0; 1500 1501 if (!p || p == current || p->state == TASK_RUNNING) 1502 return 0; 1503 1504 sp = p->thread.ksp; 1505 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1506 return 0; 1507 1508 do { 1509 sp = *(unsigned long *)sp; 1510 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1511 return 0; 1512 if (count > 0) { 1513 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1514 if (!in_sched_functions(ip)) 1515 return ip; 1516 } 1517 } while (count++ < 16); 1518 return 0; 1519 } 1520 1521 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1522 1523 void show_stack(struct task_struct *tsk, unsigned long *stack) 1524 { 1525 unsigned long sp, ip, lr, newsp; 1526 int count = 0; 1527 int firstframe = 1; 1528 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1529 int curr_frame = current->curr_ret_stack; 1530 extern void return_to_handler(void); 1531 unsigned long rth = (unsigned long)return_to_handler; 1532 unsigned long mrth = -1; 1533 #ifdef CONFIG_PPC64 1534 extern void mod_return_to_handler(void); 1535 rth = *(unsigned long *)rth; 1536 mrth = (unsigned long)mod_return_to_handler; 1537 mrth = *(unsigned long *)mrth; 1538 #endif 1539 #endif 1540 1541 sp = (unsigned long) stack; 1542 if (tsk == NULL) 1543 tsk = current; 1544 if (sp == 0) { 1545 if (tsk == current) 1546 asm("mr %0,1" : "=r" (sp)); 1547 else 1548 sp = tsk->thread.ksp; 1549 } 1550 1551 lr = 0; 1552 printk("Call Trace:\n"); 1553 do { 1554 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1555 return; 1556 1557 stack = (unsigned long *) sp; 1558 newsp = stack[0]; 1559 ip = stack[STACK_FRAME_LR_SAVE]; 1560 if (!firstframe || ip != lr) { 1561 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1562 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1563 if ((ip == rth || ip == mrth) && curr_frame >= 0) { 1564 printk(" (%pS)", 1565 (void *)current->ret_stack[curr_frame].ret); 1566 curr_frame--; 1567 } 1568 #endif 1569 if (firstframe) 1570 printk(" (unreliable)"); 1571 printk("\n"); 1572 } 1573 firstframe = 0; 1574 1575 /* 1576 * See if this is an exception frame. 1577 * We look for the "regshere" marker in the current frame. 1578 */ 1579 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1580 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1581 struct pt_regs *regs = (struct pt_regs *) 1582 (sp + STACK_FRAME_OVERHEAD); 1583 lr = regs->link; 1584 printk("--- interrupt: %lx at %pS\n LR = %pS\n", 1585 regs->trap, (void *)regs->nip, (void *)lr); 1586 firstframe = 1; 1587 } 1588 1589 sp = newsp; 1590 } while (count++ < kstack_depth_to_print); 1591 } 1592 1593 #ifdef CONFIG_PPC64 1594 /* Called with hard IRQs off */ 1595 void notrace __ppc64_runlatch_on(void) 1596 { 1597 struct thread_info *ti = current_thread_info(); 1598 unsigned long ctrl; 1599 1600 ctrl = mfspr(SPRN_CTRLF); 1601 ctrl |= CTRL_RUNLATCH; 1602 mtspr(SPRN_CTRLT, ctrl); 1603 1604 ti->local_flags |= _TLF_RUNLATCH; 1605 } 1606 1607 /* Called with hard IRQs off */ 1608 void notrace __ppc64_runlatch_off(void) 1609 { 1610 struct thread_info *ti = current_thread_info(); 1611 unsigned long ctrl; 1612 1613 ti->local_flags &= ~_TLF_RUNLATCH; 1614 1615 ctrl = mfspr(SPRN_CTRLF); 1616 ctrl &= ~CTRL_RUNLATCH; 1617 mtspr(SPRN_CTRLT, ctrl); 1618 } 1619 #endif /* CONFIG_PPC64 */ 1620 1621 unsigned long arch_align_stack(unsigned long sp) 1622 { 1623 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1624 sp -= get_random_int() & ~PAGE_MASK; 1625 return sp & ~0xf; 1626 } 1627 1628 static inline unsigned long brk_rnd(void) 1629 { 1630 unsigned long rnd = 0; 1631 1632 /* 8MB for 32bit, 1GB for 64bit */ 1633 if (is_32bit_task()) 1634 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); 1635 else 1636 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); 1637 1638 return rnd << PAGE_SHIFT; 1639 } 1640 1641 unsigned long arch_randomize_brk(struct mm_struct *mm) 1642 { 1643 unsigned long base = mm->brk; 1644 unsigned long ret; 1645 1646 #ifdef CONFIG_PPC_STD_MMU_64 1647 /* 1648 * If we are using 1TB segments and we are allowed to randomise 1649 * the heap, we can put it above 1TB so it is backed by a 1TB 1650 * segment. Otherwise the heap will be in the bottom 1TB 1651 * which always uses 256MB segments and this may result in a 1652 * performance penalty. 1653 */ 1654 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1655 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1656 #endif 1657 1658 ret = PAGE_ALIGN(base + brk_rnd()); 1659 1660 if (ret < mm->brk) 1661 return mm->brk; 1662 1663 return ret; 1664 } 1665 1666 unsigned long randomize_et_dyn(unsigned long base) 1667 { 1668 unsigned long ret = PAGE_ALIGN(base + brk_rnd()); 1669 1670 if (ret < base) 1671 return base; 1672 1673 return ret; 1674 } 1675