xref: /openbmc/linux/arch/powerpc/kernel/process.c (revision 1b39eacd)
1 /*
2  *  Derived from "arch/i386/kernel/process.c"
3  *    Copyright (C) 1995  Linus Torvalds
4  *
5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6  *  Paul Mackerras (paulus@cs.anu.edu.au)
7  *
8  *  PowerPC version
9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10  *
11  *  This program is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU General Public License
13  *  as published by the Free Software Foundation; either version
14  *  2 of the License, or (at your option) any later version.
15  */
16 
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
23 #include <linux/mm.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
45 
46 #include <asm/pgtable.h>
47 #include <asm/io.h>
48 #include <asm/processor.h>
49 #include <asm/mmu.h>
50 #include <asm/prom.h>
51 #include <asm/machdep.h>
52 #include <asm/time.h>
53 #include <asm/runlatch.h>
54 #include <asm/syscalls.h>
55 #include <asm/switch_to.h>
56 #include <asm/tm.h>
57 #include <asm/debug.h>
58 #ifdef CONFIG_PPC64
59 #include <asm/firmware.h>
60 #endif
61 #include <asm/code-patching.h>
62 #include <asm/exec.h>
63 #include <asm/livepatch.h>
64 #include <asm/cpu_has_feature.h>
65 #include <asm/asm-prototypes.h>
66 
67 #include <linux/kprobes.h>
68 #include <linux/kdebug.h>
69 
70 /* Transactional Memory debug */
71 #ifdef TM_DEBUG_SW
72 #define TM_DEBUG(x...) printk(KERN_INFO x)
73 #else
74 #define TM_DEBUG(x...) do { } while(0)
75 #endif
76 
77 extern unsigned long _get_SP(void);
78 
79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
80 /*
81  * Are we running in "Suspend disabled" mode? If so we have to block any
82  * sigreturn that would get us into suspended state, and we also warn in some
83  * other paths that we should never reach with suspend disabled.
84  */
85 bool tm_suspend_disabled __ro_after_init = false;
86 
87 static void check_if_tm_restore_required(struct task_struct *tsk)
88 {
89 	/*
90 	 * If we are saving the current thread's registers, and the
91 	 * thread is in a transactional state, set the TIF_RESTORE_TM
92 	 * bit so that we know to restore the registers before
93 	 * returning to userspace.
94 	 */
95 	if (tsk == current && tsk->thread.regs &&
96 	    MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
97 	    !test_thread_flag(TIF_RESTORE_TM)) {
98 		tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
99 		set_thread_flag(TIF_RESTORE_TM);
100 	}
101 }
102 
103 static inline bool msr_tm_active(unsigned long msr)
104 {
105 	return MSR_TM_ACTIVE(msr);
106 }
107 
108 static bool tm_active_with_fp(struct task_struct *tsk)
109 {
110 	return msr_tm_active(tsk->thread.regs->msr) &&
111 		(tsk->thread.ckpt_regs.msr & MSR_FP);
112 }
113 
114 static bool tm_active_with_altivec(struct task_struct *tsk)
115 {
116 	return msr_tm_active(tsk->thread.regs->msr) &&
117 		(tsk->thread.ckpt_regs.msr & MSR_VEC);
118 }
119 #else
120 static inline bool msr_tm_active(unsigned long msr) { return false; }
121 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
122 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
123 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
124 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
125 
126 bool strict_msr_control;
127 EXPORT_SYMBOL(strict_msr_control);
128 
129 static int __init enable_strict_msr_control(char *str)
130 {
131 	strict_msr_control = true;
132 	pr_info("Enabling strict facility control\n");
133 
134 	return 0;
135 }
136 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
137 
138 unsigned long msr_check_and_set(unsigned long bits)
139 {
140 	unsigned long oldmsr = mfmsr();
141 	unsigned long newmsr;
142 
143 	newmsr = oldmsr | bits;
144 
145 #ifdef CONFIG_VSX
146 	if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
147 		newmsr |= MSR_VSX;
148 #endif
149 
150 	if (oldmsr != newmsr)
151 		mtmsr_isync(newmsr);
152 
153 	return newmsr;
154 }
155 
156 void __msr_check_and_clear(unsigned long bits)
157 {
158 	unsigned long oldmsr = mfmsr();
159 	unsigned long newmsr;
160 
161 	newmsr = oldmsr & ~bits;
162 
163 #ifdef CONFIG_VSX
164 	if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
165 		newmsr &= ~MSR_VSX;
166 #endif
167 
168 	if (oldmsr != newmsr)
169 		mtmsr_isync(newmsr);
170 }
171 EXPORT_SYMBOL(__msr_check_and_clear);
172 
173 #ifdef CONFIG_PPC_FPU
174 void __giveup_fpu(struct task_struct *tsk)
175 {
176 	unsigned long msr;
177 
178 	save_fpu(tsk);
179 	msr = tsk->thread.regs->msr;
180 	msr &= ~MSR_FP;
181 #ifdef CONFIG_VSX
182 	if (cpu_has_feature(CPU_FTR_VSX))
183 		msr &= ~MSR_VSX;
184 #endif
185 	tsk->thread.regs->msr = msr;
186 }
187 
188 void giveup_fpu(struct task_struct *tsk)
189 {
190 	check_if_tm_restore_required(tsk);
191 
192 	msr_check_and_set(MSR_FP);
193 	__giveup_fpu(tsk);
194 	msr_check_and_clear(MSR_FP);
195 }
196 EXPORT_SYMBOL(giveup_fpu);
197 
198 /*
199  * Make sure the floating-point register state in the
200  * the thread_struct is up to date for task tsk.
201  */
202 void flush_fp_to_thread(struct task_struct *tsk)
203 {
204 	if (tsk->thread.regs) {
205 		/*
206 		 * We need to disable preemption here because if we didn't,
207 		 * another process could get scheduled after the regs->msr
208 		 * test but before we have finished saving the FP registers
209 		 * to the thread_struct.  That process could take over the
210 		 * FPU, and then when we get scheduled again we would store
211 		 * bogus values for the remaining FP registers.
212 		 */
213 		preempt_disable();
214 		if (tsk->thread.regs->msr & MSR_FP) {
215 			/*
216 			 * This should only ever be called for current or
217 			 * for a stopped child process.  Since we save away
218 			 * the FP register state on context switch,
219 			 * there is something wrong if a stopped child appears
220 			 * to still have its FP state in the CPU registers.
221 			 */
222 			BUG_ON(tsk != current);
223 			giveup_fpu(tsk);
224 		}
225 		preempt_enable();
226 	}
227 }
228 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
229 
230 void enable_kernel_fp(void)
231 {
232 	unsigned long cpumsr;
233 
234 	WARN_ON(preemptible());
235 
236 	cpumsr = msr_check_and_set(MSR_FP);
237 
238 	if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
239 		check_if_tm_restore_required(current);
240 		/*
241 		 * If a thread has already been reclaimed then the
242 		 * checkpointed registers are on the CPU but have definitely
243 		 * been saved by the reclaim code. Don't need to and *cannot*
244 		 * giveup as this would save  to the 'live' structure not the
245 		 * checkpointed structure.
246 		 */
247 		if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
248 			return;
249 		__giveup_fpu(current);
250 	}
251 }
252 EXPORT_SYMBOL(enable_kernel_fp);
253 
254 static int restore_fp(struct task_struct *tsk)
255 {
256 	if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
257 		load_fp_state(&current->thread.fp_state);
258 		current->thread.load_fp++;
259 		return 1;
260 	}
261 	return 0;
262 }
263 #else
264 static int restore_fp(struct task_struct *tsk) { return 0; }
265 #endif /* CONFIG_PPC_FPU */
266 
267 #ifdef CONFIG_ALTIVEC
268 #define loadvec(thr) ((thr).load_vec)
269 
270 static void __giveup_altivec(struct task_struct *tsk)
271 {
272 	unsigned long msr;
273 
274 	save_altivec(tsk);
275 	msr = tsk->thread.regs->msr;
276 	msr &= ~MSR_VEC;
277 #ifdef CONFIG_VSX
278 	if (cpu_has_feature(CPU_FTR_VSX))
279 		msr &= ~MSR_VSX;
280 #endif
281 	tsk->thread.regs->msr = msr;
282 }
283 
284 void giveup_altivec(struct task_struct *tsk)
285 {
286 	check_if_tm_restore_required(tsk);
287 
288 	msr_check_and_set(MSR_VEC);
289 	__giveup_altivec(tsk);
290 	msr_check_and_clear(MSR_VEC);
291 }
292 EXPORT_SYMBOL(giveup_altivec);
293 
294 void enable_kernel_altivec(void)
295 {
296 	unsigned long cpumsr;
297 
298 	WARN_ON(preemptible());
299 
300 	cpumsr = msr_check_and_set(MSR_VEC);
301 
302 	if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
303 		check_if_tm_restore_required(current);
304 		/*
305 		 * If a thread has already been reclaimed then the
306 		 * checkpointed registers are on the CPU but have definitely
307 		 * been saved by the reclaim code. Don't need to and *cannot*
308 		 * giveup as this would save  to the 'live' structure not the
309 		 * checkpointed structure.
310 		 */
311 		if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
312 			return;
313 		__giveup_altivec(current);
314 	}
315 }
316 EXPORT_SYMBOL(enable_kernel_altivec);
317 
318 /*
319  * Make sure the VMX/Altivec register state in the
320  * the thread_struct is up to date for task tsk.
321  */
322 void flush_altivec_to_thread(struct task_struct *tsk)
323 {
324 	if (tsk->thread.regs) {
325 		preempt_disable();
326 		if (tsk->thread.regs->msr & MSR_VEC) {
327 			BUG_ON(tsk != current);
328 			giveup_altivec(tsk);
329 		}
330 		preempt_enable();
331 	}
332 }
333 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
334 
335 static int restore_altivec(struct task_struct *tsk)
336 {
337 	if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
338 		(tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
339 		load_vr_state(&tsk->thread.vr_state);
340 		tsk->thread.used_vr = 1;
341 		tsk->thread.load_vec++;
342 
343 		return 1;
344 	}
345 	return 0;
346 }
347 #else
348 #define loadvec(thr) 0
349 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
350 #endif /* CONFIG_ALTIVEC */
351 
352 #ifdef CONFIG_VSX
353 static void __giveup_vsx(struct task_struct *tsk)
354 {
355 	unsigned long msr = tsk->thread.regs->msr;
356 
357 	/*
358 	 * We should never be ssetting MSR_VSX without also setting
359 	 * MSR_FP and MSR_VEC
360 	 */
361 	WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
362 
363 	/* __giveup_fpu will clear MSR_VSX */
364 	if (msr & MSR_FP)
365 		__giveup_fpu(tsk);
366 	if (msr & MSR_VEC)
367 		__giveup_altivec(tsk);
368 }
369 
370 static void giveup_vsx(struct task_struct *tsk)
371 {
372 	check_if_tm_restore_required(tsk);
373 
374 	msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
375 	__giveup_vsx(tsk);
376 	msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
377 }
378 
379 void enable_kernel_vsx(void)
380 {
381 	unsigned long cpumsr;
382 
383 	WARN_ON(preemptible());
384 
385 	cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
386 
387 	if (current->thread.regs &&
388 	    (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
389 		check_if_tm_restore_required(current);
390 		/*
391 		 * If a thread has already been reclaimed then the
392 		 * checkpointed registers are on the CPU but have definitely
393 		 * been saved by the reclaim code. Don't need to and *cannot*
394 		 * giveup as this would save  to the 'live' structure not the
395 		 * checkpointed structure.
396 		 */
397 		if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
398 			return;
399 		__giveup_vsx(current);
400 	}
401 }
402 EXPORT_SYMBOL(enable_kernel_vsx);
403 
404 void flush_vsx_to_thread(struct task_struct *tsk)
405 {
406 	if (tsk->thread.regs) {
407 		preempt_disable();
408 		if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
409 			BUG_ON(tsk != current);
410 			giveup_vsx(tsk);
411 		}
412 		preempt_enable();
413 	}
414 }
415 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
416 
417 static int restore_vsx(struct task_struct *tsk)
418 {
419 	if (cpu_has_feature(CPU_FTR_VSX)) {
420 		tsk->thread.used_vsr = 1;
421 		return 1;
422 	}
423 
424 	return 0;
425 }
426 #else
427 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
428 #endif /* CONFIG_VSX */
429 
430 #ifdef CONFIG_SPE
431 void giveup_spe(struct task_struct *tsk)
432 {
433 	check_if_tm_restore_required(tsk);
434 
435 	msr_check_and_set(MSR_SPE);
436 	__giveup_spe(tsk);
437 	msr_check_and_clear(MSR_SPE);
438 }
439 EXPORT_SYMBOL(giveup_spe);
440 
441 void enable_kernel_spe(void)
442 {
443 	WARN_ON(preemptible());
444 
445 	msr_check_and_set(MSR_SPE);
446 
447 	if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
448 		check_if_tm_restore_required(current);
449 		__giveup_spe(current);
450 	}
451 }
452 EXPORT_SYMBOL(enable_kernel_spe);
453 
454 void flush_spe_to_thread(struct task_struct *tsk)
455 {
456 	if (tsk->thread.regs) {
457 		preempt_disable();
458 		if (tsk->thread.regs->msr & MSR_SPE) {
459 			BUG_ON(tsk != current);
460 			tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
461 			giveup_spe(tsk);
462 		}
463 		preempt_enable();
464 	}
465 }
466 #endif /* CONFIG_SPE */
467 
468 static unsigned long msr_all_available;
469 
470 static int __init init_msr_all_available(void)
471 {
472 #ifdef CONFIG_PPC_FPU
473 	msr_all_available |= MSR_FP;
474 #endif
475 #ifdef CONFIG_ALTIVEC
476 	if (cpu_has_feature(CPU_FTR_ALTIVEC))
477 		msr_all_available |= MSR_VEC;
478 #endif
479 #ifdef CONFIG_VSX
480 	if (cpu_has_feature(CPU_FTR_VSX))
481 		msr_all_available |= MSR_VSX;
482 #endif
483 #ifdef CONFIG_SPE
484 	if (cpu_has_feature(CPU_FTR_SPE))
485 		msr_all_available |= MSR_SPE;
486 #endif
487 
488 	return 0;
489 }
490 early_initcall(init_msr_all_available);
491 
492 void giveup_all(struct task_struct *tsk)
493 {
494 	unsigned long usermsr;
495 
496 	if (!tsk->thread.regs)
497 		return;
498 
499 	usermsr = tsk->thread.regs->msr;
500 
501 	if ((usermsr & msr_all_available) == 0)
502 		return;
503 
504 	msr_check_and_set(msr_all_available);
505 	check_if_tm_restore_required(tsk);
506 
507 	WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
508 
509 #ifdef CONFIG_PPC_FPU
510 	if (usermsr & MSR_FP)
511 		__giveup_fpu(tsk);
512 #endif
513 #ifdef CONFIG_ALTIVEC
514 	if (usermsr & MSR_VEC)
515 		__giveup_altivec(tsk);
516 #endif
517 #ifdef CONFIG_SPE
518 	if (usermsr & MSR_SPE)
519 		__giveup_spe(tsk);
520 #endif
521 
522 	msr_check_and_clear(msr_all_available);
523 }
524 EXPORT_SYMBOL(giveup_all);
525 
526 void restore_math(struct pt_regs *regs)
527 {
528 	unsigned long msr;
529 
530 	if (!msr_tm_active(regs->msr) &&
531 		!current->thread.load_fp && !loadvec(current->thread))
532 		return;
533 
534 	msr = regs->msr;
535 	msr_check_and_set(msr_all_available);
536 
537 	/*
538 	 * Only reload if the bit is not set in the user MSR, the bit BEING set
539 	 * indicates that the registers are hot
540 	 */
541 	if ((!(msr & MSR_FP)) && restore_fp(current))
542 		msr |= MSR_FP | current->thread.fpexc_mode;
543 
544 	if ((!(msr & MSR_VEC)) && restore_altivec(current))
545 		msr |= MSR_VEC;
546 
547 	if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
548 			restore_vsx(current)) {
549 		msr |= MSR_VSX;
550 	}
551 
552 	msr_check_and_clear(msr_all_available);
553 
554 	regs->msr = msr;
555 }
556 
557 void save_all(struct task_struct *tsk)
558 {
559 	unsigned long usermsr;
560 
561 	if (!tsk->thread.regs)
562 		return;
563 
564 	usermsr = tsk->thread.regs->msr;
565 
566 	if ((usermsr & msr_all_available) == 0)
567 		return;
568 
569 	msr_check_and_set(msr_all_available);
570 
571 	WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
572 
573 	if (usermsr & MSR_FP)
574 		save_fpu(tsk);
575 
576 	if (usermsr & MSR_VEC)
577 		save_altivec(tsk);
578 
579 	if (usermsr & MSR_SPE)
580 		__giveup_spe(tsk);
581 
582 	msr_check_and_clear(msr_all_available);
583 }
584 
585 void flush_all_to_thread(struct task_struct *tsk)
586 {
587 	if (tsk->thread.regs) {
588 		preempt_disable();
589 		BUG_ON(tsk != current);
590 		save_all(tsk);
591 
592 #ifdef CONFIG_SPE
593 		if (tsk->thread.regs->msr & MSR_SPE)
594 			tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
595 #endif
596 
597 		preempt_enable();
598 	}
599 }
600 EXPORT_SYMBOL(flush_all_to_thread);
601 
602 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
603 void do_send_trap(struct pt_regs *regs, unsigned long address,
604 		  unsigned long error_code, int signal_code, int breakpt)
605 {
606 	siginfo_t info;
607 
608 	current->thread.trap_nr = signal_code;
609 	if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
610 			11, SIGSEGV) == NOTIFY_STOP)
611 		return;
612 
613 	/* Deliver the signal to userspace */
614 	info.si_signo = SIGTRAP;
615 	info.si_errno = breakpt;	/* breakpoint or watchpoint id */
616 	info.si_code = signal_code;
617 	info.si_addr = (void __user *)address;
618 	force_sig_info(SIGTRAP, &info, current);
619 }
620 #else	/* !CONFIG_PPC_ADV_DEBUG_REGS */
621 void do_break (struct pt_regs *regs, unsigned long address,
622 		    unsigned long error_code)
623 {
624 	siginfo_t info;
625 
626 	current->thread.trap_nr = TRAP_HWBKPT;
627 	if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
628 			11, SIGSEGV) == NOTIFY_STOP)
629 		return;
630 
631 	if (debugger_break_match(regs))
632 		return;
633 
634 	/* Clear the breakpoint */
635 	hw_breakpoint_disable();
636 
637 	/* Deliver the signal to userspace */
638 	info.si_signo = SIGTRAP;
639 	info.si_errno = 0;
640 	info.si_code = TRAP_HWBKPT;
641 	info.si_addr = (void __user *)address;
642 	force_sig_info(SIGTRAP, &info, current);
643 }
644 #endif	/* CONFIG_PPC_ADV_DEBUG_REGS */
645 
646 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
647 
648 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
649 /*
650  * Set the debug registers back to their default "safe" values.
651  */
652 static void set_debug_reg_defaults(struct thread_struct *thread)
653 {
654 	thread->debug.iac1 = thread->debug.iac2 = 0;
655 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
656 	thread->debug.iac3 = thread->debug.iac4 = 0;
657 #endif
658 	thread->debug.dac1 = thread->debug.dac2 = 0;
659 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
660 	thread->debug.dvc1 = thread->debug.dvc2 = 0;
661 #endif
662 	thread->debug.dbcr0 = 0;
663 #ifdef CONFIG_BOOKE
664 	/*
665 	 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
666 	 */
667 	thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
668 			DBCR1_IAC3US | DBCR1_IAC4US;
669 	/*
670 	 * Force Data Address Compare User/Supervisor bits to be User-only
671 	 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
672 	 */
673 	thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
674 #else
675 	thread->debug.dbcr1 = 0;
676 #endif
677 }
678 
679 static void prime_debug_regs(struct debug_reg *debug)
680 {
681 	/*
682 	 * We could have inherited MSR_DE from userspace, since
683 	 * it doesn't get cleared on exception entry.  Make sure
684 	 * MSR_DE is clear before we enable any debug events.
685 	 */
686 	mtmsr(mfmsr() & ~MSR_DE);
687 
688 	mtspr(SPRN_IAC1, debug->iac1);
689 	mtspr(SPRN_IAC2, debug->iac2);
690 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
691 	mtspr(SPRN_IAC3, debug->iac3);
692 	mtspr(SPRN_IAC4, debug->iac4);
693 #endif
694 	mtspr(SPRN_DAC1, debug->dac1);
695 	mtspr(SPRN_DAC2, debug->dac2);
696 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
697 	mtspr(SPRN_DVC1, debug->dvc1);
698 	mtspr(SPRN_DVC2, debug->dvc2);
699 #endif
700 	mtspr(SPRN_DBCR0, debug->dbcr0);
701 	mtspr(SPRN_DBCR1, debug->dbcr1);
702 #ifdef CONFIG_BOOKE
703 	mtspr(SPRN_DBCR2, debug->dbcr2);
704 #endif
705 }
706 /*
707  * Unless neither the old or new thread are making use of the
708  * debug registers, set the debug registers from the values
709  * stored in the new thread.
710  */
711 void switch_booke_debug_regs(struct debug_reg *new_debug)
712 {
713 	if ((current->thread.debug.dbcr0 & DBCR0_IDM)
714 		|| (new_debug->dbcr0 & DBCR0_IDM))
715 			prime_debug_regs(new_debug);
716 }
717 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
718 #else	/* !CONFIG_PPC_ADV_DEBUG_REGS */
719 #ifndef CONFIG_HAVE_HW_BREAKPOINT
720 static void set_debug_reg_defaults(struct thread_struct *thread)
721 {
722 	thread->hw_brk.address = 0;
723 	thread->hw_brk.type = 0;
724 	set_breakpoint(&thread->hw_brk);
725 }
726 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
727 #endif	/* CONFIG_PPC_ADV_DEBUG_REGS */
728 
729 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
730 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
731 {
732 	mtspr(SPRN_DAC1, dabr);
733 #ifdef CONFIG_PPC_47x
734 	isync();
735 #endif
736 	return 0;
737 }
738 #elif defined(CONFIG_PPC_BOOK3S)
739 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
740 {
741 	mtspr(SPRN_DABR, dabr);
742 	if (cpu_has_feature(CPU_FTR_DABRX))
743 		mtspr(SPRN_DABRX, dabrx);
744 	return 0;
745 }
746 #elif defined(CONFIG_PPC_8xx)
747 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
748 {
749 	unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
750 	unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
751 	unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
752 
753 	if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
754 		lctrl1 |= 0xa0000;
755 	else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
756 		lctrl1 |= 0xf0000;
757 	else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
758 		lctrl2 = 0;
759 
760 	mtspr(SPRN_LCTRL2, 0);
761 	mtspr(SPRN_CMPE, addr);
762 	mtspr(SPRN_CMPF, addr + 4);
763 	mtspr(SPRN_LCTRL1, lctrl1);
764 	mtspr(SPRN_LCTRL2, lctrl2);
765 
766 	return 0;
767 }
768 #else
769 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
770 {
771 	return -EINVAL;
772 }
773 #endif
774 
775 static inline int set_dabr(struct arch_hw_breakpoint *brk)
776 {
777 	unsigned long dabr, dabrx;
778 
779 	dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
780 	dabrx = ((brk->type >> 3) & 0x7);
781 
782 	if (ppc_md.set_dabr)
783 		return ppc_md.set_dabr(dabr, dabrx);
784 
785 	return __set_dabr(dabr, dabrx);
786 }
787 
788 static inline int set_dawr(struct arch_hw_breakpoint *brk)
789 {
790 	unsigned long dawr, dawrx, mrd;
791 
792 	dawr = brk->address;
793 
794 	dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
795 		                   << (63 - 58); //* read/write bits */
796 	dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
797 		                   << (63 - 59); //* translate */
798 	dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
799 		                   >> 3; //* PRIM bits */
800 	/* dawr length is stored in field MDR bits 48:53.  Matches range in
801 	   doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
802 	   0b111111=64DW.
803 	   brk->len is in bytes.
804 	   This aligns up to double word size, shifts and does the bias.
805 	*/
806 	mrd = ((brk->len + 7) >> 3) - 1;
807 	dawrx |= (mrd & 0x3f) << (63 - 53);
808 
809 	if (ppc_md.set_dawr)
810 		return ppc_md.set_dawr(dawr, dawrx);
811 	mtspr(SPRN_DAWR, dawr);
812 	mtspr(SPRN_DAWRX, dawrx);
813 	return 0;
814 }
815 
816 void __set_breakpoint(struct arch_hw_breakpoint *brk)
817 {
818 	memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
819 
820 	if (cpu_has_feature(CPU_FTR_DAWR))
821 		set_dawr(brk);
822 	else
823 		set_dabr(brk);
824 }
825 
826 void set_breakpoint(struct arch_hw_breakpoint *brk)
827 {
828 	preempt_disable();
829 	__set_breakpoint(brk);
830 	preempt_enable();
831 }
832 
833 #ifdef CONFIG_PPC64
834 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
835 #endif
836 
837 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
838 			      struct arch_hw_breakpoint *b)
839 {
840 	if (a->address != b->address)
841 		return false;
842 	if (a->type != b->type)
843 		return false;
844 	if (a->len != b->len)
845 		return false;
846 	return true;
847 }
848 
849 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
850 
851 static inline bool tm_enabled(struct task_struct *tsk)
852 {
853 	return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
854 }
855 
856 static void tm_reclaim_thread(struct thread_struct *thr,
857 			      struct thread_info *ti, uint8_t cause)
858 {
859 	/*
860 	 * Use the current MSR TM suspended bit to track if we have
861 	 * checkpointed state outstanding.
862 	 * On signal delivery, we'd normally reclaim the checkpointed
863 	 * state to obtain stack pointer (see:get_tm_stackpointer()).
864 	 * This will then directly return to userspace without going
865 	 * through __switch_to(). However, if the stack frame is bad,
866 	 * we need to exit this thread which calls __switch_to() which
867 	 * will again attempt to reclaim the already saved tm state.
868 	 * Hence we need to check that we've not already reclaimed
869 	 * this state.
870 	 * We do this using the current MSR, rather tracking it in
871 	 * some specific thread_struct bit, as it has the additional
872 	 * benefit of checking for a potential TM bad thing exception.
873 	 */
874 	if (!MSR_TM_SUSPENDED(mfmsr()))
875 		return;
876 
877 	giveup_all(container_of(thr, struct task_struct, thread));
878 
879 	tm_reclaim(thr, cause);
880 
881 	/*
882 	 * If we are in a transaction and FP is off then we can't have
883 	 * used FP inside that transaction. Hence the checkpointed
884 	 * state is the same as the live state. We need to copy the
885 	 * live state to the checkpointed state so that when the
886 	 * transaction is restored, the checkpointed state is correct
887 	 * and the aborted transaction sees the correct state. We use
888 	 * ckpt_regs.msr here as that's what tm_reclaim will use to
889 	 * determine if it's going to write the checkpointed state or
890 	 * not. So either this will write the checkpointed registers,
891 	 * or reclaim will. Similarly for VMX.
892 	 */
893 	if ((thr->ckpt_regs.msr & MSR_FP) == 0)
894 		memcpy(&thr->ckfp_state, &thr->fp_state,
895 		       sizeof(struct thread_fp_state));
896 	if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
897 		memcpy(&thr->ckvr_state, &thr->vr_state,
898 		       sizeof(struct thread_vr_state));
899 }
900 
901 void tm_reclaim_current(uint8_t cause)
902 {
903 	tm_enable();
904 	tm_reclaim_thread(&current->thread, current_thread_info(), cause);
905 }
906 
907 static inline void tm_reclaim_task(struct task_struct *tsk)
908 {
909 	/* We have to work out if we're switching from/to a task that's in the
910 	 * middle of a transaction.
911 	 *
912 	 * In switching we need to maintain a 2nd register state as
913 	 * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
914 	 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
915 	 * ckvr_state
916 	 *
917 	 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
918 	 */
919 	struct thread_struct *thr = &tsk->thread;
920 
921 	if (!thr->regs)
922 		return;
923 
924 	if (!MSR_TM_ACTIVE(thr->regs->msr))
925 		goto out_and_saveregs;
926 
927 	WARN_ON(tm_suspend_disabled);
928 
929 	TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
930 		 "ccr=%lx, msr=%lx, trap=%lx)\n",
931 		 tsk->pid, thr->regs->nip,
932 		 thr->regs->ccr, thr->regs->msr,
933 		 thr->regs->trap);
934 
935 	tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
936 
937 	TM_DEBUG("--- tm_reclaim on pid %d complete\n",
938 		 tsk->pid);
939 
940 out_and_saveregs:
941 	/* Always save the regs here, even if a transaction's not active.
942 	 * This context-switches a thread's TM info SPRs.  We do it here to
943 	 * be consistent with the restore path (in recheckpoint) which
944 	 * cannot happen later in _switch().
945 	 */
946 	tm_save_sprs(thr);
947 }
948 
949 extern void __tm_recheckpoint(struct thread_struct *thread);
950 
951 void tm_recheckpoint(struct thread_struct *thread)
952 {
953 	unsigned long flags;
954 
955 	if (!(thread->regs->msr & MSR_TM))
956 		return;
957 
958 	/* We really can't be interrupted here as the TEXASR registers can't
959 	 * change and later in the trecheckpoint code, we have a userspace R1.
960 	 * So let's hard disable over this region.
961 	 */
962 	local_irq_save(flags);
963 	hard_irq_disable();
964 
965 	/* The TM SPRs are restored here, so that TEXASR.FS can be set
966 	 * before the trecheckpoint and no explosion occurs.
967 	 */
968 	tm_restore_sprs(thread);
969 
970 	__tm_recheckpoint(thread);
971 
972 	local_irq_restore(flags);
973 }
974 
975 static inline void tm_recheckpoint_new_task(struct task_struct *new)
976 {
977 	if (!cpu_has_feature(CPU_FTR_TM))
978 		return;
979 
980 	/* Recheckpoint the registers of the thread we're about to switch to.
981 	 *
982 	 * If the task was using FP, we non-lazily reload both the original and
983 	 * the speculative FP register states.  This is because the kernel
984 	 * doesn't see if/when a TM rollback occurs, so if we take an FP
985 	 * unavailable later, we are unable to determine which set of FP regs
986 	 * need to be restored.
987 	 */
988 	if (!tm_enabled(new))
989 		return;
990 
991 	if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
992 		tm_restore_sprs(&new->thread);
993 		return;
994 	}
995 	/* Recheckpoint to restore original checkpointed register state. */
996 	TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
997 		 new->pid, new->thread.regs->msr);
998 
999 	tm_recheckpoint(&new->thread);
1000 
1001 	/*
1002 	 * The checkpointed state has been restored but the live state has
1003 	 * not, ensure all the math functionality is turned off to trigger
1004 	 * restore_math() to reload.
1005 	 */
1006 	new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1007 
1008 	TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1009 		 "(kernel msr 0x%lx)\n",
1010 		 new->pid, mfmsr());
1011 }
1012 
1013 static inline void __switch_to_tm(struct task_struct *prev,
1014 		struct task_struct *new)
1015 {
1016 	if (cpu_has_feature(CPU_FTR_TM)) {
1017 		if (tm_enabled(prev) || tm_enabled(new))
1018 			tm_enable();
1019 
1020 		if (tm_enabled(prev)) {
1021 			prev->thread.load_tm++;
1022 			tm_reclaim_task(prev);
1023 			if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1024 				prev->thread.regs->msr &= ~MSR_TM;
1025 		}
1026 
1027 		tm_recheckpoint_new_task(new);
1028 	}
1029 }
1030 
1031 /*
1032  * This is called if we are on the way out to userspace and the
1033  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1034  * FP and/or vector state and does so if necessary.
1035  * If userspace is inside a transaction (whether active or
1036  * suspended) and FP/VMX/VSX instructions have ever been enabled
1037  * inside that transaction, then we have to keep them enabled
1038  * and keep the FP/VMX/VSX state loaded while ever the transaction
1039  * continues.  The reason is that if we didn't, and subsequently
1040  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1041  * we don't know whether it's the same transaction, and thus we
1042  * don't know which of the checkpointed state and the transactional
1043  * state to use.
1044  */
1045 void restore_tm_state(struct pt_regs *regs)
1046 {
1047 	unsigned long msr_diff;
1048 
1049 	/*
1050 	 * This is the only moment we should clear TIF_RESTORE_TM as
1051 	 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1052 	 * again, anything else could lead to an incorrect ckpt_msr being
1053 	 * saved and therefore incorrect signal contexts.
1054 	 */
1055 	clear_thread_flag(TIF_RESTORE_TM);
1056 	if (!MSR_TM_ACTIVE(regs->msr))
1057 		return;
1058 
1059 	msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1060 	msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1061 
1062 	/* Ensure that restore_math() will restore */
1063 	if (msr_diff & MSR_FP)
1064 		current->thread.load_fp = 1;
1065 #ifdef CONFIG_ALTIVEC
1066 	if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1067 		current->thread.load_vec = 1;
1068 #endif
1069 	restore_math(regs);
1070 
1071 	regs->msr |= msr_diff;
1072 }
1073 
1074 #else
1075 #define tm_recheckpoint_new_task(new)
1076 #define __switch_to_tm(prev, new)
1077 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1078 
1079 static inline void save_sprs(struct thread_struct *t)
1080 {
1081 #ifdef CONFIG_ALTIVEC
1082 	if (cpu_has_feature(CPU_FTR_ALTIVEC))
1083 		t->vrsave = mfspr(SPRN_VRSAVE);
1084 #endif
1085 #ifdef CONFIG_PPC_BOOK3S_64
1086 	if (cpu_has_feature(CPU_FTR_DSCR))
1087 		t->dscr = mfspr(SPRN_DSCR);
1088 
1089 	if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1090 		t->bescr = mfspr(SPRN_BESCR);
1091 		t->ebbhr = mfspr(SPRN_EBBHR);
1092 		t->ebbrr = mfspr(SPRN_EBBRR);
1093 
1094 		t->fscr = mfspr(SPRN_FSCR);
1095 
1096 		/*
1097 		 * Note that the TAR is not available for use in the kernel.
1098 		 * (To provide this, the TAR should be backed up/restored on
1099 		 * exception entry/exit instead, and be in pt_regs.  FIXME,
1100 		 * this should be in pt_regs anyway (for debug).)
1101 		 */
1102 		t->tar = mfspr(SPRN_TAR);
1103 	}
1104 #endif
1105 }
1106 
1107 static inline void restore_sprs(struct thread_struct *old_thread,
1108 				struct thread_struct *new_thread)
1109 {
1110 #ifdef CONFIG_ALTIVEC
1111 	if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1112 	    old_thread->vrsave != new_thread->vrsave)
1113 		mtspr(SPRN_VRSAVE, new_thread->vrsave);
1114 #endif
1115 #ifdef CONFIG_PPC_BOOK3S_64
1116 	if (cpu_has_feature(CPU_FTR_DSCR)) {
1117 		u64 dscr = get_paca()->dscr_default;
1118 		if (new_thread->dscr_inherit)
1119 			dscr = new_thread->dscr;
1120 
1121 		if (old_thread->dscr != dscr)
1122 			mtspr(SPRN_DSCR, dscr);
1123 	}
1124 
1125 	if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1126 		if (old_thread->bescr != new_thread->bescr)
1127 			mtspr(SPRN_BESCR, new_thread->bescr);
1128 		if (old_thread->ebbhr != new_thread->ebbhr)
1129 			mtspr(SPRN_EBBHR, new_thread->ebbhr);
1130 		if (old_thread->ebbrr != new_thread->ebbrr)
1131 			mtspr(SPRN_EBBRR, new_thread->ebbrr);
1132 
1133 		if (old_thread->fscr != new_thread->fscr)
1134 			mtspr(SPRN_FSCR, new_thread->fscr);
1135 
1136 		if (old_thread->tar != new_thread->tar)
1137 			mtspr(SPRN_TAR, new_thread->tar);
1138 	}
1139 
1140 	if (cpu_has_feature(CPU_FTR_ARCH_300) &&
1141 	    old_thread->tidr != new_thread->tidr)
1142 		mtspr(SPRN_TIDR, new_thread->tidr);
1143 #endif
1144 }
1145 
1146 #ifdef CONFIG_PPC_BOOK3S_64
1147 #define CP_SIZE 128
1148 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1149 #endif
1150 
1151 struct task_struct *__switch_to(struct task_struct *prev,
1152 	struct task_struct *new)
1153 {
1154 	struct thread_struct *new_thread, *old_thread;
1155 	struct task_struct *last;
1156 #ifdef CONFIG_PPC_BOOK3S_64
1157 	struct ppc64_tlb_batch *batch;
1158 #endif
1159 
1160 	new_thread = &new->thread;
1161 	old_thread = &current->thread;
1162 
1163 	WARN_ON(!irqs_disabled());
1164 
1165 #ifdef CONFIG_PPC64
1166 	/*
1167 	 * Collect processor utilization data per process
1168 	 */
1169 	if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1170 		struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1171 		long unsigned start_tb, current_tb;
1172 		start_tb = old_thread->start_tb;
1173 		cu->current_tb = current_tb = mfspr(SPRN_PURR);
1174 		old_thread->accum_tb += (current_tb - start_tb);
1175 		new_thread->start_tb = current_tb;
1176 	}
1177 #endif /* CONFIG_PPC64 */
1178 
1179 #ifdef CONFIG_PPC_BOOK3S_64
1180 	batch = this_cpu_ptr(&ppc64_tlb_batch);
1181 	if (batch->active) {
1182 		current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1183 		if (batch->index)
1184 			__flush_tlb_pending(batch);
1185 		batch->active = 0;
1186 	}
1187 #endif /* CONFIG_PPC_BOOK3S_64 */
1188 
1189 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1190 	switch_booke_debug_regs(&new->thread.debug);
1191 #else
1192 /*
1193  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1194  * schedule DABR
1195  */
1196 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1197 	if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1198 		__set_breakpoint(&new->thread.hw_brk);
1199 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1200 #endif
1201 
1202 	/*
1203 	 * We need to save SPRs before treclaim/trecheckpoint as these will
1204 	 * change a number of them.
1205 	 */
1206 	save_sprs(&prev->thread);
1207 
1208 	/* Save FPU, Altivec, VSX and SPE state */
1209 	giveup_all(prev);
1210 
1211 	__switch_to_tm(prev, new);
1212 
1213 	if (!radix_enabled()) {
1214 		/*
1215 		 * We can't take a PMU exception inside _switch() since there
1216 		 * is a window where the kernel stack SLB and the kernel stack
1217 		 * are out of sync. Hard disable here.
1218 		 */
1219 		hard_irq_disable();
1220 	}
1221 
1222 	/*
1223 	 * Call restore_sprs() before calling _switch(). If we move it after
1224 	 * _switch() then we miss out on calling it for new tasks. The reason
1225 	 * for this is we manually create a stack frame for new tasks that
1226 	 * directly returns through ret_from_fork() or
1227 	 * ret_from_kernel_thread(). See copy_thread() for details.
1228 	 */
1229 	restore_sprs(old_thread, new_thread);
1230 
1231 	last = _switch(old_thread, new_thread);
1232 
1233 #ifdef CONFIG_PPC_BOOK3S_64
1234 	if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1235 		current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1236 		batch = this_cpu_ptr(&ppc64_tlb_batch);
1237 		batch->active = 1;
1238 	}
1239 
1240 	if (current_thread_info()->task->thread.regs) {
1241 		restore_math(current_thread_info()->task->thread.regs);
1242 
1243 		/*
1244 		 * The copy-paste buffer can only store into foreign real
1245 		 * addresses, so unprivileged processes can not see the
1246 		 * data or use it in any way unless they have foreign real
1247 		 * mappings. If the new process has the foreign real address
1248 		 * mappings, we must issue a cp_abort to clear any state and
1249 		 * prevent snooping, corruption or a covert channel.
1250 		 *
1251 		 * DD1 allows paste into normal system memory so we do an
1252 		 * unpaired copy, rather than cp_abort, to clear the buffer,
1253 		 * since cp_abort is quite expensive.
1254 		 */
1255 		if (current_thread_info()->task->thread.used_vas) {
1256 			asm volatile(PPC_CP_ABORT);
1257 		} else if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
1258 			asm volatile(PPC_COPY(%0, %1)
1259 					: : "r"(dummy_copy_buffer), "r"(0));
1260 		}
1261 	}
1262 #endif /* CONFIG_PPC_BOOK3S_64 */
1263 
1264 	return last;
1265 }
1266 
1267 static int instructions_to_print = 16;
1268 
1269 static void show_instructions(struct pt_regs *regs)
1270 {
1271 	int i;
1272 	unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1273 			sizeof(int));
1274 
1275 	printk("Instruction dump:");
1276 
1277 	for (i = 0; i < instructions_to_print; i++) {
1278 		int instr;
1279 
1280 		if (!(i % 8))
1281 			pr_cont("\n");
1282 
1283 #if !defined(CONFIG_BOOKE)
1284 		/* If executing with the IMMU off, adjust pc rather
1285 		 * than print XXXXXXXX.
1286 		 */
1287 		if (!(regs->msr & MSR_IR))
1288 			pc = (unsigned long)phys_to_virt(pc);
1289 #endif
1290 
1291 		if (!__kernel_text_address(pc) ||
1292 		     probe_kernel_address((unsigned int __user *)pc, instr)) {
1293 			pr_cont("XXXXXXXX ");
1294 		} else {
1295 			if (regs->nip == pc)
1296 				pr_cont("<%08x> ", instr);
1297 			else
1298 				pr_cont("%08x ", instr);
1299 		}
1300 
1301 		pc += sizeof(int);
1302 	}
1303 
1304 	pr_cont("\n");
1305 }
1306 
1307 struct regbit {
1308 	unsigned long bit;
1309 	const char *name;
1310 };
1311 
1312 static struct regbit msr_bits[] = {
1313 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1314 	{MSR_SF,	"SF"},
1315 	{MSR_HV,	"HV"},
1316 #endif
1317 	{MSR_VEC,	"VEC"},
1318 	{MSR_VSX,	"VSX"},
1319 #ifdef CONFIG_BOOKE
1320 	{MSR_CE,	"CE"},
1321 #endif
1322 	{MSR_EE,	"EE"},
1323 	{MSR_PR,	"PR"},
1324 	{MSR_FP,	"FP"},
1325 	{MSR_ME,	"ME"},
1326 #ifdef CONFIG_BOOKE
1327 	{MSR_DE,	"DE"},
1328 #else
1329 	{MSR_SE,	"SE"},
1330 	{MSR_BE,	"BE"},
1331 #endif
1332 	{MSR_IR,	"IR"},
1333 	{MSR_DR,	"DR"},
1334 	{MSR_PMM,	"PMM"},
1335 #ifndef CONFIG_BOOKE
1336 	{MSR_RI,	"RI"},
1337 	{MSR_LE,	"LE"},
1338 #endif
1339 	{0,		NULL}
1340 };
1341 
1342 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1343 {
1344 	const char *s = "";
1345 
1346 	for (; bits->bit; ++bits)
1347 		if (val & bits->bit) {
1348 			pr_cont("%s%s", s, bits->name);
1349 			s = sep;
1350 		}
1351 }
1352 
1353 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1354 static struct regbit msr_tm_bits[] = {
1355 	{MSR_TS_T,	"T"},
1356 	{MSR_TS_S,	"S"},
1357 	{MSR_TM,	"E"},
1358 	{0,		NULL}
1359 };
1360 
1361 static void print_tm_bits(unsigned long val)
1362 {
1363 /*
1364  * This only prints something if at least one of the TM bit is set.
1365  * Inside the TM[], the output means:
1366  *   E: Enabled		(bit 32)
1367  *   S: Suspended	(bit 33)
1368  *   T: Transactional	(bit 34)
1369  */
1370 	if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1371 		pr_cont(",TM[");
1372 		print_bits(val, msr_tm_bits, "");
1373 		pr_cont("]");
1374 	}
1375 }
1376 #else
1377 static void print_tm_bits(unsigned long val) {}
1378 #endif
1379 
1380 static void print_msr_bits(unsigned long val)
1381 {
1382 	pr_cont("<");
1383 	print_bits(val, msr_bits, ",");
1384 	print_tm_bits(val);
1385 	pr_cont(">");
1386 }
1387 
1388 #ifdef CONFIG_PPC64
1389 #define REG		"%016lx"
1390 #define REGS_PER_LINE	4
1391 #define LAST_VOLATILE	13
1392 #else
1393 #define REG		"%08lx"
1394 #define REGS_PER_LINE	8
1395 #define LAST_VOLATILE	12
1396 #endif
1397 
1398 void show_regs(struct pt_regs * regs)
1399 {
1400 	int i, trap;
1401 
1402 	show_regs_print_info(KERN_DEFAULT);
1403 
1404 	printk("NIP:  "REG" LR: "REG" CTR: "REG"\n",
1405 	       regs->nip, regs->link, regs->ctr);
1406 	printk("REGS: %px TRAP: %04lx   %s  (%s)\n",
1407 	       regs, regs->trap, print_tainted(), init_utsname()->release);
1408 	printk("MSR:  "REG" ", regs->msr);
1409 	print_msr_bits(regs->msr);
1410 	pr_cont("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1411 	trap = TRAP(regs);
1412 	if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1413 		pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1414 	if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1415 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1416 		pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1417 #else
1418 		pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1419 #endif
1420 #ifdef CONFIG_PPC64
1421 	pr_cont("SOFTE: %ld ", regs->softe);
1422 #endif
1423 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1424 	if (MSR_TM_ACTIVE(regs->msr))
1425 		pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1426 #endif
1427 
1428 	for (i = 0;  i < 32;  i++) {
1429 		if ((i % REGS_PER_LINE) == 0)
1430 			pr_cont("\nGPR%02d: ", i);
1431 		pr_cont(REG " ", regs->gpr[i]);
1432 		if (i == LAST_VOLATILE && !FULL_REGS(regs))
1433 			break;
1434 	}
1435 	pr_cont("\n");
1436 #ifdef CONFIG_KALLSYMS
1437 	/*
1438 	 * Lookup NIP late so we have the best change of getting the
1439 	 * above info out without failing
1440 	 */
1441 	printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1442 	printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1443 #endif
1444 	show_stack(current, (unsigned long *) regs->gpr[1]);
1445 	if (!user_mode(regs))
1446 		show_instructions(regs);
1447 }
1448 
1449 void flush_thread(void)
1450 {
1451 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1452 	flush_ptrace_hw_breakpoint(current);
1453 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1454 	set_debug_reg_defaults(&current->thread);
1455 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1456 }
1457 
1458 int set_thread_uses_vas(void)
1459 {
1460 #ifdef CONFIG_PPC_BOOK3S_64
1461 	if (!cpu_has_feature(CPU_FTR_ARCH_300))
1462 		return -EINVAL;
1463 
1464 	current->thread.used_vas = 1;
1465 
1466 	/*
1467 	 * Even a process that has no foreign real address mapping can use
1468 	 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1469 	 * to clear any pending COPY and prevent a covert channel.
1470 	 *
1471 	 * __switch_to() will issue CP_ABORT on future context switches.
1472 	 */
1473 	asm volatile(PPC_CP_ABORT);
1474 
1475 #endif /* CONFIG_PPC_BOOK3S_64 */
1476 	return 0;
1477 }
1478 
1479 #ifdef CONFIG_PPC64
1480 static DEFINE_SPINLOCK(vas_thread_id_lock);
1481 static DEFINE_IDA(vas_thread_ida);
1482 
1483 /*
1484  * We need to assign a unique thread id to each thread in a process.
1485  *
1486  * This thread id, referred to as TIDR, and separate from the Linux's tgid,
1487  * is intended to be used to direct an ASB_Notify from the hardware to the
1488  * thread, when a suitable event occurs in the system.
1489  *
1490  * One such event is a "paste" instruction in the context of Fast Thread
1491  * Wakeup (aka Core-to-core wake up in the Virtual Accelerator Switchboard
1492  * (VAS) in POWER9.
1493  *
1494  * To get a unique TIDR per process we could simply reuse task_pid_nr() but
1495  * the problem is that task_pid_nr() is not yet available copy_thread() is
1496  * called. Fixing that would require changing more intrusive arch-neutral
1497  * code in code path in copy_process()?.
1498  *
1499  * Further, to assign unique TIDRs within each process, we need an atomic
1500  * field (or an IDR) in task_struct, which again intrudes into the arch-
1501  * neutral code. So try to assign globally unique TIDRs for now.
1502  *
1503  * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.
1504  *	 For now, only threads that expect to be notified by the VAS
1505  *	 hardware need a TIDR value and we assign values > 0 for those.
1506  */
1507 #define MAX_THREAD_CONTEXT	((1 << 16) - 1)
1508 static int assign_thread_tidr(void)
1509 {
1510 	int index;
1511 	int err;
1512 
1513 again:
1514 	if (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))
1515 		return -ENOMEM;
1516 
1517 	spin_lock(&vas_thread_id_lock);
1518 	err = ida_get_new_above(&vas_thread_ida, 1, &index);
1519 	spin_unlock(&vas_thread_id_lock);
1520 
1521 	if (err == -EAGAIN)
1522 		goto again;
1523 	else if (err)
1524 		return err;
1525 
1526 	if (index > MAX_THREAD_CONTEXT) {
1527 		spin_lock(&vas_thread_id_lock);
1528 		ida_remove(&vas_thread_ida, index);
1529 		spin_unlock(&vas_thread_id_lock);
1530 		return -ENOMEM;
1531 	}
1532 
1533 	return index;
1534 }
1535 
1536 static void free_thread_tidr(int id)
1537 {
1538 	spin_lock(&vas_thread_id_lock);
1539 	ida_remove(&vas_thread_ida, id);
1540 	spin_unlock(&vas_thread_id_lock);
1541 }
1542 
1543 /*
1544  * Clear any TIDR value assigned to this thread.
1545  */
1546 void clear_thread_tidr(struct task_struct *t)
1547 {
1548 	if (!t->thread.tidr)
1549 		return;
1550 
1551 	if (!cpu_has_feature(CPU_FTR_ARCH_300)) {
1552 		WARN_ON_ONCE(1);
1553 		return;
1554 	}
1555 
1556 	mtspr(SPRN_TIDR, 0);
1557 	free_thread_tidr(t->thread.tidr);
1558 	t->thread.tidr = 0;
1559 }
1560 
1561 void arch_release_task_struct(struct task_struct *t)
1562 {
1563 	clear_thread_tidr(t);
1564 }
1565 
1566 /*
1567  * Assign a unique TIDR (thread id) for task @t and set it in the thread
1568  * structure. For now, we only support setting TIDR for 'current' task.
1569  */
1570 int set_thread_tidr(struct task_struct *t)
1571 {
1572 	int rc;
1573 
1574 	if (!cpu_has_feature(CPU_FTR_ARCH_300))
1575 		return -EINVAL;
1576 
1577 	if (t != current)
1578 		return -EINVAL;
1579 
1580 	if (t->thread.tidr)
1581 		return 0;
1582 
1583 	rc = assign_thread_tidr();
1584 	if (rc < 0)
1585 		return rc;
1586 
1587 	t->thread.tidr = rc;
1588 	mtspr(SPRN_TIDR, t->thread.tidr);
1589 
1590 	return 0;
1591 }
1592 
1593 #endif /* CONFIG_PPC64 */
1594 
1595 void
1596 release_thread(struct task_struct *t)
1597 {
1598 }
1599 
1600 /*
1601  * this gets called so that we can store coprocessor state into memory and
1602  * copy the current task into the new thread.
1603  */
1604 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1605 {
1606 	flush_all_to_thread(src);
1607 	/*
1608 	 * Flush TM state out so we can copy it.  __switch_to_tm() does this
1609 	 * flush but it removes the checkpointed state from the current CPU and
1610 	 * transitions the CPU out of TM mode.  Hence we need to call
1611 	 * tm_recheckpoint_new_task() (on the same task) to restore the
1612 	 * checkpointed state back and the TM mode.
1613 	 *
1614 	 * Can't pass dst because it isn't ready. Doesn't matter, passing
1615 	 * dst is only important for __switch_to()
1616 	 */
1617 	__switch_to_tm(src, src);
1618 
1619 	*dst = *src;
1620 
1621 	clear_task_ebb(dst);
1622 
1623 	return 0;
1624 }
1625 
1626 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1627 {
1628 #ifdef CONFIG_PPC_BOOK3S_64
1629 	unsigned long sp_vsid;
1630 	unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1631 
1632 	if (radix_enabled())
1633 		return;
1634 
1635 	if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1636 		sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1637 			<< SLB_VSID_SHIFT_1T;
1638 	else
1639 		sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1640 			<< SLB_VSID_SHIFT;
1641 	sp_vsid |= SLB_VSID_KERNEL | llp;
1642 	p->thread.ksp_vsid = sp_vsid;
1643 #endif
1644 }
1645 
1646 /*
1647  * Copy a thread..
1648  */
1649 
1650 /*
1651  * Copy architecture-specific thread state
1652  */
1653 int copy_thread(unsigned long clone_flags, unsigned long usp,
1654 		unsigned long kthread_arg, struct task_struct *p)
1655 {
1656 	struct pt_regs *childregs, *kregs;
1657 	extern void ret_from_fork(void);
1658 	extern void ret_from_kernel_thread(void);
1659 	void (*f)(void);
1660 	unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1661 	struct thread_info *ti = task_thread_info(p);
1662 
1663 	klp_init_thread_info(ti);
1664 
1665 	/* Copy registers */
1666 	sp -= sizeof(struct pt_regs);
1667 	childregs = (struct pt_regs *) sp;
1668 	if (unlikely(p->flags & PF_KTHREAD)) {
1669 		/* kernel thread */
1670 		memset(childregs, 0, sizeof(struct pt_regs));
1671 		childregs->gpr[1] = sp + sizeof(struct pt_regs);
1672 		/* function */
1673 		if (usp)
1674 			childregs->gpr[14] = ppc_function_entry((void *)usp);
1675 #ifdef CONFIG_PPC64
1676 		clear_tsk_thread_flag(p, TIF_32BIT);
1677 		childregs->softe = 1;
1678 #endif
1679 		childregs->gpr[15] = kthread_arg;
1680 		p->thread.regs = NULL;	/* no user register state */
1681 		ti->flags |= _TIF_RESTOREALL;
1682 		f = ret_from_kernel_thread;
1683 	} else {
1684 		/* user thread */
1685 		struct pt_regs *regs = current_pt_regs();
1686 		CHECK_FULL_REGS(regs);
1687 		*childregs = *regs;
1688 		if (usp)
1689 			childregs->gpr[1] = usp;
1690 		p->thread.regs = childregs;
1691 		childregs->gpr[3] = 0;  /* Result from fork() */
1692 		if (clone_flags & CLONE_SETTLS) {
1693 #ifdef CONFIG_PPC64
1694 			if (!is_32bit_task())
1695 				childregs->gpr[13] = childregs->gpr[6];
1696 			else
1697 #endif
1698 				childregs->gpr[2] = childregs->gpr[6];
1699 		}
1700 
1701 		f = ret_from_fork;
1702 	}
1703 	childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1704 	sp -= STACK_FRAME_OVERHEAD;
1705 
1706 	/*
1707 	 * The way this works is that at some point in the future
1708 	 * some task will call _switch to switch to the new task.
1709 	 * That will pop off the stack frame created below and start
1710 	 * the new task running at ret_from_fork.  The new task will
1711 	 * do some house keeping and then return from the fork or clone
1712 	 * system call, using the stack frame created above.
1713 	 */
1714 	((unsigned long *)sp)[0] = 0;
1715 	sp -= sizeof(struct pt_regs);
1716 	kregs = (struct pt_regs *) sp;
1717 	sp -= STACK_FRAME_OVERHEAD;
1718 	p->thread.ksp = sp;
1719 #ifdef CONFIG_PPC32
1720 	p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1721 				_ALIGN_UP(sizeof(struct thread_info), 16);
1722 #endif
1723 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1724 	p->thread.ptrace_bps[0] = NULL;
1725 #endif
1726 
1727 	p->thread.fp_save_area = NULL;
1728 #ifdef CONFIG_ALTIVEC
1729 	p->thread.vr_save_area = NULL;
1730 #endif
1731 
1732 	setup_ksp_vsid(p, sp);
1733 
1734 #ifdef CONFIG_PPC64
1735 	if (cpu_has_feature(CPU_FTR_DSCR)) {
1736 		p->thread.dscr_inherit = current->thread.dscr_inherit;
1737 		p->thread.dscr = mfspr(SPRN_DSCR);
1738 	}
1739 	if (cpu_has_feature(CPU_FTR_HAS_PPR))
1740 		p->thread.ppr = INIT_PPR;
1741 
1742 	p->thread.tidr = 0;
1743 #endif
1744 	kregs->nip = ppc_function_entry(f);
1745 	return 0;
1746 }
1747 
1748 /*
1749  * Set up a thread for executing a new program
1750  */
1751 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1752 {
1753 #ifdef CONFIG_PPC64
1754 	unsigned long load_addr = regs->gpr[2];	/* saved by ELF_PLAT_INIT */
1755 #endif
1756 
1757 	/*
1758 	 * If we exec out of a kernel thread then thread.regs will not be
1759 	 * set.  Do it now.
1760 	 */
1761 	if (!current->thread.regs) {
1762 		struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1763 		current->thread.regs = regs - 1;
1764 	}
1765 
1766 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1767 	/*
1768 	 * Clear any transactional state, we're exec()ing. The cause is
1769 	 * not important as there will never be a recheckpoint so it's not
1770 	 * user visible.
1771 	 */
1772 	if (MSR_TM_SUSPENDED(mfmsr()))
1773 		tm_reclaim_current(0);
1774 #endif
1775 
1776 	memset(regs->gpr, 0, sizeof(regs->gpr));
1777 	regs->ctr = 0;
1778 	regs->link = 0;
1779 	regs->xer = 0;
1780 	regs->ccr = 0;
1781 	regs->gpr[1] = sp;
1782 
1783 	/*
1784 	 * We have just cleared all the nonvolatile GPRs, so make
1785 	 * FULL_REGS(regs) return true.  This is necessary to allow
1786 	 * ptrace to examine the thread immediately after exec.
1787 	 */
1788 	regs->trap &= ~1UL;
1789 
1790 #ifdef CONFIG_PPC32
1791 	regs->mq = 0;
1792 	regs->nip = start;
1793 	regs->msr = MSR_USER;
1794 #else
1795 	if (!is_32bit_task()) {
1796 		unsigned long entry;
1797 
1798 		if (is_elf2_task()) {
1799 			/* Look ma, no function descriptors! */
1800 			entry = start;
1801 
1802 			/*
1803 			 * Ulrich says:
1804 			 *   The latest iteration of the ABI requires that when
1805 			 *   calling a function (at its global entry point),
1806 			 *   the caller must ensure r12 holds the entry point
1807 			 *   address (so that the function can quickly
1808 			 *   establish addressability).
1809 			 */
1810 			regs->gpr[12] = start;
1811 			/* Make sure that's restored on entry to userspace. */
1812 			set_thread_flag(TIF_RESTOREALL);
1813 		} else {
1814 			unsigned long toc;
1815 
1816 			/* start is a relocated pointer to the function
1817 			 * descriptor for the elf _start routine.  The first
1818 			 * entry in the function descriptor is the entry
1819 			 * address of _start and the second entry is the TOC
1820 			 * value we need to use.
1821 			 */
1822 			__get_user(entry, (unsigned long __user *)start);
1823 			__get_user(toc, (unsigned long __user *)start+1);
1824 
1825 			/* Check whether the e_entry function descriptor entries
1826 			 * need to be relocated before we can use them.
1827 			 */
1828 			if (load_addr != 0) {
1829 				entry += load_addr;
1830 				toc   += load_addr;
1831 			}
1832 			regs->gpr[2] = toc;
1833 		}
1834 		regs->nip = entry;
1835 		regs->msr = MSR_USER64;
1836 	} else {
1837 		regs->nip = start;
1838 		regs->gpr[2] = 0;
1839 		regs->msr = MSR_USER32;
1840 	}
1841 #endif
1842 #ifdef CONFIG_VSX
1843 	current->thread.used_vsr = 0;
1844 #endif
1845 	current->thread.load_fp = 0;
1846 	memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1847 	current->thread.fp_save_area = NULL;
1848 #ifdef CONFIG_ALTIVEC
1849 	memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1850 	current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1851 	current->thread.vr_save_area = NULL;
1852 	current->thread.vrsave = 0;
1853 	current->thread.used_vr = 0;
1854 	current->thread.load_vec = 0;
1855 #endif /* CONFIG_ALTIVEC */
1856 #ifdef CONFIG_SPE
1857 	memset(current->thread.evr, 0, sizeof(current->thread.evr));
1858 	current->thread.acc = 0;
1859 	current->thread.spefscr = 0;
1860 	current->thread.used_spe = 0;
1861 #endif /* CONFIG_SPE */
1862 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1863 	current->thread.tm_tfhar = 0;
1864 	current->thread.tm_texasr = 0;
1865 	current->thread.tm_tfiar = 0;
1866 	current->thread.load_tm = 0;
1867 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1868 }
1869 EXPORT_SYMBOL(start_thread);
1870 
1871 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1872 		| PR_FP_EXC_RES | PR_FP_EXC_INV)
1873 
1874 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1875 {
1876 	struct pt_regs *regs = tsk->thread.regs;
1877 
1878 	/* This is a bit hairy.  If we are an SPE enabled  processor
1879 	 * (have embedded fp) we store the IEEE exception enable flags in
1880 	 * fpexc_mode.  fpexc_mode is also used for setting FP exception
1881 	 * mode (asyn, precise, disabled) for 'Classic' FP. */
1882 	if (val & PR_FP_EXC_SW_ENABLE) {
1883 #ifdef CONFIG_SPE
1884 		if (cpu_has_feature(CPU_FTR_SPE)) {
1885 			/*
1886 			 * When the sticky exception bits are set
1887 			 * directly by userspace, it must call prctl
1888 			 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1889 			 * in the existing prctl settings) or
1890 			 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1891 			 * the bits being set).  <fenv.h> functions
1892 			 * saving and restoring the whole
1893 			 * floating-point environment need to do so
1894 			 * anyway to restore the prctl settings from
1895 			 * the saved environment.
1896 			 */
1897 			tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1898 			tsk->thread.fpexc_mode = val &
1899 				(PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1900 			return 0;
1901 		} else {
1902 			return -EINVAL;
1903 		}
1904 #else
1905 		return -EINVAL;
1906 #endif
1907 	}
1908 
1909 	/* on a CONFIG_SPE this does not hurt us.  The bits that
1910 	 * __pack_fe01 use do not overlap with bits used for
1911 	 * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1912 	 * on CONFIG_SPE implementations are reserved so writing to
1913 	 * them does not change anything */
1914 	if (val > PR_FP_EXC_PRECISE)
1915 		return -EINVAL;
1916 	tsk->thread.fpexc_mode = __pack_fe01(val);
1917 	if (regs != NULL && (regs->msr & MSR_FP) != 0)
1918 		regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1919 			| tsk->thread.fpexc_mode;
1920 	return 0;
1921 }
1922 
1923 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1924 {
1925 	unsigned int val;
1926 
1927 	if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1928 #ifdef CONFIG_SPE
1929 		if (cpu_has_feature(CPU_FTR_SPE)) {
1930 			/*
1931 			 * When the sticky exception bits are set
1932 			 * directly by userspace, it must call prctl
1933 			 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1934 			 * in the existing prctl settings) or
1935 			 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1936 			 * the bits being set).  <fenv.h> functions
1937 			 * saving and restoring the whole
1938 			 * floating-point environment need to do so
1939 			 * anyway to restore the prctl settings from
1940 			 * the saved environment.
1941 			 */
1942 			tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1943 			val = tsk->thread.fpexc_mode;
1944 		} else
1945 			return -EINVAL;
1946 #else
1947 		return -EINVAL;
1948 #endif
1949 	else
1950 		val = __unpack_fe01(tsk->thread.fpexc_mode);
1951 	return put_user(val, (unsigned int __user *) adr);
1952 }
1953 
1954 int set_endian(struct task_struct *tsk, unsigned int val)
1955 {
1956 	struct pt_regs *regs = tsk->thread.regs;
1957 
1958 	if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1959 	    (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1960 		return -EINVAL;
1961 
1962 	if (regs == NULL)
1963 		return -EINVAL;
1964 
1965 	if (val == PR_ENDIAN_BIG)
1966 		regs->msr &= ~MSR_LE;
1967 	else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1968 		regs->msr |= MSR_LE;
1969 	else
1970 		return -EINVAL;
1971 
1972 	return 0;
1973 }
1974 
1975 int get_endian(struct task_struct *tsk, unsigned long adr)
1976 {
1977 	struct pt_regs *regs = tsk->thread.regs;
1978 	unsigned int val;
1979 
1980 	if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1981 	    !cpu_has_feature(CPU_FTR_REAL_LE))
1982 		return -EINVAL;
1983 
1984 	if (regs == NULL)
1985 		return -EINVAL;
1986 
1987 	if (regs->msr & MSR_LE) {
1988 		if (cpu_has_feature(CPU_FTR_REAL_LE))
1989 			val = PR_ENDIAN_LITTLE;
1990 		else
1991 			val = PR_ENDIAN_PPC_LITTLE;
1992 	} else
1993 		val = PR_ENDIAN_BIG;
1994 
1995 	return put_user(val, (unsigned int __user *)adr);
1996 }
1997 
1998 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1999 {
2000 	tsk->thread.align_ctl = val;
2001 	return 0;
2002 }
2003 
2004 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
2005 {
2006 	return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
2007 }
2008 
2009 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
2010 				  unsigned long nbytes)
2011 {
2012 	unsigned long stack_page;
2013 	unsigned long cpu = task_cpu(p);
2014 
2015 	/*
2016 	 * Avoid crashing if the stack has overflowed and corrupted
2017 	 * task_cpu(p), which is in the thread_info struct.
2018 	 */
2019 	if (cpu < NR_CPUS && cpu_possible(cpu)) {
2020 		stack_page = (unsigned long) hardirq_ctx[cpu];
2021 		if (sp >= stack_page + sizeof(struct thread_struct)
2022 		    && sp <= stack_page + THREAD_SIZE - nbytes)
2023 			return 1;
2024 
2025 		stack_page = (unsigned long) softirq_ctx[cpu];
2026 		if (sp >= stack_page + sizeof(struct thread_struct)
2027 		    && sp <= stack_page + THREAD_SIZE - nbytes)
2028 			return 1;
2029 	}
2030 	return 0;
2031 }
2032 
2033 int validate_sp(unsigned long sp, struct task_struct *p,
2034 		       unsigned long nbytes)
2035 {
2036 	unsigned long stack_page = (unsigned long)task_stack_page(p);
2037 
2038 	if (sp >= stack_page + sizeof(struct thread_struct)
2039 	    && sp <= stack_page + THREAD_SIZE - nbytes)
2040 		return 1;
2041 
2042 	return valid_irq_stack(sp, p, nbytes);
2043 }
2044 
2045 EXPORT_SYMBOL(validate_sp);
2046 
2047 unsigned long get_wchan(struct task_struct *p)
2048 {
2049 	unsigned long ip, sp;
2050 	int count = 0;
2051 
2052 	if (!p || p == current || p->state == TASK_RUNNING)
2053 		return 0;
2054 
2055 	sp = p->thread.ksp;
2056 	if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2057 		return 0;
2058 
2059 	do {
2060 		sp = *(unsigned long *)sp;
2061 		if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2062 		    p->state == TASK_RUNNING)
2063 			return 0;
2064 		if (count > 0) {
2065 			ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2066 			if (!in_sched_functions(ip))
2067 				return ip;
2068 		}
2069 	} while (count++ < 16);
2070 	return 0;
2071 }
2072 
2073 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2074 
2075 void show_stack(struct task_struct *tsk, unsigned long *stack)
2076 {
2077 	unsigned long sp, ip, lr, newsp;
2078 	int count = 0;
2079 	int firstframe = 1;
2080 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2081 	int curr_frame = current->curr_ret_stack;
2082 	extern void return_to_handler(void);
2083 	unsigned long rth = (unsigned long)return_to_handler;
2084 #endif
2085 
2086 	sp = (unsigned long) stack;
2087 	if (tsk == NULL)
2088 		tsk = current;
2089 	if (sp == 0) {
2090 		if (tsk == current)
2091 			sp = current_stack_pointer();
2092 		else
2093 			sp = tsk->thread.ksp;
2094 	}
2095 
2096 	lr = 0;
2097 	printk("Call Trace:\n");
2098 	do {
2099 		if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2100 			return;
2101 
2102 		stack = (unsigned long *) sp;
2103 		newsp = stack[0];
2104 		ip = stack[STACK_FRAME_LR_SAVE];
2105 		if (!firstframe || ip != lr) {
2106 			printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2107 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2108 			if ((ip == rth) && curr_frame >= 0) {
2109 				pr_cont(" (%pS)",
2110 				       (void *)current->ret_stack[curr_frame].ret);
2111 				curr_frame--;
2112 			}
2113 #endif
2114 			if (firstframe)
2115 				pr_cont(" (unreliable)");
2116 			pr_cont("\n");
2117 		}
2118 		firstframe = 0;
2119 
2120 		/*
2121 		 * See if this is an exception frame.
2122 		 * We look for the "regshere" marker in the current frame.
2123 		 */
2124 		if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2125 		    && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2126 			struct pt_regs *regs = (struct pt_regs *)
2127 				(sp + STACK_FRAME_OVERHEAD);
2128 			lr = regs->link;
2129 			printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
2130 			       regs->trap, (void *)regs->nip, (void *)lr);
2131 			firstframe = 1;
2132 		}
2133 
2134 		sp = newsp;
2135 	} while (count++ < kstack_depth_to_print);
2136 }
2137 
2138 #ifdef CONFIG_PPC64
2139 /* Called with hard IRQs off */
2140 void notrace __ppc64_runlatch_on(void)
2141 {
2142 	struct thread_info *ti = current_thread_info();
2143 
2144 	if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2145 		/*
2146 		 * Least significant bit (RUN) is the only writable bit of
2147 		 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2148 		 * earliest ISA where this is the case, but it's convenient.
2149 		 */
2150 		mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2151 	} else {
2152 		unsigned long ctrl;
2153 
2154 		/*
2155 		 * Some architectures (e.g., Cell) have writable fields other
2156 		 * than RUN, so do the read-modify-write.
2157 		 */
2158 		ctrl = mfspr(SPRN_CTRLF);
2159 		ctrl |= CTRL_RUNLATCH;
2160 		mtspr(SPRN_CTRLT, ctrl);
2161 	}
2162 
2163 	ti->local_flags |= _TLF_RUNLATCH;
2164 }
2165 
2166 /* Called with hard IRQs off */
2167 void notrace __ppc64_runlatch_off(void)
2168 {
2169 	struct thread_info *ti = current_thread_info();
2170 
2171 	ti->local_flags &= ~_TLF_RUNLATCH;
2172 
2173 	if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2174 		mtspr(SPRN_CTRLT, 0);
2175 	} else {
2176 		unsigned long ctrl;
2177 
2178 		ctrl = mfspr(SPRN_CTRLF);
2179 		ctrl &= ~CTRL_RUNLATCH;
2180 		mtspr(SPRN_CTRLT, ctrl);
2181 	}
2182 }
2183 #endif /* CONFIG_PPC64 */
2184 
2185 unsigned long arch_align_stack(unsigned long sp)
2186 {
2187 	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2188 		sp -= get_random_int() & ~PAGE_MASK;
2189 	return sp & ~0xf;
2190 }
2191 
2192 static inline unsigned long brk_rnd(void)
2193 {
2194         unsigned long rnd = 0;
2195 
2196 	/* 8MB for 32bit, 1GB for 64bit */
2197 	if (is_32bit_task())
2198 		rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2199 	else
2200 		rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2201 
2202 	return rnd << PAGE_SHIFT;
2203 }
2204 
2205 unsigned long arch_randomize_brk(struct mm_struct *mm)
2206 {
2207 	unsigned long base = mm->brk;
2208 	unsigned long ret;
2209 
2210 #ifdef CONFIG_PPC_BOOK3S_64
2211 	/*
2212 	 * If we are using 1TB segments and we are allowed to randomise
2213 	 * the heap, we can put it above 1TB so it is backed by a 1TB
2214 	 * segment. Otherwise the heap will be in the bottom 1TB
2215 	 * which always uses 256MB segments and this may result in a
2216 	 * performance penalty. We don't need to worry about radix. For
2217 	 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2218 	 */
2219 	if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2220 		base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2221 #endif
2222 
2223 	ret = PAGE_ALIGN(base + brk_rnd());
2224 
2225 	if (ret < mm->brk)
2226 		return mm->brk;
2227 
2228 	return ret;
2229 }
2230 
2231