1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Derived from "arch/i386/kernel/process.c" 4 * Copyright (C) 1995 Linus Torvalds 5 * 6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and 7 * Paul Mackerras (paulus@cs.anu.edu.au) 8 * 9 * PowerPC version 10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 11 */ 12 13 #include <linux/errno.h> 14 #include <linux/sched.h> 15 #include <linux/sched/debug.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/task_stack.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/smp.h> 21 #include <linux/stddef.h> 22 #include <linux/unistd.h> 23 #include <linux/ptrace.h> 24 #include <linux/slab.h> 25 #include <linux/user.h> 26 #include <linux/elf.h> 27 #include <linux/prctl.h> 28 #include <linux/init_task.h> 29 #include <linux/export.h> 30 #include <linux/kallsyms.h> 31 #include <linux/mqueue.h> 32 #include <linux/hardirq.h> 33 #include <linux/utsname.h> 34 #include <linux/ftrace.h> 35 #include <linux/kernel_stat.h> 36 #include <linux/personality.h> 37 #include <linux/random.h> 38 #include <linux/hw_breakpoint.h> 39 #include <linux/uaccess.h> 40 #include <linux/elf-randomize.h> 41 #include <linux/pkeys.h> 42 #include <linux/seq_buf.h> 43 44 #include <asm/io.h> 45 #include <asm/processor.h> 46 #include <asm/mmu.h> 47 #include <asm/prom.h> 48 #include <asm/machdep.h> 49 #include <asm/time.h> 50 #include <asm/runlatch.h> 51 #include <asm/syscalls.h> 52 #include <asm/switch_to.h> 53 #include <asm/tm.h> 54 #include <asm/debug.h> 55 #ifdef CONFIG_PPC64 56 #include <asm/firmware.h> 57 #include <asm/hw_irq.h> 58 #endif 59 #include <asm/code-patching.h> 60 #include <asm/exec.h> 61 #include <asm/livepatch.h> 62 #include <asm/cpu_has_feature.h> 63 #include <asm/asm-prototypes.h> 64 #include <asm/stacktrace.h> 65 #include <asm/hw_breakpoint.h> 66 67 #include <linux/kprobes.h> 68 #include <linux/kdebug.h> 69 70 /* Transactional Memory debug */ 71 #ifdef TM_DEBUG_SW 72 #define TM_DEBUG(x...) printk(KERN_INFO x) 73 #else 74 #define TM_DEBUG(x...) do { } while(0) 75 #endif 76 77 extern unsigned long _get_SP(void); 78 79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 80 /* 81 * Are we running in "Suspend disabled" mode? If so we have to block any 82 * sigreturn that would get us into suspended state, and we also warn in some 83 * other paths that we should never reach with suspend disabled. 84 */ 85 bool tm_suspend_disabled __ro_after_init = false; 86 87 static void check_if_tm_restore_required(struct task_struct *tsk) 88 { 89 /* 90 * If we are saving the current thread's registers, and the 91 * thread is in a transactional state, set the TIF_RESTORE_TM 92 * bit so that we know to restore the registers before 93 * returning to userspace. 94 */ 95 if (tsk == current && tsk->thread.regs && 96 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 97 !test_thread_flag(TIF_RESTORE_TM)) { 98 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 99 set_thread_flag(TIF_RESTORE_TM); 100 } 101 } 102 103 #else 104 static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 105 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 106 107 bool strict_msr_control; 108 EXPORT_SYMBOL(strict_msr_control); 109 110 static int __init enable_strict_msr_control(char *str) 111 { 112 strict_msr_control = true; 113 pr_info("Enabling strict facility control\n"); 114 115 return 0; 116 } 117 early_param("ppc_strict_facility_enable", enable_strict_msr_control); 118 119 /* notrace because it's called by restore_math */ 120 unsigned long notrace msr_check_and_set(unsigned long bits) 121 { 122 unsigned long oldmsr = mfmsr(); 123 unsigned long newmsr; 124 125 newmsr = oldmsr | bits; 126 127 #ifdef CONFIG_VSX 128 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 129 newmsr |= MSR_VSX; 130 #endif 131 132 if (oldmsr != newmsr) 133 mtmsr_isync(newmsr); 134 135 return newmsr; 136 } 137 EXPORT_SYMBOL_GPL(msr_check_and_set); 138 139 /* notrace because it's called by restore_math */ 140 void notrace __msr_check_and_clear(unsigned long bits) 141 { 142 unsigned long oldmsr = mfmsr(); 143 unsigned long newmsr; 144 145 newmsr = oldmsr & ~bits; 146 147 #ifdef CONFIG_VSX 148 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 149 newmsr &= ~MSR_VSX; 150 #endif 151 152 if (oldmsr != newmsr) 153 mtmsr_isync(newmsr); 154 } 155 EXPORT_SYMBOL(__msr_check_and_clear); 156 157 #ifdef CONFIG_PPC_FPU 158 static void __giveup_fpu(struct task_struct *tsk) 159 { 160 unsigned long msr; 161 162 save_fpu(tsk); 163 msr = tsk->thread.regs->msr; 164 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); 165 #ifdef CONFIG_VSX 166 if (cpu_has_feature(CPU_FTR_VSX)) 167 msr &= ~MSR_VSX; 168 #endif 169 tsk->thread.regs->msr = msr; 170 } 171 172 void giveup_fpu(struct task_struct *tsk) 173 { 174 check_if_tm_restore_required(tsk); 175 176 msr_check_and_set(MSR_FP); 177 __giveup_fpu(tsk); 178 msr_check_and_clear(MSR_FP); 179 } 180 EXPORT_SYMBOL(giveup_fpu); 181 182 /* 183 * Make sure the floating-point register state in the 184 * the thread_struct is up to date for task tsk. 185 */ 186 void flush_fp_to_thread(struct task_struct *tsk) 187 { 188 if (tsk->thread.regs) { 189 /* 190 * We need to disable preemption here because if we didn't, 191 * another process could get scheduled after the regs->msr 192 * test but before we have finished saving the FP registers 193 * to the thread_struct. That process could take over the 194 * FPU, and then when we get scheduled again we would store 195 * bogus values for the remaining FP registers. 196 */ 197 preempt_disable(); 198 if (tsk->thread.regs->msr & MSR_FP) { 199 /* 200 * This should only ever be called for current or 201 * for a stopped child process. Since we save away 202 * the FP register state on context switch, 203 * there is something wrong if a stopped child appears 204 * to still have its FP state in the CPU registers. 205 */ 206 BUG_ON(tsk != current); 207 giveup_fpu(tsk); 208 } 209 preempt_enable(); 210 } 211 } 212 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 213 214 void enable_kernel_fp(void) 215 { 216 unsigned long cpumsr; 217 218 WARN_ON(preemptible()); 219 220 cpumsr = msr_check_and_set(MSR_FP); 221 222 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 223 check_if_tm_restore_required(current); 224 /* 225 * If a thread has already been reclaimed then the 226 * checkpointed registers are on the CPU but have definitely 227 * been saved by the reclaim code. Don't need to and *cannot* 228 * giveup as this would save to the 'live' structure not the 229 * checkpointed structure. 230 */ 231 if (!MSR_TM_ACTIVE(cpumsr) && 232 MSR_TM_ACTIVE(current->thread.regs->msr)) 233 return; 234 __giveup_fpu(current); 235 } 236 } 237 EXPORT_SYMBOL(enable_kernel_fp); 238 #endif /* CONFIG_PPC_FPU */ 239 240 #ifdef CONFIG_ALTIVEC 241 static void __giveup_altivec(struct task_struct *tsk) 242 { 243 unsigned long msr; 244 245 save_altivec(tsk); 246 msr = tsk->thread.regs->msr; 247 msr &= ~MSR_VEC; 248 #ifdef CONFIG_VSX 249 if (cpu_has_feature(CPU_FTR_VSX)) 250 msr &= ~MSR_VSX; 251 #endif 252 tsk->thread.regs->msr = msr; 253 } 254 255 void giveup_altivec(struct task_struct *tsk) 256 { 257 check_if_tm_restore_required(tsk); 258 259 msr_check_and_set(MSR_VEC); 260 __giveup_altivec(tsk); 261 msr_check_and_clear(MSR_VEC); 262 } 263 EXPORT_SYMBOL(giveup_altivec); 264 265 void enable_kernel_altivec(void) 266 { 267 unsigned long cpumsr; 268 269 WARN_ON(preemptible()); 270 271 cpumsr = msr_check_and_set(MSR_VEC); 272 273 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 274 check_if_tm_restore_required(current); 275 /* 276 * If a thread has already been reclaimed then the 277 * checkpointed registers are on the CPU but have definitely 278 * been saved by the reclaim code. Don't need to and *cannot* 279 * giveup as this would save to the 'live' structure not the 280 * checkpointed structure. 281 */ 282 if (!MSR_TM_ACTIVE(cpumsr) && 283 MSR_TM_ACTIVE(current->thread.regs->msr)) 284 return; 285 __giveup_altivec(current); 286 } 287 } 288 EXPORT_SYMBOL(enable_kernel_altivec); 289 290 /* 291 * Make sure the VMX/Altivec register state in the 292 * the thread_struct is up to date for task tsk. 293 */ 294 void flush_altivec_to_thread(struct task_struct *tsk) 295 { 296 if (tsk->thread.regs) { 297 preempt_disable(); 298 if (tsk->thread.regs->msr & MSR_VEC) { 299 BUG_ON(tsk != current); 300 giveup_altivec(tsk); 301 } 302 preempt_enable(); 303 } 304 } 305 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 306 #endif /* CONFIG_ALTIVEC */ 307 308 #ifdef CONFIG_VSX 309 static void __giveup_vsx(struct task_struct *tsk) 310 { 311 unsigned long msr = tsk->thread.regs->msr; 312 313 /* 314 * We should never be ssetting MSR_VSX without also setting 315 * MSR_FP and MSR_VEC 316 */ 317 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); 318 319 /* __giveup_fpu will clear MSR_VSX */ 320 if (msr & MSR_FP) 321 __giveup_fpu(tsk); 322 if (msr & MSR_VEC) 323 __giveup_altivec(tsk); 324 } 325 326 static void giveup_vsx(struct task_struct *tsk) 327 { 328 check_if_tm_restore_required(tsk); 329 330 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 331 __giveup_vsx(tsk); 332 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 333 } 334 335 void enable_kernel_vsx(void) 336 { 337 unsigned long cpumsr; 338 339 WARN_ON(preemptible()); 340 341 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 342 343 if (current->thread.regs && 344 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { 345 check_if_tm_restore_required(current); 346 /* 347 * If a thread has already been reclaimed then the 348 * checkpointed registers are on the CPU but have definitely 349 * been saved by the reclaim code. Don't need to and *cannot* 350 * giveup as this would save to the 'live' structure not the 351 * checkpointed structure. 352 */ 353 if (!MSR_TM_ACTIVE(cpumsr) && 354 MSR_TM_ACTIVE(current->thread.regs->msr)) 355 return; 356 __giveup_vsx(current); 357 } 358 } 359 EXPORT_SYMBOL(enable_kernel_vsx); 360 361 void flush_vsx_to_thread(struct task_struct *tsk) 362 { 363 if (tsk->thread.regs) { 364 preempt_disable(); 365 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { 366 BUG_ON(tsk != current); 367 giveup_vsx(tsk); 368 } 369 preempt_enable(); 370 } 371 } 372 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 373 #endif /* CONFIG_VSX */ 374 375 #ifdef CONFIG_SPE 376 void giveup_spe(struct task_struct *tsk) 377 { 378 check_if_tm_restore_required(tsk); 379 380 msr_check_and_set(MSR_SPE); 381 __giveup_spe(tsk); 382 msr_check_and_clear(MSR_SPE); 383 } 384 EXPORT_SYMBOL(giveup_spe); 385 386 void enable_kernel_spe(void) 387 { 388 WARN_ON(preemptible()); 389 390 msr_check_and_set(MSR_SPE); 391 392 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 393 check_if_tm_restore_required(current); 394 __giveup_spe(current); 395 } 396 } 397 EXPORT_SYMBOL(enable_kernel_spe); 398 399 void flush_spe_to_thread(struct task_struct *tsk) 400 { 401 if (tsk->thread.regs) { 402 preempt_disable(); 403 if (tsk->thread.regs->msr & MSR_SPE) { 404 BUG_ON(tsk != current); 405 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 406 giveup_spe(tsk); 407 } 408 preempt_enable(); 409 } 410 } 411 #endif /* CONFIG_SPE */ 412 413 static unsigned long msr_all_available; 414 415 static int __init init_msr_all_available(void) 416 { 417 #ifdef CONFIG_PPC_FPU 418 msr_all_available |= MSR_FP; 419 #endif 420 #ifdef CONFIG_ALTIVEC 421 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 422 msr_all_available |= MSR_VEC; 423 #endif 424 #ifdef CONFIG_VSX 425 if (cpu_has_feature(CPU_FTR_VSX)) 426 msr_all_available |= MSR_VSX; 427 #endif 428 #ifdef CONFIG_SPE 429 if (cpu_has_feature(CPU_FTR_SPE)) 430 msr_all_available |= MSR_SPE; 431 #endif 432 433 return 0; 434 } 435 early_initcall(init_msr_all_available); 436 437 void giveup_all(struct task_struct *tsk) 438 { 439 unsigned long usermsr; 440 441 if (!tsk->thread.regs) 442 return; 443 444 check_if_tm_restore_required(tsk); 445 446 usermsr = tsk->thread.regs->msr; 447 448 if ((usermsr & msr_all_available) == 0) 449 return; 450 451 msr_check_and_set(msr_all_available); 452 453 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 454 455 #ifdef CONFIG_PPC_FPU 456 if (usermsr & MSR_FP) 457 __giveup_fpu(tsk); 458 #endif 459 #ifdef CONFIG_ALTIVEC 460 if (usermsr & MSR_VEC) 461 __giveup_altivec(tsk); 462 #endif 463 #ifdef CONFIG_SPE 464 if (usermsr & MSR_SPE) 465 __giveup_spe(tsk); 466 #endif 467 468 msr_check_and_clear(msr_all_available); 469 } 470 EXPORT_SYMBOL(giveup_all); 471 472 #ifdef CONFIG_PPC_BOOK3S_64 473 #ifdef CONFIG_PPC_FPU 474 static int restore_fp(struct task_struct *tsk) 475 { 476 if (tsk->thread.load_fp) { 477 load_fp_state(¤t->thread.fp_state); 478 current->thread.load_fp++; 479 return 1; 480 } 481 return 0; 482 } 483 #else 484 static int restore_fp(struct task_struct *tsk) { return 0; } 485 #endif /* CONFIG_PPC_FPU */ 486 487 #ifdef CONFIG_ALTIVEC 488 #define loadvec(thr) ((thr).load_vec) 489 static int restore_altivec(struct task_struct *tsk) 490 { 491 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) { 492 load_vr_state(&tsk->thread.vr_state); 493 tsk->thread.used_vr = 1; 494 tsk->thread.load_vec++; 495 496 return 1; 497 } 498 return 0; 499 } 500 #else 501 #define loadvec(thr) 0 502 static inline int restore_altivec(struct task_struct *tsk) { return 0; } 503 #endif /* CONFIG_ALTIVEC */ 504 505 #ifdef CONFIG_VSX 506 static int restore_vsx(struct task_struct *tsk) 507 { 508 if (cpu_has_feature(CPU_FTR_VSX)) { 509 tsk->thread.used_vsr = 1; 510 return 1; 511 } 512 513 return 0; 514 } 515 #else 516 static inline int restore_vsx(struct task_struct *tsk) { return 0; } 517 #endif /* CONFIG_VSX */ 518 519 /* 520 * The exception exit path calls restore_math() with interrupts hard disabled 521 * but the soft irq state not "reconciled". ftrace code that calls 522 * local_irq_save/restore causes warnings. 523 * 524 * Rather than complicate the exit path, just don't trace restore_math. This 525 * could be done by having ftrace entry code check for this un-reconciled 526 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and 527 * temporarily fix it up for the duration of the ftrace call. 528 */ 529 void notrace restore_math(struct pt_regs *regs) 530 { 531 unsigned long msr; 532 533 if (!MSR_TM_ACTIVE(regs->msr) && 534 !current->thread.load_fp && !loadvec(current->thread)) 535 return; 536 537 msr = regs->msr; 538 msr_check_and_set(msr_all_available); 539 540 /* 541 * Only reload if the bit is not set in the user MSR, the bit BEING set 542 * indicates that the registers are hot 543 */ 544 if ((!(msr & MSR_FP)) && restore_fp(current)) 545 msr |= MSR_FP | current->thread.fpexc_mode; 546 547 if ((!(msr & MSR_VEC)) && restore_altivec(current)) 548 msr |= MSR_VEC; 549 550 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && 551 restore_vsx(current)) { 552 msr |= MSR_VSX; 553 } 554 555 msr_check_and_clear(msr_all_available); 556 557 regs->msr = msr; 558 } 559 #endif 560 561 static void save_all(struct task_struct *tsk) 562 { 563 unsigned long usermsr; 564 565 if (!tsk->thread.regs) 566 return; 567 568 usermsr = tsk->thread.regs->msr; 569 570 if ((usermsr & msr_all_available) == 0) 571 return; 572 573 msr_check_and_set(msr_all_available); 574 575 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); 576 577 if (usermsr & MSR_FP) 578 save_fpu(tsk); 579 580 if (usermsr & MSR_VEC) 581 save_altivec(tsk); 582 583 if (usermsr & MSR_SPE) 584 __giveup_spe(tsk); 585 586 msr_check_and_clear(msr_all_available); 587 thread_pkey_regs_save(&tsk->thread); 588 } 589 590 void flush_all_to_thread(struct task_struct *tsk) 591 { 592 if (tsk->thread.regs) { 593 preempt_disable(); 594 BUG_ON(tsk != current); 595 #ifdef CONFIG_SPE 596 if (tsk->thread.regs->msr & MSR_SPE) 597 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 598 #endif 599 save_all(tsk); 600 601 preempt_enable(); 602 } 603 } 604 EXPORT_SYMBOL(flush_all_to_thread); 605 606 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 607 void do_send_trap(struct pt_regs *regs, unsigned long address, 608 unsigned long error_code, int breakpt) 609 { 610 current->thread.trap_nr = TRAP_HWBKPT; 611 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 612 11, SIGSEGV) == NOTIFY_STOP) 613 return; 614 615 /* Deliver the signal to userspace */ 616 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ 617 (void __user *)address); 618 } 619 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 620 void do_break (struct pt_regs *regs, unsigned long address, 621 unsigned long error_code) 622 { 623 current->thread.trap_nr = TRAP_HWBKPT; 624 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 625 11, SIGSEGV) == NOTIFY_STOP) 626 return; 627 628 if (debugger_break_match(regs)) 629 return; 630 631 /* Deliver the signal to userspace */ 632 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address); 633 } 634 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 635 636 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]); 637 638 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 639 /* 640 * Set the debug registers back to their default "safe" values. 641 */ 642 static void set_debug_reg_defaults(struct thread_struct *thread) 643 { 644 thread->debug.iac1 = thread->debug.iac2 = 0; 645 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 646 thread->debug.iac3 = thread->debug.iac4 = 0; 647 #endif 648 thread->debug.dac1 = thread->debug.dac2 = 0; 649 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 650 thread->debug.dvc1 = thread->debug.dvc2 = 0; 651 #endif 652 thread->debug.dbcr0 = 0; 653 #ifdef CONFIG_BOOKE 654 /* 655 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 656 */ 657 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 658 DBCR1_IAC3US | DBCR1_IAC4US; 659 /* 660 * Force Data Address Compare User/Supervisor bits to be User-only 661 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 662 */ 663 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 664 #else 665 thread->debug.dbcr1 = 0; 666 #endif 667 } 668 669 static void prime_debug_regs(struct debug_reg *debug) 670 { 671 /* 672 * We could have inherited MSR_DE from userspace, since 673 * it doesn't get cleared on exception entry. Make sure 674 * MSR_DE is clear before we enable any debug events. 675 */ 676 mtmsr(mfmsr() & ~MSR_DE); 677 678 mtspr(SPRN_IAC1, debug->iac1); 679 mtspr(SPRN_IAC2, debug->iac2); 680 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 681 mtspr(SPRN_IAC3, debug->iac3); 682 mtspr(SPRN_IAC4, debug->iac4); 683 #endif 684 mtspr(SPRN_DAC1, debug->dac1); 685 mtspr(SPRN_DAC2, debug->dac2); 686 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 687 mtspr(SPRN_DVC1, debug->dvc1); 688 mtspr(SPRN_DVC2, debug->dvc2); 689 #endif 690 mtspr(SPRN_DBCR0, debug->dbcr0); 691 mtspr(SPRN_DBCR1, debug->dbcr1); 692 #ifdef CONFIG_BOOKE 693 mtspr(SPRN_DBCR2, debug->dbcr2); 694 #endif 695 } 696 /* 697 * Unless neither the old or new thread are making use of the 698 * debug registers, set the debug registers from the values 699 * stored in the new thread. 700 */ 701 void switch_booke_debug_regs(struct debug_reg *new_debug) 702 { 703 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 704 || (new_debug->dbcr0 & DBCR0_IDM)) 705 prime_debug_regs(new_debug); 706 } 707 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 708 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 709 #ifndef CONFIG_HAVE_HW_BREAKPOINT 710 static void set_breakpoint(int i, struct arch_hw_breakpoint *brk) 711 { 712 preempt_disable(); 713 __set_breakpoint(i, brk); 714 preempt_enable(); 715 } 716 717 static void set_debug_reg_defaults(struct thread_struct *thread) 718 { 719 int i; 720 struct arch_hw_breakpoint null_brk = {0}; 721 722 for (i = 0; i < nr_wp_slots(); i++) { 723 thread->hw_brk[i] = null_brk; 724 if (ppc_breakpoint_available()) 725 set_breakpoint(i, &thread->hw_brk[i]); 726 } 727 } 728 729 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 730 struct arch_hw_breakpoint *b) 731 { 732 if (a->address != b->address) 733 return false; 734 if (a->type != b->type) 735 return false; 736 if (a->len != b->len) 737 return false; 738 /* no need to check hw_len. it's calculated from address and len */ 739 return true; 740 } 741 742 static void switch_hw_breakpoint(struct task_struct *new) 743 { 744 int i; 745 746 for (i = 0; i < nr_wp_slots(); i++) { 747 if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]), 748 &new->thread.hw_brk[i]))) 749 continue; 750 751 __set_breakpoint(i, &new->thread.hw_brk[i]); 752 } 753 } 754 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 755 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 756 757 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 758 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 759 { 760 mtspr(SPRN_DAC1, dabr); 761 #ifdef CONFIG_PPC_47x 762 isync(); 763 #endif 764 return 0; 765 } 766 #elif defined(CONFIG_PPC_BOOK3S) 767 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 768 { 769 mtspr(SPRN_DABR, dabr); 770 if (cpu_has_feature(CPU_FTR_DABRX)) 771 mtspr(SPRN_DABRX, dabrx); 772 return 0; 773 } 774 #else 775 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 776 { 777 return -EINVAL; 778 } 779 #endif 780 781 static inline int set_dabr(struct arch_hw_breakpoint *brk) 782 { 783 unsigned long dabr, dabrx; 784 785 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 786 dabrx = ((brk->type >> 3) & 0x7); 787 788 if (ppc_md.set_dabr) 789 return ppc_md.set_dabr(dabr, dabrx); 790 791 return __set_dabr(dabr, dabrx); 792 } 793 794 static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk) 795 { 796 unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW | 797 LCTRL1_CRWF_RW; 798 unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN; 799 unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE); 800 unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE); 801 802 if (start_addr == 0) 803 lctrl2 |= LCTRL2_LW0LA_F; 804 else if (end_addr == 0) 805 lctrl2 |= LCTRL2_LW0LA_E; 806 else 807 lctrl2 |= LCTRL2_LW0LA_EandF; 808 809 mtspr(SPRN_LCTRL2, 0); 810 811 if ((brk->type & HW_BRK_TYPE_RDWR) == 0) 812 return 0; 813 814 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) 815 lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO; 816 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) 817 lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO; 818 819 mtspr(SPRN_CMPE, start_addr - 1); 820 mtspr(SPRN_CMPF, end_addr); 821 mtspr(SPRN_LCTRL1, lctrl1); 822 mtspr(SPRN_LCTRL2, lctrl2); 823 824 return 0; 825 } 826 827 void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk) 828 { 829 memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk)); 830 831 if (dawr_enabled()) 832 // Power8 or later 833 set_dawr(nr, brk); 834 else if (IS_ENABLED(CONFIG_PPC_8xx)) 835 set_breakpoint_8xx(brk); 836 else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) 837 // Power7 or earlier 838 set_dabr(brk); 839 else 840 // Shouldn't happen due to higher level checks 841 WARN_ON_ONCE(1); 842 } 843 844 /* Check if we have DAWR or DABR hardware */ 845 bool ppc_breakpoint_available(void) 846 { 847 if (dawr_enabled()) 848 return true; /* POWER8 DAWR or POWER9 forced DAWR */ 849 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 850 return false; /* POWER9 with DAWR disabled */ 851 /* DABR: Everything but POWER8 and POWER9 */ 852 return true; 853 } 854 EXPORT_SYMBOL_GPL(ppc_breakpoint_available); 855 856 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 857 858 static inline bool tm_enabled(struct task_struct *tsk) 859 { 860 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); 861 } 862 863 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause) 864 { 865 /* 866 * Use the current MSR TM suspended bit to track if we have 867 * checkpointed state outstanding. 868 * On signal delivery, we'd normally reclaim the checkpointed 869 * state to obtain stack pointer (see:get_tm_stackpointer()). 870 * This will then directly return to userspace without going 871 * through __switch_to(). However, if the stack frame is bad, 872 * we need to exit this thread which calls __switch_to() which 873 * will again attempt to reclaim the already saved tm state. 874 * Hence we need to check that we've not already reclaimed 875 * this state. 876 * We do this using the current MSR, rather tracking it in 877 * some specific thread_struct bit, as it has the additional 878 * benefit of checking for a potential TM bad thing exception. 879 */ 880 if (!MSR_TM_SUSPENDED(mfmsr())) 881 return; 882 883 giveup_all(container_of(thr, struct task_struct, thread)); 884 885 tm_reclaim(thr, cause); 886 887 /* 888 * If we are in a transaction and FP is off then we can't have 889 * used FP inside that transaction. Hence the checkpointed 890 * state is the same as the live state. We need to copy the 891 * live state to the checkpointed state so that when the 892 * transaction is restored, the checkpointed state is correct 893 * and the aborted transaction sees the correct state. We use 894 * ckpt_regs.msr here as that's what tm_reclaim will use to 895 * determine if it's going to write the checkpointed state or 896 * not. So either this will write the checkpointed registers, 897 * or reclaim will. Similarly for VMX. 898 */ 899 if ((thr->ckpt_regs.msr & MSR_FP) == 0) 900 memcpy(&thr->ckfp_state, &thr->fp_state, 901 sizeof(struct thread_fp_state)); 902 if ((thr->ckpt_regs.msr & MSR_VEC) == 0) 903 memcpy(&thr->ckvr_state, &thr->vr_state, 904 sizeof(struct thread_vr_state)); 905 } 906 907 void tm_reclaim_current(uint8_t cause) 908 { 909 tm_enable(); 910 tm_reclaim_thread(¤t->thread, cause); 911 } 912 913 static inline void tm_reclaim_task(struct task_struct *tsk) 914 { 915 /* We have to work out if we're switching from/to a task that's in the 916 * middle of a transaction. 917 * 918 * In switching we need to maintain a 2nd register state as 919 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 920 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and 921 * ckvr_state 922 * 923 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 924 */ 925 struct thread_struct *thr = &tsk->thread; 926 927 if (!thr->regs) 928 return; 929 930 if (!MSR_TM_ACTIVE(thr->regs->msr)) 931 goto out_and_saveregs; 932 933 WARN_ON(tm_suspend_disabled); 934 935 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 936 "ccr=%lx, msr=%lx, trap=%lx)\n", 937 tsk->pid, thr->regs->nip, 938 thr->regs->ccr, thr->regs->msr, 939 thr->regs->trap); 940 941 tm_reclaim_thread(thr, TM_CAUSE_RESCHED); 942 943 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 944 tsk->pid); 945 946 out_and_saveregs: 947 /* Always save the regs here, even if a transaction's not active. 948 * This context-switches a thread's TM info SPRs. We do it here to 949 * be consistent with the restore path (in recheckpoint) which 950 * cannot happen later in _switch(). 951 */ 952 tm_save_sprs(thr); 953 } 954 955 extern void __tm_recheckpoint(struct thread_struct *thread); 956 957 void tm_recheckpoint(struct thread_struct *thread) 958 { 959 unsigned long flags; 960 961 if (!(thread->regs->msr & MSR_TM)) 962 return; 963 964 /* We really can't be interrupted here as the TEXASR registers can't 965 * change and later in the trecheckpoint code, we have a userspace R1. 966 * So let's hard disable over this region. 967 */ 968 local_irq_save(flags); 969 hard_irq_disable(); 970 971 /* The TM SPRs are restored here, so that TEXASR.FS can be set 972 * before the trecheckpoint and no explosion occurs. 973 */ 974 tm_restore_sprs(thread); 975 976 __tm_recheckpoint(thread); 977 978 local_irq_restore(flags); 979 } 980 981 static inline void tm_recheckpoint_new_task(struct task_struct *new) 982 { 983 if (!cpu_has_feature(CPU_FTR_TM)) 984 return; 985 986 /* Recheckpoint the registers of the thread we're about to switch to. 987 * 988 * If the task was using FP, we non-lazily reload both the original and 989 * the speculative FP register states. This is because the kernel 990 * doesn't see if/when a TM rollback occurs, so if we take an FP 991 * unavailable later, we are unable to determine which set of FP regs 992 * need to be restored. 993 */ 994 if (!tm_enabled(new)) 995 return; 996 997 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 998 tm_restore_sprs(&new->thread); 999 return; 1000 } 1001 /* Recheckpoint to restore original checkpointed register state. */ 1002 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", 1003 new->pid, new->thread.regs->msr); 1004 1005 tm_recheckpoint(&new->thread); 1006 1007 /* 1008 * The checkpointed state has been restored but the live state has 1009 * not, ensure all the math functionality is turned off to trigger 1010 * restore_math() to reload. 1011 */ 1012 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); 1013 1014 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 1015 "(kernel msr 0x%lx)\n", 1016 new->pid, mfmsr()); 1017 } 1018 1019 static inline void __switch_to_tm(struct task_struct *prev, 1020 struct task_struct *new) 1021 { 1022 if (cpu_has_feature(CPU_FTR_TM)) { 1023 if (tm_enabled(prev) || tm_enabled(new)) 1024 tm_enable(); 1025 1026 if (tm_enabled(prev)) { 1027 prev->thread.load_tm++; 1028 tm_reclaim_task(prev); 1029 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) 1030 prev->thread.regs->msr &= ~MSR_TM; 1031 } 1032 1033 tm_recheckpoint_new_task(new); 1034 } 1035 } 1036 1037 /* 1038 * This is called if we are on the way out to userspace and the 1039 * TIF_RESTORE_TM flag is set. It checks if we need to reload 1040 * FP and/or vector state and does so if necessary. 1041 * If userspace is inside a transaction (whether active or 1042 * suspended) and FP/VMX/VSX instructions have ever been enabled 1043 * inside that transaction, then we have to keep them enabled 1044 * and keep the FP/VMX/VSX state loaded while ever the transaction 1045 * continues. The reason is that if we didn't, and subsequently 1046 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 1047 * we don't know whether it's the same transaction, and thus we 1048 * don't know which of the checkpointed state and the transactional 1049 * state to use. 1050 */ 1051 void restore_tm_state(struct pt_regs *regs) 1052 { 1053 unsigned long msr_diff; 1054 1055 /* 1056 * This is the only moment we should clear TIF_RESTORE_TM as 1057 * it is here that ckpt_regs.msr and pt_regs.msr become the same 1058 * again, anything else could lead to an incorrect ckpt_msr being 1059 * saved and therefore incorrect signal contexts. 1060 */ 1061 clear_thread_flag(TIF_RESTORE_TM); 1062 if (!MSR_TM_ACTIVE(regs->msr)) 1063 return; 1064 1065 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 1066 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 1067 1068 /* Ensure that restore_math() will restore */ 1069 if (msr_diff & MSR_FP) 1070 current->thread.load_fp = 1; 1071 #ifdef CONFIG_ALTIVEC 1072 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) 1073 current->thread.load_vec = 1; 1074 #endif 1075 restore_math(regs); 1076 1077 regs->msr |= msr_diff; 1078 } 1079 1080 #else 1081 #define tm_recheckpoint_new_task(new) 1082 #define __switch_to_tm(prev, new) 1083 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1084 1085 static inline void save_sprs(struct thread_struct *t) 1086 { 1087 #ifdef CONFIG_ALTIVEC 1088 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1089 t->vrsave = mfspr(SPRN_VRSAVE); 1090 #endif 1091 #ifdef CONFIG_PPC_BOOK3S_64 1092 if (cpu_has_feature(CPU_FTR_DSCR)) 1093 t->dscr = mfspr(SPRN_DSCR); 1094 1095 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1096 t->bescr = mfspr(SPRN_BESCR); 1097 t->ebbhr = mfspr(SPRN_EBBHR); 1098 t->ebbrr = mfspr(SPRN_EBBRR); 1099 1100 t->fscr = mfspr(SPRN_FSCR); 1101 1102 /* 1103 * Note that the TAR is not available for use in the kernel. 1104 * (To provide this, the TAR should be backed up/restored on 1105 * exception entry/exit instead, and be in pt_regs. FIXME, 1106 * this should be in pt_regs anyway (for debug).) 1107 */ 1108 t->tar = mfspr(SPRN_TAR); 1109 } 1110 #endif 1111 1112 thread_pkey_regs_save(t); 1113 } 1114 1115 static inline void restore_sprs(struct thread_struct *old_thread, 1116 struct thread_struct *new_thread) 1117 { 1118 #ifdef CONFIG_ALTIVEC 1119 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1120 old_thread->vrsave != new_thread->vrsave) 1121 mtspr(SPRN_VRSAVE, new_thread->vrsave); 1122 #endif 1123 #ifdef CONFIG_PPC_BOOK3S_64 1124 if (cpu_has_feature(CPU_FTR_DSCR)) { 1125 u64 dscr = get_paca()->dscr_default; 1126 if (new_thread->dscr_inherit) 1127 dscr = new_thread->dscr; 1128 1129 if (old_thread->dscr != dscr) 1130 mtspr(SPRN_DSCR, dscr); 1131 } 1132 1133 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1134 if (old_thread->bescr != new_thread->bescr) 1135 mtspr(SPRN_BESCR, new_thread->bescr); 1136 if (old_thread->ebbhr != new_thread->ebbhr) 1137 mtspr(SPRN_EBBHR, new_thread->ebbhr); 1138 if (old_thread->ebbrr != new_thread->ebbrr) 1139 mtspr(SPRN_EBBRR, new_thread->ebbrr); 1140 1141 if (old_thread->fscr != new_thread->fscr) 1142 mtspr(SPRN_FSCR, new_thread->fscr); 1143 1144 if (old_thread->tar != new_thread->tar) 1145 mtspr(SPRN_TAR, new_thread->tar); 1146 } 1147 1148 if (cpu_has_feature(CPU_FTR_P9_TIDR) && 1149 old_thread->tidr != new_thread->tidr) 1150 mtspr(SPRN_TIDR, new_thread->tidr); 1151 #endif 1152 1153 thread_pkey_regs_restore(new_thread, old_thread); 1154 } 1155 1156 struct task_struct *__switch_to(struct task_struct *prev, 1157 struct task_struct *new) 1158 { 1159 struct thread_struct *new_thread, *old_thread; 1160 struct task_struct *last; 1161 #ifdef CONFIG_PPC_BOOK3S_64 1162 struct ppc64_tlb_batch *batch; 1163 #endif 1164 1165 new_thread = &new->thread; 1166 old_thread = ¤t->thread; 1167 1168 WARN_ON(!irqs_disabled()); 1169 1170 #ifdef CONFIG_PPC_BOOK3S_64 1171 batch = this_cpu_ptr(&ppc64_tlb_batch); 1172 if (batch->active) { 1173 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1174 if (batch->index) 1175 __flush_tlb_pending(batch); 1176 batch->active = 0; 1177 } 1178 #endif /* CONFIG_PPC_BOOK3S_64 */ 1179 1180 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1181 switch_booke_debug_regs(&new->thread.debug); 1182 #else 1183 /* 1184 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1185 * schedule DABR 1186 */ 1187 #ifndef CONFIG_HAVE_HW_BREAKPOINT 1188 switch_hw_breakpoint(new); 1189 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1190 #endif 1191 1192 /* 1193 * We need to save SPRs before treclaim/trecheckpoint as these will 1194 * change a number of them. 1195 */ 1196 save_sprs(&prev->thread); 1197 1198 /* Save FPU, Altivec, VSX and SPE state */ 1199 giveup_all(prev); 1200 1201 __switch_to_tm(prev, new); 1202 1203 if (!radix_enabled()) { 1204 /* 1205 * We can't take a PMU exception inside _switch() since there 1206 * is a window where the kernel stack SLB and the kernel stack 1207 * are out of sync. Hard disable here. 1208 */ 1209 hard_irq_disable(); 1210 } 1211 1212 /* 1213 * Call restore_sprs() before calling _switch(). If we move it after 1214 * _switch() then we miss out on calling it for new tasks. The reason 1215 * for this is we manually create a stack frame for new tasks that 1216 * directly returns through ret_from_fork() or 1217 * ret_from_kernel_thread(). See copy_thread() for details. 1218 */ 1219 restore_sprs(old_thread, new_thread); 1220 1221 last = _switch(old_thread, new_thread); 1222 1223 #ifdef CONFIG_PPC_BOOK3S_64 1224 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1225 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 1226 batch = this_cpu_ptr(&ppc64_tlb_batch); 1227 batch->active = 1; 1228 } 1229 1230 if (current->thread.regs) { 1231 restore_math(current->thread.regs); 1232 1233 /* 1234 * The copy-paste buffer can only store into foreign real 1235 * addresses, so unprivileged processes can not see the 1236 * data or use it in any way unless they have foreign real 1237 * mappings. If the new process has the foreign real address 1238 * mappings, we must issue a cp_abort to clear any state and 1239 * prevent snooping, corruption or a covert channel. 1240 */ 1241 if (current->mm && 1242 atomic_read(¤t->mm->context.vas_windows)) 1243 asm volatile(PPC_CP_ABORT); 1244 } 1245 #endif /* CONFIG_PPC_BOOK3S_64 */ 1246 1247 return last; 1248 } 1249 1250 #define NR_INSN_TO_PRINT 16 1251 1252 static void show_instructions(struct pt_regs *regs) 1253 { 1254 int i; 1255 unsigned long nip = regs->nip; 1256 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 1257 1258 printk("Instruction dump:"); 1259 1260 /* 1261 * If we were executing with the MMU off for instructions, adjust pc 1262 * rather than printing XXXXXXXX. 1263 */ 1264 if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) { 1265 pc = (unsigned long)phys_to_virt(pc); 1266 nip = (unsigned long)phys_to_virt(regs->nip); 1267 } 1268 1269 for (i = 0; i < NR_INSN_TO_PRINT; i++) { 1270 int instr; 1271 1272 if (!(i % 8)) 1273 pr_cont("\n"); 1274 1275 if (!__kernel_text_address(pc) || 1276 get_kernel_nofault(instr, (const void *)pc)) { 1277 pr_cont("XXXXXXXX "); 1278 } else { 1279 if (nip == pc) 1280 pr_cont("<%08x> ", instr); 1281 else 1282 pr_cont("%08x ", instr); 1283 } 1284 1285 pc += sizeof(int); 1286 } 1287 1288 pr_cont("\n"); 1289 } 1290 1291 void show_user_instructions(struct pt_regs *regs) 1292 { 1293 unsigned long pc; 1294 int n = NR_INSN_TO_PRINT; 1295 struct seq_buf s; 1296 char buf[96]; /* enough for 8 times 9 + 2 chars */ 1297 1298 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); 1299 1300 seq_buf_init(&s, buf, sizeof(buf)); 1301 1302 while (n) { 1303 int i; 1304 1305 seq_buf_clear(&s); 1306 1307 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) { 1308 int instr; 1309 1310 if (copy_from_user_nofault(&instr, (void __user *)pc, 1311 sizeof(instr))) { 1312 seq_buf_printf(&s, "XXXXXXXX "); 1313 continue; 1314 } 1315 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr); 1316 } 1317 1318 if (!seq_buf_has_overflowed(&s)) 1319 pr_info("%s[%d]: code: %s\n", current->comm, 1320 current->pid, s.buffer); 1321 } 1322 } 1323 1324 struct regbit { 1325 unsigned long bit; 1326 const char *name; 1327 }; 1328 1329 static struct regbit msr_bits[] = { 1330 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 1331 {MSR_SF, "SF"}, 1332 {MSR_HV, "HV"}, 1333 #endif 1334 {MSR_VEC, "VEC"}, 1335 {MSR_VSX, "VSX"}, 1336 #ifdef CONFIG_BOOKE 1337 {MSR_CE, "CE"}, 1338 #endif 1339 {MSR_EE, "EE"}, 1340 {MSR_PR, "PR"}, 1341 {MSR_FP, "FP"}, 1342 {MSR_ME, "ME"}, 1343 #ifdef CONFIG_BOOKE 1344 {MSR_DE, "DE"}, 1345 #else 1346 {MSR_SE, "SE"}, 1347 {MSR_BE, "BE"}, 1348 #endif 1349 {MSR_IR, "IR"}, 1350 {MSR_DR, "DR"}, 1351 {MSR_PMM, "PMM"}, 1352 #ifndef CONFIG_BOOKE 1353 {MSR_RI, "RI"}, 1354 {MSR_LE, "LE"}, 1355 #endif 1356 {0, NULL} 1357 }; 1358 1359 static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 1360 { 1361 const char *s = ""; 1362 1363 for (; bits->bit; ++bits) 1364 if (val & bits->bit) { 1365 pr_cont("%s%s", s, bits->name); 1366 s = sep; 1367 } 1368 } 1369 1370 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1371 static struct regbit msr_tm_bits[] = { 1372 {MSR_TS_T, "T"}, 1373 {MSR_TS_S, "S"}, 1374 {MSR_TM, "E"}, 1375 {0, NULL} 1376 }; 1377 1378 static void print_tm_bits(unsigned long val) 1379 { 1380 /* 1381 * This only prints something if at least one of the TM bit is set. 1382 * Inside the TM[], the output means: 1383 * E: Enabled (bit 32) 1384 * S: Suspended (bit 33) 1385 * T: Transactional (bit 34) 1386 */ 1387 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1388 pr_cont(",TM["); 1389 print_bits(val, msr_tm_bits, ""); 1390 pr_cont("]"); 1391 } 1392 } 1393 #else 1394 static void print_tm_bits(unsigned long val) {} 1395 #endif 1396 1397 static void print_msr_bits(unsigned long val) 1398 { 1399 pr_cont("<"); 1400 print_bits(val, msr_bits, ","); 1401 print_tm_bits(val); 1402 pr_cont(">"); 1403 } 1404 1405 #ifdef CONFIG_PPC64 1406 #define REG "%016lx" 1407 #define REGS_PER_LINE 4 1408 #define LAST_VOLATILE 13 1409 #else 1410 #define REG "%08lx" 1411 #define REGS_PER_LINE 8 1412 #define LAST_VOLATILE 12 1413 #endif 1414 1415 void show_regs(struct pt_regs * regs) 1416 { 1417 int i, trap; 1418 1419 show_regs_print_info(KERN_DEFAULT); 1420 1421 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 1422 regs->nip, regs->link, regs->ctr); 1423 printk("REGS: %px TRAP: %04lx %s (%s)\n", 1424 regs, regs->trap, print_tainted(), init_utsname()->release); 1425 printk("MSR: "REG" ", regs->msr); 1426 print_msr_bits(regs->msr); 1427 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1428 trap = TRAP(regs); 1429 if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR)) 1430 pr_cont("CFAR: "REG" ", regs->orig_gpr3); 1431 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1432 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1433 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1434 #else 1435 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1436 #endif 1437 #ifdef CONFIG_PPC64 1438 pr_cont("IRQMASK: %lx ", regs->softe); 1439 #endif 1440 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1441 if (MSR_TM_ACTIVE(regs->msr)) 1442 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1443 #endif 1444 1445 for (i = 0; i < 32; i++) { 1446 if ((i % REGS_PER_LINE) == 0) 1447 pr_cont("\nGPR%02d: ", i); 1448 pr_cont(REG " ", regs->gpr[i]); 1449 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1450 break; 1451 } 1452 pr_cont("\n"); 1453 #ifdef CONFIG_KALLSYMS 1454 /* 1455 * Lookup NIP late so we have the best change of getting the 1456 * above info out without failing 1457 */ 1458 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1459 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1460 #endif 1461 show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT); 1462 if (!user_mode(regs)) 1463 show_instructions(regs); 1464 } 1465 1466 void flush_thread(void) 1467 { 1468 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1469 flush_ptrace_hw_breakpoint(current); 1470 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1471 set_debug_reg_defaults(¤t->thread); 1472 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1473 } 1474 1475 #ifdef CONFIG_PPC_BOOK3S_64 1476 void arch_setup_new_exec(void) 1477 { 1478 if (radix_enabled()) 1479 return; 1480 hash__setup_new_exec(); 1481 } 1482 #endif 1483 1484 #ifdef CONFIG_PPC64 1485 /** 1486 * Assign a TIDR (thread ID) for task @t and set it in the thread 1487 * structure. For now, we only support setting TIDR for 'current' task. 1488 * 1489 * Since the TID value is a truncated form of it PID, it is possible 1490 * (but unlikely) for 2 threads to have the same TID. In the unlikely event 1491 * that 2 threads share the same TID and are waiting, one of the following 1492 * cases will happen: 1493 * 1494 * 1. The correct thread is running, the wrong thread is not 1495 * In this situation, the correct thread is woken and proceeds to pass it's 1496 * condition check. 1497 * 1498 * 2. Neither threads are running 1499 * In this situation, neither thread will be woken. When scheduled, the waiting 1500 * threads will execute either a wait, which will return immediately, followed 1501 * by a condition check, which will pass for the correct thread and fail 1502 * for the wrong thread, or they will execute the condition check immediately. 1503 * 1504 * 3. The wrong thread is running, the correct thread is not 1505 * The wrong thread will be woken, but will fail it's condition check and 1506 * re-execute wait. The correct thread, when scheduled, will execute either 1507 * it's condition check (which will pass), or wait, which returns immediately 1508 * when called the first time after the thread is scheduled, followed by it's 1509 * condition check (which will pass). 1510 * 1511 * 4. Both threads are running 1512 * Both threads will be woken. The wrong thread will fail it's condition check 1513 * and execute another wait, while the correct thread will pass it's condition 1514 * check. 1515 * 1516 * @t: the task to set the thread ID for 1517 */ 1518 int set_thread_tidr(struct task_struct *t) 1519 { 1520 if (!cpu_has_feature(CPU_FTR_P9_TIDR)) 1521 return -EINVAL; 1522 1523 if (t != current) 1524 return -EINVAL; 1525 1526 if (t->thread.tidr) 1527 return 0; 1528 1529 t->thread.tidr = (u16)task_pid_nr(t); 1530 mtspr(SPRN_TIDR, t->thread.tidr); 1531 1532 return 0; 1533 } 1534 EXPORT_SYMBOL_GPL(set_thread_tidr); 1535 1536 #endif /* CONFIG_PPC64 */ 1537 1538 void 1539 release_thread(struct task_struct *t) 1540 { 1541 } 1542 1543 /* 1544 * this gets called so that we can store coprocessor state into memory and 1545 * copy the current task into the new thread. 1546 */ 1547 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1548 { 1549 flush_all_to_thread(src); 1550 /* 1551 * Flush TM state out so we can copy it. __switch_to_tm() does this 1552 * flush but it removes the checkpointed state from the current CPU and 1553 * transitions the CPU out of TM mode. Hence we need to call 1554 * tm_recheckpoint_new_task() (on the same task) to restore the 1555 * checkpointed state back and the TM mode. 1556 * 1557 * Can't pass dst because it isn't ready. Doesn't matter, passing 1558 * dst is only important for __switch_to() 1559 */ 1560 __switch_to_tm(src, src); 1561 1562 *dst = *src; 1563 1564 clear_task_ebb(dst); 1565 1566 return 0; 1567 } 1568 1569 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1570 { 1571 #ifdef CONFIG_PPC_BOOK3S_64 1572 unsigned long sp_vsid; 1573 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1574 1575 if (radix_enabled()) 1576 return; 1577 1578 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1579 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1580 << SLB_VSID_SHIFT_1T; 1581 else 1582 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1583 << SLB_VSID_SHIFT; 1584 sp_vsid |= SLB_VSID_KERNEL | llp; 1585 p->thread.ksp_vsid = sp_vsid; 1586 #endif 1587 } 1588 1589 /* 1590 * Copy a thread.. 1591 */ 1592 1593 /* 1594 * Copy architecture-specific thread state 1595 */ 1596 int copy_thread_tls(unsigned long clone_flags, unsigned long usp, 1597 unsigned long kthread_arg, struct task_struct *p, 1598 unsigned long tls) 1599 { 1600 struct pt_regs *childregs, *kregs; 1601 extern void ret_from_fork(void); 1602 extern void ret_from_kernel_thread(void); 1603 void (*f)(void); 1604 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1605 struct thread_info *ti = task_thread_info(p); 1606 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1607 int i; 1608 #endif 1609 1610 klp_init_thread_info(p); 1611 1612 /* Copy registers */ 1613 sp -= sizeof(struct pt_regs); 1614 childregs = (struct pt_regs *) sp; 1615 if (unlikely(p->flags & PF_KTHREAD)) { 1616 /* kernel thread */ 1617 memset(childregs, 0, sizeof(struct pt_regs)); 1618 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1619 /* function */ 1620 if (usp) 1621 childregs->gpr[14] = ppc_function_entry((void *)usp); 1622 #ifdef CONFIG_PPC64 1623 clear_tsk_thread_flag(p, TIF_32BIT); 1624 childregs->softe = IRQS_ENABLED; 1625 #endif 1626 childregs->gpr[15] = kthread_arg; 1627 p->thread.regs = NULL; /* no user register state */ 1628 ti->flags |= _TIF_RESTOREALL; 1629 f = ret_from_kernel_thread; 1630 } else { 1631 /* user thread */ 1632 struct pt_regs *regs = current_pt_regs(); 1633 CHECK_FULL_REGS(regs); 1634 *childregs = *regs; 1635 if (usp) 1636 childregs->gpr[1] = usp; 1637 p->thread.regs = childregs; 1638 childregs->gpr[3] = 0; /* Result from fork() */ 1639 if (clone_flags & CLONE_SETTLS) { 1640 if (!is_32bit_task()) 1641 childregs->gpr[13] = tls; 1642 else 1643 childregs->gpr[2] = tls; 1644 } 1645 1646 f = ret_from_fork; 1647 } 1648 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 1649 sp -= STACK_FRAME_OVERHEAD; 1650 1651 /* 1652 * The way this works is that at some point in the future 1653 * some task will call _switch to switch to the new task. 1654 * That will pop off the stack frame created below and start 1655 * the new task running at ret_from_fork. The new task will 1656 * do some house keeping and then return from the fork or clone 1657 * system call, using the stack frame created above. 1658 */ 1659 ((unsigned long *)sp)[0] = 0; 1660 sp -= sizeof(struct pt_regs); 1661 kregs = (struct pt_regs *) sp; 1662 sp -= STACK_FRAME_OVERHEAD; 1663 p->thread.ksp = sp; 1664 #ifdef CONFIG_PPC32 1665 p->thread.ksp_limit = (unsigned long)end_of_stack(p); 1666 #endif 1667 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1668 for (i = 0; i < nr_wp_slots(); i++) 1669 p->thread.ptrace_bps[i] = NULL; 1670 #endif 1671 1672 p->thread.fp_save_area = NULL; 1673 #ifdef CONFIG_ALTIVEC 1674 p->thread.vr_save_area = NULL; 1675 #endif 1676 1677 setup_ksp_vsid(p, sp); 1678 1679 #ifdef CONFIG_PPC64 1680 if (cpu_has_feature(CPU_FTR_DSCR)) { 1681 p->thread.dscr_inherit = current->thread.dscr_inherit; 1682 p->thread.dscr = mfspr(SPRN_DSCR); 1683 } 1684 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1685 childregs->ppr = DEFAULT_PPR; 1686 1687 p->thread.tidr = 0; 1688 #endif 1689 kregs->nip = ppc_function_entry(f); 1690 return 0; 1691 } 1692 1693 void preload_new_slb_context(unsigned long start, unsigned long sp); 1694 1695 /* 1696 * Set up a thread for executing a new program 1697 */ 1698 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1699 { 1700 #ifdef CONFIG_PPC64 1701 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1702 1703 #ifdef CONFIG_PPC_BOOK3S_64 1704 if (!radix_enabled()) 1705 preload_new_slb_context(start, sp); 1706 #endif 1707 #endif 1708 1709 /* 1710 * If we exec out of a kernel thread then thread.regs will not be 1711 * set. Do it now. 1712 */ 1713 if (!current->thread.regs) { 1714 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1715 current->thread.regs = regs - 1; 1716 } 1717 1718 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1719 /* 1720 * Clear any transactional state, we're exec()ing. The cause is 1721 * not important as there will never be a recheckpoint so it's not 1722 * user visible. 1723 */ 1724 if (MSR_TM_SUSPENDED(mfmsr())) 1725 tm_reclaim_current(0); 1726 #endif 1727 1728 memset(regs->gpr, 0, sizeof(regs->gpr)); 1729 regs->ctr = 0; 1730 regs->link = 0; 1731 regs->xer = 0; 1732 regs->ccr = 0; 1733 regs->gpr[1] = sp; 1734 1735 /* 1736 * We have just cleared all the nonvolatile GPRs, so make 1737 * FULL_REGS(regs) return true. This is necessary to allow 1738 * ptrace to examine the thread immediately after exec. 1739 */ 1740 SET_FULL_REGS(regs); 1741 1742 #ifdef CONFIG_PPC32 1743 regs->mq = 0; 1744 regs->nip = start; 1745 regs->msr = MSR_USER; 1746 #else 1747 if (!is_32bit_task()) { 1748 unsigned long entry; 1749 1750 if (is_elf2_task()) { 1751 /* Look ma, no function descriptors! */ 1752 entry = start; 1753 1754 /* 1755 * Ulrich says: 1756 * The latest iteration of the ABI requires that when 1757 * calling a function (at its global entry point), 1758 * the caller must ensure r12 holds the entry point 1759 * address (so that the function can quickly 1760 * establish addressability). 1761 */ 1762 regs->gpr[12] = start; 1763 /* Make sure that's restored on entry to userspace. */ 1764 set_thread_flag(TIF_RESTOREALL); 1765 } else { 1766 unsigned long toc; 1767 1768 /* start is a relocated pointer to the function 1769 * descriptor for the elf _start routine. The first 1770 * entry in the function descriptor is the entry 1771 * address of _start and the second entry is the TOC 1772 * value we need to use. 1773 */ 1774 __get_user(entry, (unsigned long __user *)start); 1775 __get_user(toc, (unsigned long __user *)start+1); 1776 1777 /* Check whether the e_entry function descriptor entries 1778 * need to be relocated before we can use them. 1779 */ 1780 if (load_addr != 0) { 1781 entry += load_addr; 1782 toc += load_addr; 1783 } 1784 regs->gpr[2] = toc; 1785 } 1786 regs->nip = entry; 1787 regs->msr = MSR_USER64; 1788 } else { 1789 regs->nip = start; 1790 regs->gpr[2] = 0; 1791 regs->msr = MSR_USER32; 1792 } 1793 #endif 1794 #ifdef CONFIG_VSX 1795 current->thread.used_vsr = 0; 1796 #endif 1797 current->thread.load_slb = 0; 1798 current->thread.load_fp = 0; 1799 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1800 current->thread.fp_save_area = NULL; 1801 #ifdef CONFIG_ALTIVEC 1802 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1803 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1804 current->thread.vr_save_area = NULL; 1805 current->thread.vrsave = 0; 1806 current->thread.used_vr = 0; 1807 current->thread.load_vec = 0; 1808 #endif /* CONFIG_ALTIVEC */ 1809 #ifdef CONFIG_SPE 1810 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1811 current->thread.acc = 0; 1812 current->thread.spefscr = 0; 1813 current->thread.used_spe = 0; 1814 #endif /* CONFIG_SPE */ 1815 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1816 current->thread.tm_tfhar = 0; 1817 current->thread.tm_texasr = 0; 1818 current->thread.tm_tfiar = 0; 1819 current->thread.load_tm = 0; 1820 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1821 1822 thread_pkey_regs_init(¤t->thread); 1823 } 1824 EXPORT_SYMBOL(start_thread); 1825 1826 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1827 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1828 1829 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1830 { 1831 struct pt_regs *regs = tsk->thread.regs; 1832 1833 /* This is a bit hairy. If we are an SPE enabled processor 1834 * (have embedded fp) we store the IEEE exception enable flags in 1835 * fpexc_mode. fpexc_mode is also used for setting FP exception 1836 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1837 if (val & PR_FP_EXC_SW_ENABLE) { 1838 #ifdef CONFIG_SPE 1839 if (cpu_has_feature(CPU_FTR_SPE)) { 1840 /* 1841 * When the sticky exception bits are set 1842 * directly by userspace, it must call prctl 1843 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1844 * in the existing prctl settings) or 1845 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1846 * the bits being set). <fenv.h> functions 1847 * saving and restoring the whole 1848 * floating-point environment need to do so 1849 * anyway to restore the prctl settings from 1850 * the saved environment. 1851 */ 1852 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1853 tsk->thread.fpexc_mode = val & 1854 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1855 return 0; 1856 } else { 1857 return -EINVAL; 1858 } 1859 #else 1860 return -EINVAL; 1861 #endif 1862 } 1863 1864 /* on a CONFIG_SPE this does not hurt us. The bits that 1865 * __pack_fe01 use do not overlap with bits used for 1866 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1867 * on CONFIG_SPE implementations are reserved so writing to 1868 * them does not change anything */ 1869 if (val > PR_FP_EXC_PRECISE) 1870 return -EINVAL; 1871 tsk->thread.fpexc_mode = __pack_fe01(val); 1872 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1873 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1874 | tsk->thread.fpexc_mode; 1875 return 0; 1876 } 1877 1878 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1879 { 1880 unsigned int val; 1881 1882 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1883 #ifdef CONFIG_SPE 1884 if (cpu_has_feature(CPU_FTR_SPE)) { 1885 /* 1886 * When the sticky exception bits are set 1887 * directly by userspace, it must call prctl 1888 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1889 * in the existing prctl settings) or 1890 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1891 * the bits being set). <fenv.h> functions 1892 * saving and restoring the whole 1893 * floating-point environment need to do so 1894 * anyway to restore the prctl settings from 1895 * the saved environment. 1896 */ 1897 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1898 val = tsk->thread.fpexc_mode; 1899 } else 1900 return -EINVAL; 1901 #else 1902 return -EINVAL; 1903 #endif 1904 else 1905 val = __unpack_fe01(tsk->thread.fpexc_mode); 1906 return put_user(val, (unsigned int __user *) adr); 1907 } 1908 1909 int set_endian(struct task_struct *tsk, unsigned int val) 1910 { 1911 struct pt_regs *regs = tsk->thread.regs; 1912 1913 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1914 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1915 return -EINVAL; 1916 1917 if (regs == NULL) 1918 return -EINVAL; 1919 1920 if (val == PR_ENDIAN_BIG) 1921 regs->msr &= ~MSR_LE; 1922 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1923 regs->msr |= MSR_LE; 1924 else 1925 return -EINVAL; 1926 1927 return 0; 1928 } 1929 1930 int get_endian(struct task_struct *tsk, unsigned long adr) 1931 { 1932 struct pt_regs *regs = tsk->thread.regs; 1933 unsigned int val; 1934 1935 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1936 !cpu_has_feature(CPU_FTR_REAL_LE)) 1937 return -EINVAL; 1938 1939 if (regs == NULL) 1940 return -EINVAL; 1941 1942 if (regs->msr & MSR_LE) { 1943 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1944 val = PR_ENDIAN_LITTLE; 1945 else 1946 val = PR_ENDIAN_PPC_LITTLE; 1947 } else 1948 val = PR_ENDIAN_BIG; 1949 1950 return put_user(val, (unsigned int __user *)adr); 1951 } 1952 1953 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1954 { 1955 tsk->thread.align_ctl = val; 1956 return 0; 1957 } 1958 1959 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1960 { 1961 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1962 } 1963 1964 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1965 unsigned long nbytes) 1966 { 1967 unsigned long stack_page; 1968 unsigned long cpu = task_cpu(p); 1969 1970 stack_page = (unsigned long)hardirq_ctx[cpu]; 1971 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1972 return 1; 1973 1974 stack_page = (unsigned long)softirq_ctx[cpu]; 1975 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1976 return 1; 1977 1978 return 0; 1979 } 1980 1981 static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p, 1982 unsigned long nbytes) 1983 { 1984 #ifdef CONFIG_PPC64 1985 unsigned long stack_page; 1986 unsigned long cpu = task_cpu(p); 1987 1988 stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE; 1989 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1990 return 1; 1991 1992 # ifdef CONFIG_PPC_BOOK3S_64 1993 stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE; 1994 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1995 return 1; 1996 1997 stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE; 1998 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 1999 return 1; 2000 # endif 2001 #endif 2002 2003 return 0; 2004 } 2005 2006 2007 int validate_sp(unsigned long sp, struct task_struct *p, 2008 unsigned long nbytes) 2009 { 2010 unsigned long stack_page = (unsigned long)task_stack_page(p); 2011 2012 if (sp < THREAD_SIZE) 2013 return 0; 2014 2015 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) 2016 return 1; 2017 2018 if (valid_irq_stack(sp, p, nbytes)) 2019 return 1; 2020 2021 return valid_emergency_stack(sp, p, nbytes); 2022 } 2023 2024 EXPORT_SYMBOL(validate_sp); 2025 2026 static unsigned long __get_wchan(struct task_struct *p) 2027 { 2028 unsigned long ip, sp; 2029 int count = 0; 2030 2031 if (!p || p == current || p->state == TASK_RUNNING) 2032 return 0; 2033 2034 sp = p->thread.ksp; 2035 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 2036 return 0; 2037 2038 do { 2039 sp = *(unsigned long *)sp; 2040 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || 2041 p->state == TASK_RUNNING) 2042 return 0; 2043 if (count > 0) { 2044 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 2045 if (!in_sched_functions(ip)) 2046 return ip; 2047 } 2048 } while (count++ < 16); 2049 return 0; 2050 } 2051 2052 unsigned long get_wchan(struct task_struct *p) 2053 { 2054 unsigned long ret; 2055 2056 if (!try_get_task_stack(p)) 2057 return 0; 2058 2059 ret = __get_wchan(p); 2060 2061 put_task_stack(p); 2062 2063 return ret; 2064 } 2065 2066 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 2067 2068 void show_stack(struct task_struct *tsk, unsigned long *stack, 2069 const char *loglvl) 2070 { 2071 unsigned long sp, ip, lr, newsp; 2072 int count = 0; 2073 int firstframe = 1; 2074 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 2075 unsigned long ret_addr; 2076 int ftrace_idx = 0; 2077 #endif 2078 2079 if (tsk == NULL) 2080 tsk = current; 2081 2082 if (!try_get_task_stack(tsk)) 2083 return; 2084 2085 sp = (unsigned long) stack; 2086 if (sp == 0) { 2087 if (tsk == current) 2088 sp = current_stack_frame(); 2089 else 2090 sp = tsk->thread.ksp; 2091 } 2092 2093 lr = 0; 2094 printk("%sCall Trace:\n", loglvl); 2095 do { 2096 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 2097 break; 2098 2099 stack = (unsigned long *) sp; 2100 newsp = stack[0]; 2101 ip = stack[STACK_FRAME_LR_SAVE]; 2102 if (!firstframe || ip != lr) { 2103 printk("%s["REG"] ["REG"] %pS", 2104 loglvl, sp, ip, (void *)ip); 2105 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 2106 ret_addr = ftrace_graph_ret_addr(current, 2107 &ftrace_idx, ip, stack); 2108 if (ret_addr != ip) 2109 pr_cont(" (%pS)", (void *)ret_addr); 2110 #endif 2111 if (firstframe) 2112 pr_cont(" (unreliable)"); 2113 pr_cont("\n"); 2114 } 2115 firstframe = 0; 2116 2117 /* 2118 * See if this is an exception frame. 2119 * We look for the "regshere" marker in the current frame. 2120 */ 2121 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 2122 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 2123 struct pt_regs *regs = (struct pt_regs *) 2124 (sp + STACK_FRAME_OVERHEAD); 2125 lr = regs->link; 2126 printk("%s--- interrupt: %lx at %pS\n LR = %pS\n", 2127 loglvl, regs->trap, 2128 (void *)regs->nip, (void *)lr); 2129 firstframe = 1; 2130 } 2131 2132 sp = newsp; 2133 } while (count++ < kstack_depth_to_print); 2134 2135 put_task_stack(tsk); 2136 } 2137 2138 #ifdef CONFIG_PPC64 2139 /* Called with hard IRQs off */ 2140 void notrace __ppc64_runlatch_on(void) 2141 { 2142 struct thread_info *ti = current_thread_info(); 2143 2144 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2145 /* 2146 * Least significant bit (RUN) is the only writable bit of 2147 * the CTRL register, so we can avoid mfspr. 2.06 is not the 2148 * earliest ISA where this is the case, but it's convenient. 2149 */ 2150 mtspr(SPRN_CTRLT, CTRL_RUNLATCH); 2151 } else { 2152 unsigned long ctrl; 2153 2154 /* 2155 * Some architectures (e.g., Cell) have writable fields other 2156 * than RUN, so do the read-modify-write. 2157 */ 2158 ctrl = mfspr(SPRN_CTRLF); 2159 ctrl |= CTRL_RUNLATCH; 2160 mtspr(SPRN_CTRLT, ctrl); 2161 } 2162 2163 ti->local_flags |= _TLF_RUNLATCH; 2164 } 2165 2166 /* Called with hard IRQs off */ 2167 void notrace __ppc64_runlatch_off(void) 2168 { 2169 struct thread_info *ti = current_thread_info(); 2170 2171 ti->local_flags &= ~_TLF_RUNLATCH; 2172 2173 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 2174 mtspr(SPRN_CTRLT, 0); 2175 } else { 2176 unsigned long ctrl; 2177 2178 ctrl = mfspr(SPRN_CTRLF); 2179 ctrl &= ~CTRL_RUNLATCH; 2180 mtspr(SPRN_CTRLT, ctrl); 2181 } 2182 } 2183 #endif /* CONFIG_PPC64 */ 2184 2185 unsigned long arch_align_stack(unsigned long sp) 2186 { 2187 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 2188 sp -= get_random_int() & ~PAGE_MASK; 2189 return sp & ~0xf; 2190 } 2191 2192 static inline unsigned long brk_rnd(void) 2193 { 2194 unsigned long rnd = 0; 2195 2196 /* 8MB for 32bit, 1GB for 64bit */ 2197 if (is_32bit_task()) 2198 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 2199 else 2200 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 2201 2202 return rnd << PAGE_SHIFT; 2203 } 2204 2205 unsigned long arch_randomize_brk(struct mm_struct *mm) 2206 { 2207 unsigned long base = mm->brk; 2208 unsigned long ret; 2209 2210 #ifdef CONFIG_PPC_BOOK3S_64 2211 /* 2212 * If we are using 1TB segments and we are allowed to randomise 2213 * the heap, we can put it above 1TB so it is backed by a 1TB 2214 * segment. Otherwise the heap will be in the bottom 1TB 2215 * which always uses 256MB segments and this may result in a 2216 * performance penalty. We don't need to worry about radix. For 2217 * radix, mmu_highuser_ssize remains unchanged from 256MB. 2218 */ 2219 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 2220 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 2221 #endif 2222 2223 ret = PAGE_ALIGN(base + brk_rnd()); 2224 2225 if (ret < mm->brk) 2226 return mm->brk; 2227 2228 return ret; 2229 } 2230 2231