1 /* 2 * Port for PPC64 David Engebretsen, IBM Corp. 3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 4 * 5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 6 * Rework, based on alpha PCI code. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #undef DEBUG 15 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 #include <linux/bootmem.h> 21 #include <linux/mm.h> 22 #include <linux/list.h> 23 #include <linux/syscalls.h> 24 #include <linux/irq.h> 25 #include <linux/vmalloc.h> 26 27 #include <asm/processor.h> 28 #include <asm/io.h> 29 #include <asm/prom.h> 30 #include <asm/pci-bridge.h> 31 #include <asm/byteorder.h> 32 #include <asm/machdep.h> 33 #include <asm/ppc-pci.h> 34 35 unsigned long pci_probe_only = 1; 36 37 /* pci_io_base -- the base address from which io bars are offsets. 38 * This is the lowest I/O base address (so bar values are always positive), 39 * and it *must* be the start of ISA space if an ISA bus exists because 40 * ISA drivers use hard coded offsets. If no ISA bus exists nothing 41 * is mapped on the first 64K of IO space 42 */ 43 unsigned long pci_io_base = ISA_IO_BASE; 44 EXPORT_SYMBOL(pci_io_base); 45 46 static void fixup_broken_pcnet32(struct pci_dev* dev) 47 { 48 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { 49 dev->vendor = PCI_VENDOR_ID_AMD; 50 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); 51 } 52 } 53 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); 54 55 56 static u32 get_int_prop(struct device_node *np, const char *name, u32 def) 57 { 58 const u32 *prop; 59 int len; 60 61 prop = of_get_property(np, name, &len); 62 if (prop && len >= 4) 63 return *prop; 64 return def; 65 } 66 67 static unsigned int pci_parse_of_flags(u32 addr0) 68 { 69 unsigned int flags = 0; 70 71 if (addr0 & 0x02000000) { 72 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 73 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; 74 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 75 if (addr0 & 0x40000000) 76 flags |= IORESOURCE_PREFETCH 77 | PCI_BASE_ADDRESS_MEM_PREFETCH; 78 } else if (addr0 & 0x01000000) 79 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 80 return flags; 81 } 82 83 84 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev) 85 { 86 u64 base, size; 87 unsigned int flags; 88 struct resource *res; 89 const u32 *addrs; 90 u32 i; 91 int proplen; 92 93 addrs = of_get_property(node, "assigned-addresses", &proplen); 94 if (!addrs) 95 return; 96 pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs); 97 for (; proplen >= 20; proplen -= 20, addrs += 5) { 98 flags = pci_parse_of_flags(addrs[0]); 99 if (!flags) 100 continue; 101 base = of_read_number(&addrs[1], 2); 102 size = of_read_number(&addrs[3], 2); 103 if (!size) 104 continue; 105 i = addrs[0] & 0xff; 106 pr_debug(" base: %llx, size: %llx, i: %x\n", 107 (unsigned long long)base, 108 (unsigned long long)size, i); 109 110 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 111 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 112 } else if (i == dev->rom_base_reg) { 113 res = &dev->resource[PCI_ROM_RESOURCE]; 114 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; 115 } else { 116 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); 117 continue; 118 } 119 res->start = base; 120 res->end = base + size - 1; 121 res->flags = flags; 122 res->name = pci_name(dev); 123 } 124 } 125 126 struct pci_dev *of_create_pci_dev(struct device_node *node, 127 struct pci_bus *bus, int devfn) 128 { 129 struct pci_dev *dev; 130 const char *type; 131 132 dev = alloc_pci_dev(); 133 if (!dev) 134 return NULL; 135 type = of_get_property(node, "device_type", NULL); 136 if (type == NULL) 137 type = ""; 138 139 pr_debug(" create device, devfn: %x, type: %s\n", devfn, type); 140 141 dev->bus = bus; 142 dev->sysdata = node; 143 dev->dev.parent = bus->bridge; 144 dev->dev.bus = &pci_bus_type; 145 dev->devfn = devfn; 146 dev->multifunction = 0; /* maybe a lie? */ 147 148 dev->vendor = get_int_prop(node, "vendor-id", 0xffff); 149 dev->device = get_int_prop(node, "device-id", 0xffff); 150 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); 151 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); 152 153 dev->cfg_size = pci_cfg_space_size(dev); 154 155 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), 156 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 157 dev->class = get_int_prop(node, "class-code", 0); 158 dev->revision = get_int_prop(node, "revision-id", 0); 159 160 pr_debug(" class: 0x%x\n", dev->class); 161 pr_debug(" revision: 0x%x\n", dev->revision); 162 163 dev->current_state = 4; /* unknown power state */ 164 dev->error_state = pci_channel_io_normal; 165 dev->dma_mask = 0xffffffff; 166 167 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { 168 /* a PCI-PCI bridge */ 169 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 170 dev->rom_base_reg = PCI_ROM_ADDRESS1; 171 } else if (!strcmp(type, "cardbus")) { 172 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 173 } else { 174 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 175 dev->rom_base_reg = PCI_ROM_ADDRESS; 176 /* Maybe do a default OF mapping here */ 177 dev->irq = NO_IRQ; 178 } 179 180 pci_parse_of_addrs(node, dev); 181 182 pr_debug(" adding to system ...\n"); 183 184 pci_device_add(dev, bus); 185 186 return dev; 187 } 188 EXPORT_SYMBOL(of_create_pci_dev); 189 190 static void __devinit __of_scan_bus(struct device_node *node, 191 struct pci_bus *bus, int rescan_existing) 192 { 193 struct device_node *child; 194 const u32 *reg; 195 int reglen, devfn; 196 struct pci_dev *dev; 197 198 pr_debug("of_scan_bus(%s) bus no %d... \n", 199 node->full_name, bus->number); 200 201 /* Scan direct children */ 202 for_each_child_of_node(node, child) { 203 pr_debug(" * %s\n", child->full_name); 204 reg = of_get_property(child, "reg", ®len); 205 if (reg == NULL || reglen < 20) 206 continue; 207 devfn = (reg[0] >> 8) & 0xff; 208 209 /* create a new pci_dev for this device */ 210 dev = of_create_pci_dev(child, bus, devfn); 211 if (!dev) 212 continue; 213 pr_debug(" dev header type: %x\n", dev->hdr_type); 214 } 215 216 /* Apply all fixups necessary. We don't fixup the bus "self" 217 * for an existing bridge that is being rescanned 218 */ 219 if (!rescan_existing) 220 pcibios_setup_bus_self(bus); 221 pcibios_setup_bus_devices(bus); 222 223 /* Now scan child busses */ 224 list_for_each_entry(dev, &bus->devices, bus_list) { 225 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 226 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) { 227 struct device_node *child = pci_device_to_OF_node(dev); 228 if (dev) 229 of_scan_pci_bridge(child, dev); 230 } 231 } 232 } 233 234 void __devinit of_scan_bus(struct device_node *node, 235 struct pci_bus *bus) 236 { 237 __of_scan_bus(node, bus, 0); 238 } 239 EXPORT_SYMBOL_GPL(of_scan_bus); 240 241 void __devinit of_rescan_bus(struct device_node *node, 242 struct pci_bus *bus) 243 { 244 __of_scan_bus(node, bus, 1); 245 } 246 EXPORT_SYMBOL_GPL(of_rescan_bus); 247 248 void __devinit of_scan_pci_bridge(struct device_node *node, 249 struct pci_dev *dev) 250 { 251 struct pci_bus *bus; 252 const u32 *busrange, *ranges; 253 int len, i, mode; 254 struct resource *res; 255 unsigned int flags; 256 u64 size; 257 258 pr_debug("of_scan_pci_bridge(%s)\n", node->full_name); 259 260 /* parse bus-range property */ 261 busrange = of_get_property(node, "bus-range", &len); 262 if (busrange == NULL || len != 8) { 263 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", 264 node->full_name); 265 return; 266 } 267 ranges = of_get_property(node, "ranges", &len); 268 if (ranges == NULL) { 269 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", 270 node->full_name); 271 return; 272 } 273 274 bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 275 if (!bus) { 276 printk(KERN_ERR "Failed to create pci bus for %s\n", 277 node->full_name); 278 return; 279 } 280 281 bus->primary = dev->bus->number; 282 bus->subordinate = busrange[1]; 283 bus->bridge_ctl = 0; 284 bus->sysdata = node; 285 286 /* parse ranges property */ 287 /* PCI #address-cells == 3 and #size-cells == 2 always */ 288 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 289 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 290 res->flags = 0; 291 bus->resource[i] = res; 292 ++res; 293 } 294 i = 1; 295 for (; len >= 32; len -= 32, ranges += 8) { 296 flags = pci_parse_of_flags(ranges[0]); 297 size = of_read_number(&ranges[6], 2); 298 if (flags == 0 || size == 0) 299 continue; 300 if (flags & IORESOURCE_IO) { 301 res = bus->resource[0]; 302 if (res->flags) { 303 printk(KERN_ERR "PCI: ignoring extra I/O range" 304 " for bridge %s\n", node->full_name); 305 continue; 306 } 307 } else { 308 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 309 printk(KERN_ERR "PCI: too many memory ranges" 310 " for bridge %s\n", node->full_name); 311 continue; 312 } 313 res = bus->resource[i]; 314 ++i; 315 } 316 res->start = of_read_number(&ranges[1], 2); 317 res->end = res->start + size - 1; 318 res->flags = flags; 319 } 320 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 321 bus->number); 322 pr_debug(" bus name: %s\n", bus->name); 323 324 mode = PCI_PROBE_NORMAL; 325 if (ppc_md.pci_probe_mode) 326 mode = ppc_md.pci_probe_mode(bus); 327 pr_debug(" probe mode: %d\n", mode); 328 329 if (mode == PCI_PROBE_DEVTREE) 330 of_scan_bus(node, bus); 331 else if (mode == PCI_PROBE_NORMAL) 332 pci_scan_child_bus(bus); 333 } 334 EXPORT_SYMBOL(of_scan_pci_bridge); 335 336 void __devinit scan_phb(struct pci_controller *hose) 337 { 338 struct pci_bus *bus; 339 struct device_node *node = hose->dn; 340 int mode; 341 342 pr_debug("PCI: Scanning PHB %s\n", 343 node ? node->full_name : "<NO NAME>"); 344 345 /* Create an empty bus for the toplevel */ 346 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node); 347 if (bus == NULL) { 348 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", 349 hose->global_number); 350 return; 351 } 352 bus->secondary = hose->first_busno; 353 hose->bus = bus; 354 355 /* Get some IO space for the new PHB */ 356 pcibios_map_io_space(bus); 357 358 /* Wire up PHB bus resources */ 359 pcibios_setup_phb_resources(hose); 360 361 /* Get probe mode and perform scan */ 362 mode = PCI_PROBE_NORMAL; 363 if (node && ppc_md.pci_probe_mode) 364 mode = ppc_md.pci_probe_mode(bus); 365 pr_debug(" probe mode: %d\n", mode); 366 if (mode == PCI_PROBE_DEVTREE) { 367 bus->subordinate = hose->last_busno; 368 of_scan_bus(node, bus); 369 } 370 371 if (mode == PCI_PROBE_NORMAL) 372 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 373 } 374 375 static int __init pcibios_init(void) 376 { 377 struct pci_controller *hose, *tmp; 378 379 printk(KERN_INFO "PCI: Probing PCI hardware\n"); 380 381 /* For now, override phys_mem_access_prot. If we need it,g 382 * later, we may move that initialization to each ppc_md 383 */ 384 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 385 386 if (pci_probe_only) 387 ppc_pci_flags |= PPC_PCI_PROBE_ONLY; 388 389 /* On ppc64, we always enable PCI domains and we keep domain 0 390 * backward compatible in /proc for video cards 391 */ 392 ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; 393 394 /* Scan all of the recorded PCI controllers. */ 395 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 396 scan_phb(hose); 397 pci_bus_add_devices(hose->bus); 398 } 399 400 /* Call common code to handle resource allocation */ 401 pcibios_resource_survey(); 402 403 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); 404 405 return 0; 406 } 407 408 subsys_initcall(pcibios_init); 409 410 #ifdef CONFIG_HOTPLUG 411 412 int pcibios_unmap_io_space(struct pci_bus *bus) 413 { 414 struct pci_controller *hose; 415 416 WARN_ON(bus == NULL); 417 418 /* If this is not a PHB, we only flush the hash table over 419 * the area mapped by this bridge. We don't play with the PTE 420 * mappings since we might have to deal with sub-page alignemnts 421 * so flushing the hash table is the only sane way to make sure 422 * that no hash entries are covering that removed bridge area 423 * while still allowing other busses overlapping those pages 424 */ 425 if (bus->self) { 426 struct resource *res = bus->resource[0]; 427 428 pr_debug("IO unmapping for PCI-PCI bridge %s\n", 429 pci_name(bus->self)); 430 431 __flush_hash_table_range(&init_mm, res->start + _IO_BASE, 432 res->end + _IO_BASE + 1); 433 return 0; 434 } 435 436 /* Get the host bridge */ 437 hose = pci_bus_to_host(bus); 438 439 /* Check if we have IOs allocated */ 440 if (hose->io_base_alloc == 0) 441 return 0; 442 443 pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name); 444 pr_debug(" alloc=0x%p\n", hose->io_base_alloc); 445 446 /* This is a PHB, we fully unmap the IO area */ 447 vunmap(hose->io_base_alloc); 448 449 return 0; 450 } 451 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); 452 453 #endif /* CONFIG_HOTPLUG */ 454 455 int __devinit pcibios_map_io_space(struct pci_bus *bus) 456 { 457 struct vm_struct *area; 458 unsigned long phys_page; 459 unsigned long size_page; 460 unsigned long io_virt_offset; 461 struct pci_controller *hose; 462 463 WARN_ON(bus == NULL); 464 465 /* If this not a PHB, nothing to do, page tables still exist and 466 * thus HPTEs will be faulted in when needed 467 */ 468 if (bus->self) { 469 pr_debug("IO mapping for PCI-PCI bridge %s\n", 470 pci_name(bus->self)); 471 pr_debug(" virt=0x%016llx...0x%016llx\n", 472 bus->resource[0]->start + _IO_BASE, 473 bus->resource[0]->end + _IO_BASE); 474 return 0; 475 } 476 477 /* Get the host bridge */ 478 hose = pci_bus_to_host(bus); 479 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); 480 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); 481 482 /* Make sure IO area address is clear */ 483 hose->io_base_alloc = NULL; 484 485 /* If there's no IO to map on that bus, get away too */ 486 if (hose->pci_io_size == 0 || hose->io_base_phys == 0) 487 return 0; 488 489 /* Let's allocate some IO space for that guy. We don't pass 490 * VM_IOREMAP because we don't care about alignment tricks that 491 * the core does in that case. Maybe we should due to stupid card 492 * with incomplete address decoding but I'd rather not deal with 493 * those outside of the reserved 64K legacy region. 494 */ 495 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); 496 if (area == NULL) 497 return -ENOMEM; 498 hose->io_base_alloc = area->addr; 499 hose->io_base_virt = (void __iomem *)(area->addr + 500 hose->io_base_phys - phys_page); 501 502 pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); 503 pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", 504 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); 505 pr_debug(" size=0x%016lx (alloc=0x%016lx)\n", 506 hose->pci_io_size, size_page); 507 508 /* Establish the mapping */ 509 if (__ioremap_at(phys_page, area->addr, size_page, 510 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL) 511 return -ENOMEM; 512 513 /* Fixup hose IO resource */ 514 io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 515 hose->io_resource.start += io_virt_offset; 516 hose->io_resource.end += io_virt_offset; 517 518 pr_debug(" hose->io_resource=0x%016llx...0x%016llx\n", 519 hose->io_resource.start, hose->io_resource.end); 520 521 return 0; 522 } 523 EXPORT_SYMBOL_GPL(pcibios_map_io_space); 524 525 #define IOBASE_BRIDGE_NUMBER 0 526 #define IOBASE_MEMORY 1 527 #define IOBASE_IO 2 528 #define IOBASE_ISA_IO 3 529 #define IOBASE_ISA_MEM 4 530 531 long sys_pciconfig_iobase(long which, unsigned long in_bus, 532 unsigned long in_devfn) 533 { 534 struct pci_controller* hose; 535 struct list_head *ln; 536 struct pci_bus *bus = NULL; 537 struct device_node *hose_node; 538 539 /* Argh ! Please forgive me for that hack, but that's the 540 * simplest way to get existing XFree to not lockup on some 541 * G5 machines... So when something asks for bus 0 io base 542 * (bus 0 is HT root), we return the AGP one instead. 543 */ 544 if (in_bus == 0 && machine_is_compatible("MacRISC4")) { 545 struct device_node *agp; 546 547 agp = of_find_compatible_node(NULL, NULL, "u3-agp"); 548 if (agp) 549 in_bus = 0xf0; 550 of_node_put(agp); 551 } 552 553 /* That syscall isn't quite compatible with PCI domains, but it's 554 * used on pre-domains setup. We return the first match 555 */ 556 557 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { 558 bus = pci_bus_b(ln); 559 if (in_bus >= bus->number && in_bus <= bus->subordinate) 560 break; 561 bus = NULL; 562 } 563 if (bus == NULL || bus->sysdata == NULL) 564 return -ENODEV; 565 566 hose_node = (struct device_node *)bus->sysdata; 567 hose = PCI_DN(hose_node)->phb; 568 569 switch (which) { 570 case IOBASE_BRIDGE_NUMBER: 571 return (long)hose->first_busno; 572 case IOBASE_MEMORY: 573 return (long)hose->pci_mem_offset; 574 case IOBASE_IO: 575 return (long)hose->io_base_phys; 576 case IOBASE_ISA_IO: 577 return (long)isa_io_base; 578 case IOBASE_ISA_MEM: 579 return -EINVAL; 580 } 581 582 return -EOPNOTSUPP; 583 } 584 585 #ifdef CONFIG_NUMA 586 int pcibus_to_node(struct pci_bus *bus) 587 { 588 struct pci_controller *phb = pci_bus_to_host(bus); 589 return phb->node; 590 } 591 EXPORT_SYMBOL(pcibus_to_node); 592 #endif 593