1 /* 2 * Port for PPC64 David Engebretsen, IBM Corp. 3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 4 * 5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 6 * Rework, based on alpha PCI code. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #undef DEBUG 15 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 #include <linux/export.h> 21 #include <linux/mm.h> 22 #include <linux/list.h> 23 #include <linux/syscalls.h> 24 #include <linux/irq.h> 25 #include <linux/vmalloc.h> 26 27 #include <asm/processor.h> 28 #include <asm/io.h> 29 #include <asm/prom.h> 30 #include <asm/pci-bridge.h> 31 #include <asm/byteorder.h> 32 #include <asm/machdep.h> 33 #include <asm/ppc-pci.h> 34 35 /* pci_io_base -- the base address from which io bars are offsets. 36 * This is the lowest I/O base address (so bar values are always positive), 37 * and it *must* be the start of ISA space if an ISA bus exists because 38 * ISA drivers use hard coded offsets. If no ISA bus exists nothing 39 * is mapped on the first 64K of IO space 40 */ 41 unsigned long pci_io_base; 42 EXPORT_SYMBOL(pci_io_base); 43 44 static int __init pcibios_init(void) 45 { 46 struct pci_controller *hose, *tmp; 47 48 printk(KERN_INFO "PCI: Probing PCI hardware\n"); 49 50 /* For now, override phys_mem_access_prot. If we need it,g 51 * later, we may move that initialization to each ppc_md 52 */ 53 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 54 55 /* On ppc64, we always enable PCI domains and we keep domain 0 56 * backward compatible in /proc for video cards 57 */ 58 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 59 60 /* Scan all of the recorded PCI controllers. */ 61 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 62 pcibios_scan_phb(hose); 63 pci_bus_add_devices(hose->bus); 64 } 65 66 /* Call common code to handle resource allocation */ 67 pcibios_resource_survey(); 68 69 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); 70 71 return 0; 72 } 73 74 subsys_initcall(pcibios_init); 75 76 int pcibios_unmap_io_space(struct pci_bus *bus) 77 { 78 struct pci_controller *hose; 79 80 WARN_ON(bus == NULL); 81 82 /* If this is not a PHB, we only flush the hash table over 83 * the area mapped by this bridge. We don't play with the PTE 84 * mappings since we might have to deal with sub-page alignemnts 85 * so flushing the hash table is the only sane way to make sure 86 * that no hash entries are covering that removed bridge area 87 * while still allowing other busses overlapping those pages 88 * 89 * Note: If we ever support P2P hotplug on Book3E, we'll have 90 * to do an appropriate TLB flush here too 91 */ 92 if (bus->self) { 93 #ifdef CONFIG_PPC_STD_MMU_64 94 struct resource *res = bus->resource[0]; 95 #endif 96 97 pr_debug("IO unmapping for PCI-PCI bridge %s\n", 98 pci_name(bus->self)); 99 100 #ifdef CONFIG_PPC_STD_MMU_64 101 __flush_hash_table_range(&init_mm, res->start + _IO_BASE, 102 res->end + _IO_BASE + 1); 103 #endif 104 return 0; 105 } 106 107 /* Get the host bridge */ 108 hose = pci_bus_to_host(bus); 109 110 /* Check if we have IOs allocated */ 111 if (hose->io_base_alloc == NULL) 112 return 0; 113 114 pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name); 115 pr_debug(" alloc=0x%p\n", hose->io_base_alloc); 116 117 /* This is a PHB, we fully unmap the IO area */ 118 vunmap(hose->io_base_alloc); 119 120 return 0; 121 } 122 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); 123 124 static int pcibios_map_phb_io_space(struct pci_controller *hose) 125 { 126 struct vm_struct *area; 127 unsigned long phys_page; 128 unsigned long size_page; 129 unsigned long io_virt_offset; 130 131 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); 132 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); 133 134 /* Make sure IO area address is clear */ 135 hose->io_base_alloc = NULL; 136 137 /* If there's no IO to map on that bus, get away too */ 138 if (hose->pci_io_size == 0 || hose->io_base_phys == 0) 139 return 0; 140 141 /* Let's allocate some IO space for that guy. We don't pass 142 * VM_IOREMAP because we don't care about alignment tricks that 143 * the core does in that case. Maybe we should due to stupid card 144 * with incomplete address decoding but I'd rather not deal with 145 * those outside of the reserved 64K legacy region. 146 */ 147 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); 148 if (area == NULL) 149 return -ENOMEM; 150 hose->io_base_alloc = area->addr; 151 hose->io_base_virt = (void __iomem *)(area->addr + 152 hose->io_base_phys - phys_page); 153 154 pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); 155 pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", 156 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); 157 pr_debug(" size=0x%016llx (alloc=0x%016lx)\n", 158 hose->pci_io_size, size_page); 159 160 /* Establish the mapping */ 161 if (__ioremap_at(phys_page, area->addr, size_page, 162 pgprot_val(pgprot_noncached(__pgprot(0)))) == NULL) 163 return -ENOMEM; 164 165 /* Fixup hose IO resource */ 166 io_virt_offset = pcibios_io_space_offset(hose); 167 hose->io_resource.start += io_virt_offset; 168 hose->io_resource.end += io_virt_offset; 169 170 pr_debug(" hose->io_resource=%pR\n", &hose->io_resource); 171 172 return 0; 173 } 174 175 int pcibios_map_io_space(struct pci_bus *bus) 176 { 177 WARN_ON(bus == NULL); 178 179 /* If this not a PHB, nothing to do, page tables still exist and 180 * thus HPTEs will be faulted in when needed 181 */ 182 if (bus->self) { 183 pr_debug("IO mapping for PCI-PCI bridge %s\n", 184 pci_name(bus->self)); 185 pr_debug(" virt=0x%016llx...0x%016llx\n", 186 bus->resource[0]->start + _IO_BASE, 187 bus->resource[0]->end + _IO_BASE); 188 return 0; 189 } 190 191 return pcibios_map_phb_io_space(pci_bus_to_host(bus)); 192 } 193 EXPORT_SYMBOL_GPL(pcibios_map_io_space); 194 195 void pcibios_setup_phb_io_space(struct pci_controller *hose) 196 { 197 pcibios_map_phb_io_space(hose); 198 } 199 200 #define IOBASE_BRIDGE_NUMBER 0 201 #define IOBASE_MEMORY 1 202 #define IOBASE_IO 2 203 #define IOBASE_ISA_IO 3 204 #define IOBASE_ISA_MEM 4 205 206 long sys_pciconfig_iobase(long which, unsigned long in_bus, 207 unsigned long in_devfn) 208 { 209 struct pci_controller* hose; 210 struct pci_bus *tmp_bus, *bus = NULL; 211 struct device_node *hose_node; 212 213 /* Argh ! Please forgive me for that hack, but that's the 214 * simplest way to get existing XFree to not lockup on some 215 * G5 machines... So when something asks for bus 0 io base 216 * (bus 0 is HT root), we return the AGP one instead. 217 */ 218 if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) { 219 struct device_node *agp; 220 221 agp = of_find_compatible_node(NULL, NULL, "u3-agp"); 222 if (agp) 223 in_bus = 0xf0; 224 of_node_put(agp); 225 } 226 227 /* That syscall isn't quite compatible with PCI domains, but it's 228 * used on pre-domains setup. We return the first match 229 */ 230 231 list_for_each_entry(tmp_bus, &pci_root_buses, node) { 232 if (in_bus >= tmp_bus->number && 233 in_bus <= tmp_bus->busn_res.end) { 234 bus = tmp_bus; 235 break; 236 } 237 } 238 if (bus == NULL || bus->dev.of_node == NULL) 239 return -ENODEV; 240 241 hose_node = bus->dev.of_node; 242 hose = PCI_DN(hose_node)->phb; 243 244 switch (which) { 245 case IOBASE_BRIDGE_NUMBER: 246 return (long)hose->first_busno; 247 case IOBASE_MEMORY: 248 return (long)hose->mem_offset[0]; 249 case IOBASE_IO: 250 return (long)hose->io_base_phys; 251 case IOBASE_ISA_IO: 252 return (long)isa_io_base; 253 case IOBASE_ISA_MEM: 254 return -EINVAL; 255 } 256 257 return -EOPNOTSUPP; 258 } 259 260 #ifdef CONFIG_NUMA 261 int pcibus_to_node(struct pci_bus *bus) 262 { 263 struct pci_controller *phb = pci_bus_to_host(bus); 264 return phb->node; 265 } 266 EXPORT_SYMBOL(pcibus_to_node); 267 #endif 268