1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/mm.h> 25 #include <linux/list.h> 26 #include <linux/syscalls.h> 27 #include <linux/irq.h> 28 #include <linux/vmalloc.h> 29 30 #include <asm/processor.h> 31 #include <asm/io.h> 32 #include <asm/prom.h> 33 #include <asm/pci-bridge.h> 34 #include <asm/byteorder.h> 35 #include <asm/machdep.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/firmware.h> 38 #include <asm/eeh.h> 39 40 static DEFINE_SPINLOCK(hose_spinlock); 41 LIST_HEAD(hose_list); 42 43 /* XXX kill that some day ... */ 44 static int global_phb_number; /* Global phb counter */ 45 46 /* ISA Memory physical address */ 47 resource_size_t isa_mem_base; 48 49 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ 50 unsigned int ppc_pci_flags = 0; 51 52 53 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 54 55 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 56 { 57 pci_dma_ops = dma_ops; 58 } 59 60 struct dma_map_ops *get_pci_dma_ops(void) 61 { 62 return pci_dma_ops; 63 } 64 EXPORT_SYMBOL(get_pci_dma_ops); 65 66 int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 67 { 68 return dma_set_mask(&dev->dev, mask); 69 } 70 71 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 72 { 73 int rc; 74 75 rc = dma_set_mask(&dev->dev, mask); 76 dev->dev.coherent_dma_mask = dev->dma_mask; 77 78 return rc; 79 } 80 81 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 82 { 83 struct pci_controller *phb; 84 85 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 86 if (phb == NULL) 87 return NULL; 88 spin_lock(&hose_spinlock); 89 phb->global_number = global_phb_number++; 90 list_add_tail(&phb->list_node, &hose_list); 91 spin_unlock(&hose_spinlock); 92 phb->dn = dev; 93 phb->is_dynamic = mem_init_done; 94 #ifdef CONFIG_PPC64 95 if (dev) { 96 int nid = of_node_to_nid(dev); 97 98 if (nid < 0 || !node_online(nid)) 99 nid = -1; 100 101 PHB_SET_NODE(phb, nid); 102 } 103 #endif 104 return phb; 105 } 106 107 void pcibios_free_controller(struct pci_controller *phb) 108 { 109 spin_lock(&hose_spinlock); 110 list_del(&phb->list_node); 111 spin_unlock(&hose_spinlock); 112 113 if (phb->is_dynamic) 114 kfree(phb); 115 } 116 117 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 118 { 119 #ifdef CONFIG_PPC64 120 return hose->pci_io_size; 121 #else 122 return hose->io_resource.end - hose->io_resource.start + 1; 123 #endif 124 } 125 126 int pcibios_vaddr_is_ioport(void __iomem *address) 127 { 128 int ret = 0; 129 struct pci_controller *hose; 130 resource_size_t size; 131 132 spin_lock(&hose_spinlock); 133 list_for_each_entry(hose, &hose_list, list_node) { 134 size = pcibios_io_size(hose); 135 if (address >= hose->io_base_virt && 136 address < (hose->io_base_virt + size)) { 137 ret = 1; 138 break; 139 } 140 } 141 spin_unlock(&hose_spinlock); 142 return ret; 143 } 144 145 unsigned long pci_address_to_pio(phys_addr_t address) 146 { 147 struct pci_controller *hose; 148 resource_size_t size; 149 unsigned long ret = ~0; 150 151 spin_lock(&hose_spinlock); 152 list_for_each_entry(hose, &hose_list, list_node) { 153 size = pcibios_io_size(hose); 154 if (address >= hose->io_base_phys && 155 address < (hose->io_base_phys + size)) { 156 unsigned long base = 157 (unsigned long)hose->io_base_virt - _IO_BASE; 158 ret = base + (address - hose->io_base_phys); 159 break; 160 } 161 } 162 spin_unlock(&hose_spinlock); 163 164 return ret; 165 } 166 EXPORT_SYMBOL_GPL(pci_address_to_pio); 167 168 /* 169 * Return the domain number for this bus. 170 */ 171 int pci_domain_nr(struct pci_bus *bus) 172 { 173 struct pci_controller *hose = pci_bus_to_host(bus); 174 175 return hose->global_number; 176 } 177 EXPORT_SYMBOL(pci_domain_nr); 178 179 /* This routine is meant to be used early during boot, when the 180 * PCI bus numbers have not yet been assigned, and you need to 181 * issue PCI config cycles to an OF device. 182 * It could also be used to "fix" RTAS config cycles if you want 183 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 184 * config cycles. 185 */ 186 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 187 { 188 while(node) { 189 struct pci_controller *hose, *tmp; 190 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 191 if (hose->dn == node) 192 return hose; 193 node = node->parent; 194 } 195 return NULL; 196 } 197 198 static ssize_t pci_show_devspec(struct device *dev, 199 struct device_attribute *attr, char *buf) 200 { 201 struct pci_dev *pdev; 202 struct device_node *np; 203 204 pdev = to_pci_dev (dev); 205 np = pci_device_to_OF_node(pdev); 206 if (np == NULL || np->full_name == NULL) 207 return 0; 208 return sprintf(buf, "%s", np->full_name); 209 } 210 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 211 212 /* Add sysfs properties */ 213 int pcibios_add_platform_entries(struct pci_dev *pdev) 214 { 215 return device_create_file(&pdev->dev, &dev_attr_devspec); 216 } 217 218 char __devinit *pcibios_setup(char *str) 219 { 220 return str; 221 } 222 223 /* 224 * Reads the interrupt pin to determine if interrupt is use by card. 225 * If the interrupt is used, then gets the interrupt line from the 226 * openfirmware and sets it in the pci_dev and pci_config line. 227 */ 228 int pci_read_irq_line(struct pci_dev *pci_dev) 229 { 230 struct of_irq oirq; 231 unsigned int virq; 232 233 /* The current device-tree that iSeries generates from the HV 234 * PCI informations doesn't contain proper interrupt routing, 235 * and all the fallback would do is print out crap, so we 236 * don't attempt to resolve the interrupts here at all, some 237 * iSeries specific fixup does it. 238 * 239 * In the long run, we will hopefully fix the generated device-tree 240 * instead. 241 */ 242 #ifdef CONFIG_PPC_ISERIES 243 if (firmware_has_feature(FW_FEATURE_ISERIES)) 244 return -1; 245 #endif 246 247 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 248 249 #ifdef DEBUG 250 memset(&oirq, 0xff, sizeof(oirq)); 251 #endif 252 /* Try to get a mapping from the device-tree */ 253 if (of_irq_map_pci(pci_dev, &oirq)) { 254 u8 line, pin; 255 256 /* If that fails, lets fallback to what is in the config 257 * space and map that through the default controller. We 258 * also set the type to level low since that's what PCI 259 * interrupts are. If your platform does differently, then 260 * either provide a proper interrupt tree or don't use this 261 * function. 262 */ 263 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 264 return -1; 265 if (pin == 0) 266 return -1; 267 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 268 line == 0xff || line == 0) { 269 return -1; 270 } 271 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 272 line, pin); 273 274 virq = irq_create_mapping(NULL, line); 275 if (virq != NO_IRQ) 276 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 277 } else { 278 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 279 oirq.size, oirq.specifier[0], oirq.specifier[1], 280 oirq.controller ? oirq.controller->full_name : 281 "<default>"); 282 283 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 284 oirq.size); 285 } 286 if(virq == NO_IRQ) { 287 pr_debug(" Failed to map !\n"); 288 return -1; 289 } 290 291 pr_debug(" Mapped to linux irq %d\n", virq); 292 293 pci_dev->irq = virq; 294 295 return 0; 296 } 297 EXPORT_SYMBOL(pci_read_irq_line); 298 299 /* 300 * Platform support for /proc/bus/pci/X/Y mmap()s, 301 * modelled on the sparc64 implementation by Dave Miller. 302 * -- paulus. 303 */ 304 305 /* 306 * Adjust vm_pgoff of VMA such that it is the physical page offset 307 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 308 * 309 * Basically, the user finds the base address for his device which he wishes 310 * to mmap. They read the 32-bit value from the config space base register, 311 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 312 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 313 * 314 * Returns negative error code on failure, zero on success. 315 */ 316 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 317 resource_size_t *offset, 318 enum pci_mmap_state mmap_state) 319 { 320 struct pci_controller *hose = pci_bus_to_host(dev->bus); 321 unsigned long io_offset = 0; 322 int i, res_bit; 323 324 if (hose == 0) 325 return NULL; /* should never happen */ 326 327 /* If memory, add on the PCI bridge address offset */ 328 if (mmap_state == pci_mmap_mem) { 329 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 330 *offset += hose->pci_mem_offset; 331 #endif 332 res_bit = IORESOURCE_MEM; 333 } else { 334 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 335 *offset += io_offset; 336 res_bit = IORESOURCE_IO; 337 } 338 339 /* 340 * Check that the offset requested corresponds to one of the 341 * resources of the device. 342 */ 343 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 344 struct resource *rp = &dev->resource[i]; 345 int flags = rp->flags; 346 347 /* treat ROM as memory (should be already) */ 348 if (i == PCI_ROM_RESOURCE) 349 flags |= IORESOURCE_MEM; 350 351 /* Active and same type? */ 352 if ((flags & res_bit) == 0) 353 continue; 354 355 /* In the range of this resource? */ 356 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 357 continue; 358 359 /* found it! construct the final physical address */ 360 if (mmap_state == pci_mmap_io) 361 *offset += hose->io_base_phys - io_offset; 362 return rp; 363 } 364 365 return NULL; 366 } 367 368 /* 369 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 370 * device mapping. 371 */ 372 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 373 pgprot_t protection, 374 enum pci_mmap_state mmap_state, 375 int write_combine) 376 { 377 unsigned long prot = pgprot_val(protection); 378 379 /* Write combine is always 0 on non-memory space mappings. On 380 * memory space, if the user didn't pass 1, we check for a 381 * "prefetchable" resource. This is a bit hackish, but we use 382 * this to workaround the inability of /sysfs to provide a write 383 * combine bit 384 */ 385 if (mmap_state != pci_mmap_mem) 386 write_combine = 0; 387 else if (write_combine == 0) { 388 if (rp->flags & IORESOURCE_PREFETCH) 389 write_combine = 1; 390 } 391 392 /* XXX would be nice to have a way to ask for write-through */ 393 if (write_combine) 394 return pgprot_noncached_wc(prot); 395 else 396 return pgprot_noncached(prot); 397 } 398 399 /* 400 * This one is used by /dev/mem and fbdev who have no clue about the 401 * PCI device, it tries to find the PCI device first and calls the 402 * above routine 403 */ 404 pgprot_t pci_phys_mem_access_prot(struct file *file, 405 unsigned long pfn, 406 unsigned long size, 407 pgprot_t prot) 408 { 409 struct pci_dev *pdev = NULL; 410 struct resource *found = NULL; 411 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 412 int i; 413 414 if (page_is_ram(pfn)) 415 return prot; 416 417 prot = pgprot_noncached(prot); 418 for_each_pci_dev(pdev) { 419 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 420 struct resource *rp = &pdev->resource[i]; 421 int flags = rp->flags; 422 423 /* Active and same type? */ 424 if ((flags & IORESOURCE_MEM) == 0) 425 continue; 426 /* In the range of this resource? */ 427 if (offset < (rp->start & PAGE_MASK) || 428 offset > rp->end) 429 continue; 430 found = rp; 431 break; 432 } 433 if (found) 434 break; 435 } 436 if (found) { 437 if (found->flags & IORESOURCE_PREFETCH) 438 prot = pgprot_noncached_wc(prot); 439 pci_dev_put(pdev); 440 } 441 442 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 443 (unsigned long long)offset, pgprot_val(prot)); 444 445 return prot; 446 } 447 448 449 /* 450 * Perform the actual remap of the pages for a PCI device mapping, as 451 * appropriate for this architecture. The region in the process to map 452 * is described by vm_start and vm_end members of VMA, the base physical 453 * address is found in vm_pgoff. 454 * The pci device structure is provided so that architectures may make mapping 455 * decisions on a per-device or per-bus basis. 456 * 457 * Returns a negative error code on failure, zero on success. 458 */ 459 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 460 enum pci_mmap_state mmap_state, int write_combine) 461 { 462 resource_size_t offset = 463 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 464 struct resource *rp; 465 int ret; 466 467 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 468 if (rp == NULL) 469 return -EINVAL; 470 471 vma->vm_pgoff = offset >> PAGE_SHIFT; 472 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 473 vma->vm_page_prot, 474 mmap_state, write_combine); 475 476 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 477 vma->vm_end - vma->vm_start, vma->vm_page_prot); 478 479 return ret; 480 } 481 482 /* This provides legacy IO read access on a bus */ 483 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 484 { 485 unsigned long offset; 486 struct pci_controller *hose = pci_bus_to_host(bus); 487 struct resource *rp = &hose->io_resource; 488 void __iomem *addr; 489 490 /* Check if port can be supported by that bus. We only check 491 * the ranges of the PHB though, not the bus itself as the rules 492 * for forwarding legacy cycles down bridges are not our problem 493 * here. So if the host bridge supports it, we do it. 494 */ 495 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 496 offset += port; 497 498 if (!(rp->flags & IORESOURCE_IO)) 499 return -ENXIO; 500 if (offset < rp->start || (offset + size) > rp->end) 501 return -ENXIO; 502 addr = hose->io_base_virt + port; 503 504 switch(size) { 505 case 1: 506 *((u8 *)val) = in_8(addr); 507 return 1; 508 case 2: 509 if (port & 1) 510 return -EINVAL; 511 *((u16 *)val) = in_le16(addr); 512 return 2; 513 case 4: 514 if (port & 3) 515 return -EINVAL; 516 *((u32 *)val) = in_le32(addr); 517 return 4; 518 } 519 return -EINVAL; 520 } 521 522 /* This provides legacy IO write access on a bus */ 523 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 524 { 525 unsigned long offset; 526 struct pci_controller *hose = pci_bus_to_host(bus); 527 struct resource *rp = &hose->io_resource; 528 void __iomem *addr; 529 530 /* Check if port can be supported by that bus. We only check 531 * the ranges of the PHB though, not the bus itself as the rules 532 * for forwarding legacy cycles down bridges are not our problem 533 * here. So if the host bridge supports it, we do it. 534 */ 535 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 536 offset += port; 537 538 if (!(rp->flags & IORESOURCE_IO)) 539 return -ENXIO; 540 if (offset < rp->start || (offset + size) > rp->end) 541 return -ENXIO; 542 addr = hose->io_base_virt + port; 543 544 /* WARNING: The generic code is idiotic. It gets passed a pointer 545 * to what can be a 1, 2 or 4 byte quantity and always reads that 546 * as a u32, which means that we have to correct the location of 547 * the data read within those 32 bits for size 1 and 2 548 */ 549 switch(size) { 550 case 1: 551 out_8(addr, val >> 24); 552 return 1; 553 case 2: 554 if (port & 1) 555 return -EINVAL; 556 out_le16(addr, val >> 16); 557 return 2; 558 case 4: 559 if (port & 3) 560 return -EINVAL; 561 out_le32(addr, val); 562 return 4; 563 } 564 return -EINVAL; 565 } 566 567 /* This provides legacy IO or memory mmap access on a bus */ 568 int pci_mmap_legacy_page_range(struct pci_bus *bus, 569 struct vm_area_struct *vma, 570 enum pci_mmap_state mmap_state) 571 { 572 struct pci_controller *hose = pci_bus_to_host(bus); 573 resource_size_t offset = 574 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 575 resource_size_t size = vma->vm_end - vma->vm_start; 576 struct resource *rp; 577 578 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 579 pci_domain_nr(bus), bus->number, 580 mmap_state == pci_mmap_mem ? "MEM" : "IO", 581 (unsigned long long)offset, 582 (unsigned long long)(offset + size - 1)); 583 584 if (mmap_state == pci_mmap_mem) { 585 /* Hack alert ! 586 * 587 * Because X is lame and can fail starting if it gets an error trying 588 * to mmap legacy_mem (instead of just moving on without legacy memory 589 * access) we fake it here by giving it anonymous memory, effectively 590 * behaving just like /dev/zero 591 */ 592 if ((offset + size) > hose->isa_mem_size) { 593 printk(KERN_DEBUG 594 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 595 current->comm, current->pid, pci_domain_nr(bus), bus->number); 596 if (vma->vm_flags & VM_SHARED) 597 return shmem_zero_setup(vma); 598 return 0; 599 } 600 offset += hose->isa_mem_phys; 601 } else { 602 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 603 unsigned long roffset = offset + io_offset; 604 rp = &hose->io_resource; 605 if (!(rp->flags & IORESOURCE_IO)) 606 return -ENXIO; 607 if (roffset < rp->start || (roffset + size) > rp->end) 608 return -ENXIO; 609 offset += hose->io_base_phys; 610 } 611 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 612 613 vma->vm_pgoff = offset >> PAGE_SHIFT; 614 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 615 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 616 vma->vm_end - vma->vm_start, 617 vma->vm_page_prot); 618 } 619 620 void pci_resource_to_user(const struct pci_dev *dev, int bar, 621 const struct resource *rsrc, 622 resource_size_t *start, resource_size_t *end) 623 { 624 struct pci_controller *hose = pci_bus_to_host(dev->bus); 625 resource_size_t offset = 0; 626 627 if (hose == NULL) 628 return; 629 630 if (rsrc->flags & IORESOURCE_IO) 631 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 632 633 /* We pass a fully fixed up address to userland for MMIO instead of 634 * a BAR value because X is lame and expects to be able to use that 635 * to pass to /dev/mem ! 636 * 637 * That means that we'll have potentially 64 bits values where some 638 * userland apps only expect 32 (like X itself since it thinks only 639 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 640 * 32 bits CHRPs :-( 641 * 642 * Hopefully, the sysfs insterface is immune to that gunk. Once X 643 * has been fixed (and the fix spread enough), we can re-enable the 644 * 2 lines below and pass down a BAR value to userland. In that case 645 * we'll also have to re-enable the matching code in 646 * __pci_mmap_make_offset(). 647 * 648 * BenH. 649 */ 650 #if 0 651 else if (rsrc->flags & IORESOURCE_MEM) 652 offset = hose->pci_mem_offset; 653 #endif 654 655 *start = rsrc->start - offset; 656 *end = rsrc->end - offset; 657 } 658 659 /** 660 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 661 * @hose: newly allocated pci_controller to be setup 662 * @dev: device node of the host bridge 663 * @primary: set if primary bus (32 bits only, soon to be deprecated) 664 * 665 * This function will parse the "ranges" property of a PCI host bridge device 666 * node and setup the resource mapping of a pci controller based on its 667 * content. 668 * 669 * Life would be boring if it wasn't for a few issues that we have to deal 670 * with here: 671 * 672 * - We can only cope with one IO space range and up to 3 Memory space 673 * ranges. However, some machines (thanks Apple !) tend to split their 674 * space into lots of small contiguous ranges. So we have to coalesce. 675 * 676 * - We can only cope with all memory ranges having the same offset 677 * between CPU addresses and PCI addresses. Unfortunately, some bridges 678 * are setup for a large 1:1 mapping along with a small "window" which 679 * maps PCI address 0 to some arbitrary high address of the CPU space in 680 * order to give access to the ISA memory hole. 681 * The way out of here that I've chosen for now is to always set the 682 * offset based on the first resource found, then override it if we 683 * have a different offset and the previous was set by an ISA hole. 684 * 685 * - Some busses have IO space not starting at 0, which causes trouble with 686 * the way we do our IO resource renumbering. The code somewhat deals with 687 * it for 64 bits but I would expect problems on 32 bits. 688 * 689 * - Some 32 bits platforms such as 4xx can have physical space larger than 690 * 32 bits so we need to use 64 bits values for the parsing 691 */ 692 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 693 struct device_node *dev, 694 int primary) 695 { 696 const u32 *ranges; 697 int rlen; 698 int pna = of_n_addr_cells(dev); 699 int np = pna + 5; 700 int memno = 0, isa_hole = -1; 701 u32 pci_space; 702 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 703 unsigned long long isa_mb = 0; 704 struct resource *res; 705 706 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 707 dev->full_name, primary ? "(primary)" : ""); 708 709 /* Get ranges property */ 710 ranges = of_get_property(dev, "ranges", &rlen); 711 if (ranges == NULL) 712 return; 713 714 /* Parse it */ 715 while ((rlen -= np * 4) >= 0) { 716 /* Read next ranges element */ 717 pci_space = ranges[0]; 718 pci_addr = of_read_number(ranges + 1, 2); 719 cpu_addr = of_translate_address(dev, ranges + 3); 720 size = of_read_number(ranges + pna + 3, 2); 721 ranges += np; 722 723 /* If we failed translation or got a zero-sized region 724 * (some FW try to feed us with non sensical zero sized regions 725 * such as power3 which look like some kind of attempt at exposing 726 * the VGA memory hole) 727 */ 728 if (cpu_addr == OF_BAD_ADDR || size == 0) 729 continue; 730 731 /* Now consume following elements while they are contiguous */ 732 for (; rlen >= np * sizeof(u32); 733 ranges += np, rlen -= np * 4) { 734 if (ranges[0] != pci_space) 735 break; 736 pci_next = of_read_number(ranges + 1, 2); 737 cpu_next = of_translate_address(dev, ranges + 3); 738 if (pci_next != pci_addr + size || 739 cpu_next != cpu_addr + size) 740 break; 741 size += of_read_number(ranges + pna + 3, 2); 742 } 743 744 /* Act based on address space type */ 745 res = NULL; 746 switch ((pci_space >> 24) & 0x3) { 747 case 1: /* PCI IO space */ 748 printk(KERN_INFO 749 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 750 cpu_addr, cpu_addr + size - 1, pci_addr); 751 752 /* We support only one IO range */ 753 if (hose->pci_io_size) { 754 printk(KERN_INFO 755 " \\--> Skipped (too many) !\n"); 756 continue; 757 } 758 #ifdef CONFIG_PPC32 759 /* On 32 bits, limit I/O space to 16MB */ 760 if (size > 0x01000000) 761 size = 0x01000000; 762 763 /* 32 bits needs to map IOs here */ 764 hose->io_base_virt = ioremap(cpu_addr, size); 765 766 /* Expect trouble if pci_addr is not 0 */ 767 if (primary) 768 isa_io_base = 769 (unsigned long)hose->io_base_virt; 770 #endif /* CONFIG_PPC32 */ 771 /* pci_io_size and io_base_phys always represent IO 772 * space starting at 0 so we factor in pci_addr 773 */ 774 hose->pci_io_size = pci_addr + size; 775 hose->io_base_phys = cpu_addr - pci_addr; 776 777 /* Build resource */ 778 res = &hose->io_resource; 779 res->flags = IORESOURCE_IO; 780 res->start = pci_addr; 781 break; 782 case 2: /* PCI Memory space */ 783 case 3: /* PCI 64 bits Memory space */ 784 printk(KERN_INFO 785 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 786 cpu_addr, cpu_addr + size - 1, pci_addr, 787 (pci_space & 0x40000000) ? "Prefetch" : ""); 788 789 /* We support only 3 memory ranges */ 790 if (memno >= 3) { 791 printk(KERN_INFO 792 " \\--> Skipped (too many) !\n"); 793 continue; 794 } 795 /* Handles ISA memory hole space here */ 796 if (pci_addr == 0) { 797 isa_mb = cpu_addr; 798 isa_hole = memno; 799 if (primary || isa_mem_base == 0) 800 isa_mem_base = cpu_addr; 801 hose->isa_mem_phys = cpu_addr; 802 hose->isa_mem_size = size; 803 } 804 805 /* We get the PCI/Mem offset from the first range or 806 * the, current one if the offset came from an ISA 807 * hole. If they don't match, bugger. 808 */ 809 if (memno == 0 || 810 (isa_hole >= 0 && pci_addr != 0 && 811 hose->pci_mem_offset == isa_mb)) 812 hose->pci_mem_offset = cpu_addr - pci_addr; 813 else if (pci_addr != 0 && 814 hose->pci_mem_offset != cpu_addr - pci_addr) { 815 printk(KERN_INFO 816 " \\--> Skipped (offset mismatch) !\n"); 817 continue; 818 } 819 820 /* Build resource */ 821 res = &hose->mem_resources[memno++]; 822 res->flags = IORESOURCE_MEM; 823 if (pci_space & 0x40000000) 824 res->flags |= IORESOURCE_PREFETCH; 825 res->start = cpu_addr; 826 break; 827 } 828 if (res != NULL) { 829 res->name = dev->full_name; 830 res->end = res->start + size - 1; 831 res->parent = NULL; 832 res->sibling = NULL; 833 res->child = NULL; 834 } 835 } 836 837 /* If there's an ISA hole and the pci_mem_offset is -not- matching 838 * the ISA hole offset, then we need to remove the ISA hole from 839 * the resource list for that brige 840 */ 841 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 842 unsigned int next = isa_hole + 1; 843 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 844 if (next < memno) 845 memmove(&hose->mem_resources[isa_hole], 846 &hose->mem_resources[next], 847 sizeof(struct resource) * (memno - next)); 848 hose->mem_resources[--memno].flags = 0; 849 } 850 } 851 852 /* Decide whether to display the domain number in /proc */ 853 int pci_proc_domain(struct pci_bus *bus) 854 { 855 struct pci_controller *hose = pci_bus_to_host(bus); 856 857 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) 858 return 0; 859 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) 860 return hose->global_number != 0; 861 return 1; 862 } 863 864 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 865 struct resource *res) 866 { 867 resource_size_t offset = 0, mask = (resource_size_t)-1; 868 struct pci_controller *hose = pci_bus_to_host(dev->bus); 869 870 if (!hose) 871 return; 872 if (res->flags & IORESOURCE_IO) { 873 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 874 mask = 0xffffffffu; 875 } else if (res->flags & IORESOURCE_MEM) 876 offset = hose->pci_mem_offset; 877 878 region->start = (res->start - offset) & mask; 879 region->end = (res->end - offset) & mask; 880 } 881 EXPORT_SYMBOL(pcibios_resource_to_bus); 882 883 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 884 struct pci_bus_region *region) 885 { 886 resource_size_t offset = 0, mask = (resource_size_t)-1; 887 struct pci_controller *hose = pci_bus_to_host(dev->bus); 888 889 if (!hose) 890 return; 891 if (res->flags & IORESOURCE_IO) { 892 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 893 mask = 0xffffffffu; 894 } else if (res->flags & IORESOURCE_MEM) 895 offset = hose->pci_mem_offset; 896 res->start = (region->start + offset) & mask; 897 res->end = (region->end + offset) & mask; 898 } 899 EXPORT_SYMBOL(pcibios_bus_to_resource); 900 901 /* Fixup a bus resource into a linux resource */ 902 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) 903 { 904 struct pci_controller *hose = pci_bus_to_host(dev->bus); 905 resource_size_t offset = 0, mask = (resource_size_t)-1; 906 907 if (res->flags & IORESOURCE_IO) { 908 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 909 mask = 0xffffffffu; 910 } else if (res->flags & IORESOURCE_MEM) 911 offset = hose->pci_mem_offset; 912 913 res->start = (res->start + offset) & mask; 914 res->end = (res->end + offset) & mask; 915 } 916 917 918 /* This header fixup will do the resource fixup for all devices as they are 919 * probed, but not for bridge ranges 920 */ 921 static void __devinit pcibios_fixup_resources(struct pci_dev *dev) 922 { 923 struct pci_controller *hose = pci_bus_to_host(dev->bus); 924 int i; 925 926 if (!hose) { 927 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 928 pci_name(dev)); 929 return; 930 } 931 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 932 struct resource *res = dev->resource + i; 933 if (!res->flags) 934 continue; 935 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't 936 * consider 0 as an unassigned BAR value. It's technically 937 * a valid value, but linux doesn't like it... so when we can 938 * re-assign things, we do so, but if we can't, we keep it 939 * around and hope for the best... 940 */ 941 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 942 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 943 pci_name(dev), i, 944 (unsigned long long)res->start, 945 (unsigned long long)res->end, 946 (unsigned int)res->flags); 947 res->end -= res->start; 948 res->start = 0; 949 res->flags |= IORESOURCE_UNSET; 950 continue; 951 } 952 953 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", 954 pci_name(dev), i, 955 (unsigned long long)res->start,\ 956 (unsigned long long)res->end, 957 (unsigned int)res->flags); 958 959 fixup_resource(res, dev); 960 961 pr_debug("PCI:%s %016llx-%016llx\n", 962 pci_name(dev), 963 (unsigned long long)res->start, 964 (unsigned long long)res->end); 965 } 966 967 /* Call machine specific resource fixup */ 968 if (ppc_md.pcibios_fixup_resources) 969 ppc_md.pcibios_fixup_resources(dev); 970 } 971 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 972 973 /* This function tries to figure out if a bridge resource has been initialized 974 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 975 * things go more smoothly when it gets it right. It should covers cases such 976 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 977 */ 978 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 979 struct resource *res) 980 { 981 struct pci_controller *hose = pci_bus_to_host(bus); 982 struct pci_dev *dev = bus->self; 983 resource_size_t offset; 984 u16 command; 985 int i; 986 987 /* We don't do anything if PCI_PROBE_ONLY is set */ 988 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY) 989 return 0; 990 991 /* Job is a bit different between memory and IO */ 992 if (res->flags & IORESOURCE_MEM) { 993 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been 994 * initialized by somebody 995 */ 996 if (res->start != hose->pci_mem_offset) 997 return 0; 998 999 /* The BAR is 0, let's check if memory decoding is enabled on 1000 * the bridge. If not, we consider it unassigned 1001 */ 1002 pci_read_config_word(dev, PCI_COMMAND, &command); 1003 if ((command & PCI_COMMAND_MEMORY) == 0) 1004 return 1; 1005 1006 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 1007 * resources covers that starting address (0 then it's good enough for 1008 * us for memory 1009 */ 1010 for (i = 0; i < 3; i++) { 1011 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 1012 hose->mem_resources[i].start == hose->pci_mem_offset) 1013 return 0; 1014 } 1015 1016 /* Well, it starts at 0 and we know it will collide so we may as 1017 * well consider it as unassigned. That covers the Apple case. 1018 */ 1019 return 1; 1020 } else { 1021 /* If the BAR is non-0, then we consider it assigned */ 1022 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1023 if (((res->start - offset) & 0xfffffffful) != 0) 1024 return 0; 1025 1026 /* Here, we are a bit different than memory as typically IO space 1027 * starting at low addresses -is- valid. What we do instead if that 1028 * we consider as unassigned anything that doesn't have IO enabled 1029 * in the PCI command register, and that's it. 1030 */ 1031 pci_read_config_word(dev, PCI_COMMAND, &command); 1032 if (command & PCI_COMMAND_IO) 1033 return 0; 1034 1035 /* It's starting at 0 and IO is disabled in the bridge, consider 1036 * it unassigned 1037 */ 1038 return 1; 1039 } 1040 } 1041 1042 /* Fixup resources of a PCI<->PCI bridge */ 1043 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) 1044 { 1045 struct resource *res; 1046 int i; 1047 1048 struct pci_dev *dev = bus->self; 1049 1050 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 1051 if ((res = bus->resource[i]) == NULL) 1052 continue; 1053 if (!res->flags) 1054 continue; 1055 if (i >= 3 && bus->self->transparent) 1056 continue; 1057 1058 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", 1059 pci_name(dev), i, 1060 (unsigned long long)res->start,\ 1061 (unsigned long long)res->end, 1062 (unsigned int)res->flags); 1063 1064 /* Perform fixup */ 1065 fixup_resource(res, dev); 1066 1067 /* Try to detect uninitialized P2P bridge resources, 1068 * and clear them out so they get re-assigned later 1069 */ 1070 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1071 res->flags = 0; 1072 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1073 } else { 1074 1075 pr_debug("PCI:%s %016llx-%016llx\n", 1076 pci_name(dev), 1077 (unsigned long long)res->start, 1078 (unsigned long long)res->end); 1079 } 1080 } 1081 } 1082 1083 void __devinit pcibios_setup_bus_self(struct pci_bus *bus) 1084 { 1085 /* Fix up the bus resources for P2P bridges */ 1086 if (bus->self != NULL) 1087 pcibios_fixup_bridge(bus); 1088 1089 /* Platform specific bus fixups. This is currently only used 1090 * by fsl_pci and I'm hoping to get rid of it at some point 1091 */ 1092 if (ppc_md.pcibios_fixup_bus) 1093 ppc_md.pcibios_fixup_bus(bus); 1094 1095 /* Setup bus DMA mappings */ 1096 if (ppc_md.pci_dma_bus_setup) 1097 ppc_md.pci_dma_bus_setup(bus); 1098 } 1099 1100 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) 1101 { 1102 struct pci_dev *dev; 1103 1104 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1105 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1106 1107 list_for_each_entry(dev, &bus->devices, bus_list) { 1108 struct dev_archdata *sd = &dev->dev.archdata; 1109 1110 /* Setup OF node pointer in archdata */ 1111 sd->of_node = pci_device_to_OF_node(dev); 1112 1113 /* Fixup NUMA node as it may not be setup yet by the generic 1114 * code and is needed by the DMA init 1115 */ 1116 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1117 1118 /* Hook up default DMA ops */ 1119 sd->dma_ops = pci_dma_ops; 1120 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1121 1122 /* Additional platform DMA/iommu setup */ 1123 if (ppc_md.pci_dma_dev_setup) 1124 ppc_md.pci_dma_dev_setup(dev); 1125 1126 /* Read default IRQs and fixup if necessary */ 1127 pci_read_irq_line(dev); 1128 if (ppc_md.pci_irq_fixup) 1129 ppc_md.pci_irq_fixup(dev); 1130 } 1131 } 1132 1133 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 1134 { 1135 /* When called from the generic PCI probe, read PCI<->PCI bridge 1136 * bases. This is -not- called when generating the PCI tree from 1137 * the OF device-tree. 1138 */ 1139 if (bus->self != NULL) 1140 pci_read_bridge_bases(bus); 1141 1142 /* Now fixup the bus bus */ 1143 pcibios_setup_bus_self(bus); 1144 1145 /* Now fixup devices on that bus */ 1146 pcibios_setup_bus_devices(bus); 1147 } 1148 EXPORT_SYMBOL(pcibios_fixup_bus); 1149 1150 static int skip_isa_ioresource_align(struct pci_dev *dev) 1151 { 1152 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && 1153 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1154 return 1; 1155 return 0; 1156 } 1157 1158 /* 1159 * We need to avoid collisions with `mirrored' VGA ports 1160 * and other strange ISA hardware, so we always want the 1161 * addresses to be allocated in the 0x000-0x0ff region 1162 * modulo 0x400. 1163 * 1164 * Why? Because some silly external IO cards only decode 1165 * the low 10 bits of the IO address. The 0x00-0xff region 1166 * is reserved for motherboard devices that decode all 16 1167 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1168 * but we want to try to avoid allocating at 0x2900-0x2bff 1169 * which might have be mirrored at 0x0100-0x03ff.. 1170 */ 1171 void pcibios_align_resource(void *data, struct resource *res, 1172 resource_size_t size, resource_size_t align) 1173 { 1174 struct pci_dev *dev = data; 1175 1176 if (res->flags & IORESOURCE_IO) { 1177 resource_size_t start = res->start; 1178 1179 if (skip_isa_ioresource_align(dev)) 1180 return; 1181 if (start & 0x300) { 1182 start = (start + 0x3ff) & ~0x3ff; 1183 res->start = start; 1184 } 1185 } 1186 } 1187 EXPORT_SYMBOL(pcibios_align_resource); 1188 1189 /* 1190 * Reparent resource children of pr that conflict with res 1191 * under res, and make res replace those children. 1192 */ 1193 static int __init reparent_resources(struct resource *parent, 1194 struct resource *res) 1195 { 1196 struct resource *p, **pp; 1197 struct resource **firstpp = NULL; 1198 1199 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1200 if (p->end < res->start) 1201 continue; 1202 if (res->end < p->start) 1203 break; 1204 if (p->start < res->start || p->end > res->end) 1205 return -1; /* not completely contained */ 1206 if (firstpp == NULL) 1207 firstpp = pp; 1208 } 1209 if (firstpp == NULL) 1210 return -1; /* didn't find any conflicting entries? */ 1211 res->parent = parent; 1212 res->child = *firstpp; 1213 res->sibling = *pp; 1214 *firstpp = res; 1215 *pp = NULL; 1216 for (p = res->child; p != NULL; p = p->sibling) { 1217 p->parent = res; 1218 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1219 p->name, 1220 (unsigned long long)p->start, 1221 (unsigned long long)p->end, res->name); 1222 } 1223 return 0; 1224 } 1225 1226 /* 1227 * Handle resources of PCI devices. If the world were perfect, we could 1228 * just allocate all the resource regions and do nothing more. It isn't. 1229 * On the other hand, we cannot just re-allocate all devices, as it would 1230 * require us to know lots of host bridge internals. So we attempt to 1231 * keep as much of the original configuration as possible, but tweak it 1232 * when it's found to be wrong. 1233 * 1234 * Known BIOS problems we have to work around: 1235 * - I/O or memory regions not configured 1236 * - regions configured, but not enabled in the command register 1237 * - bogus I/O addresses above 64K used 1238 * - expansion ROMs left enabled (this may sound harmless, but given 1239 * the fact the PCI specs explicitly allow address decoders to be 1240 * shared between expansion ROMs and other resource regions, it's 1241 * at least dangerous) 1242 * 1243 * Our solution: 1244 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1245 * This gives us fixed barriers on where we can allocate. 1246 * (2) Allocate resources for all enabled devices. If there is 1247 * a collision, just mark the resource as unallocated. Also 1248 * disable expansion ROMs during this step. 1249 * (3) Try to allocate resources for disabled devices. If the 1250 * resources were assigned correctly, everything goes well, 1251 * if they weren't, they won't disturb allocation of other 1252 * resources. 1253 * (4) Assign new addresses to resources which were either 1254 * not configured at all or misconfigured. If explicitly 1255 * requested by the user, configure expansion ROM address 1256 * as well. 1257 */ 1258 1259 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1260 { 1261 struct pci_bus *b; 1262 int i; 1263 struct resource *res, *pr; 1264 1265 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1266 pci_domain_nr(bus), bus->number); 1267 1268 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 1269 if ((res = bus->resource[i]) == NULL || !res->flags 1270 || res->start > res->end || res->parent) 1271 continue; 1272 if (bus->parent == NULL) 1273 pr = (res->flags & IORESOURCE_IO) ? 1274 &ioport_resource : &iomem_resource; 1275 else { 1276 /* Don't bother with non-root busses when 1277 * re-assigning all resources. We clear the 1278 * resource flags as if they were colliding 1279 * and as such ensure proper re-allocation 1280 * later. 1281 */ 1282 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) 1283 goto clear_resource; 1284 pr = pci_find_parent_resource(bus->self, res); 1285 if (pr == res) { 1286 /* this happens when the generic PCI 1287 * code (wrongly) decides that this 1288 * bridge is transparent -- paulus 1289 */ 1290 continue; 1291 } 1292 } 1293 1294 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1295 "[0x%x], parent %p (%s)\n", 1296 bus->self ? pci_name(bus->self) : "PHB", 1297 bus->number, i, 1298 (unsigned long long)res->start, 1299 (unsigned long long)res->end, 1300 (unsigned int)res->flags, 1301 pr, (pr && pr->name) ? pr->name : "nil"); 1302 1303 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1304 if (request_resource(pr, res) == 0) 1305 continue; 1306 /* 1307 * Must be a conflict with an existing entry. 1308 * Move that entry (or entries) under the 1309 * bridge resource and try again. 1310 */ 1311 if (reparent_resources(pr, res) == 0) 1312 continue; 1313 } 1314 printk(KERN_WARNING "PCI: Cannot allocate resource region " 1315 "%d of PCI bridge %d, will remap\n", i, bus->number); 1316 clear_resource: 1317 res->flags = 0; 1318 } 1319 1320 list_for_each_entry(b, &bus->children, node) 1321 pcibios_allocate_bus_resources(b); 1322 } 1323 1324 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) 1325 { 1326 struct resource *pr, *r = &dev->resource[idx]; 1327 1328 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1329 pci_name(dev), idx, 1330 (unsigned long long)r->start, 1331 (unsigned long long)r->end, 1332 (unsigned int)r->flags); 1333 1334 pr = pci_find_parent_resource(dev, r); 1335 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1336 request_resource(pr, r) < 0) { 1337 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1338 " of device %s, will remap\n", idx, pci_name(dev)); 1339 if (pr) 1340 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1341 pr, 1342 (unsigned long long)pr->start, 1343 (unsigned long long)pr->end, 1344 (unsigned int)pr->flags); 1345 /* We'll assign a new address later */ 1346 r->flags |= IORESOURCE_UNSET; 1347 r->end -= r->start; 1348 r->start = 0; 1349 } 1350 } 1351 1352 static void __init pcibios_allocate_resources(int pass) 1353 { 1354 struct pci_dev *dev = NULL; 1355 int idx, disabled; 1356 u16 command; 1357 struct resource *r; 1358 1359 for_each_pci_dev(dev) { 1360 pci_read_config_word(dev, PCI_COMMAND, &command); 1361 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1362 r = &dev->resource[idx]; 1363 if (r->parent) /* Already allocated */ 1364 continue; 1365 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1366 continue; /* Not assigned at all */ 1367 /* We only allocate ROMs on pass 1 just in case they 1368 * have been screwed up by firmware 1369 */ 1370 if (idx == PCI_ROM_RESOURCE ) 1371 disabled = 1; 1372 if (r->flags & IORESOURCE_IO) 1373 disabled = !(command & PCI_COMMAND_IO); 1374 else 1375 disabled = !(command & PCI_COMMAND_MEMORY); 1376 if (pass == disabled) 1377 alloc_resource(dev, idx); 1378 } 1379 if (pass) 1380 continue; 1381 r = &dev->resource[PCI_ROM_RESOURCE]; 1382 if (r->flags) { 1383 /* Turn the ROM off, leave the resource region, 1384 * but keep it unregistered. 1385 */ 1386 u32 reg; 1387 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1388 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1389 pr_debug("PCI: Switching off ROM of %s\n", 1390 pci_name(dev)); 1391 r->flags &= ~IORESOURCE_ROM_ENABLE; 1392 pci_write_config_dword(dev, dev->rom_base_reg, 1393 reg & ~PCI_ROM_ADDRESS_ENABLE); 1394 } 1395 } 1396 } 1397 } 1398 1399 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1400 { 1401 struct pci_controller *hose = pci_bus_to_host(bus); 1402 resource_size_t offset; 1403 struct resource *res, *pres; 1404 int i; 1405 1406 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1407 1408 /* Check for IO */ 1409 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1410 goto no_io; 1411 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1412 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1413 BUG_ON(res == NULL); 1414 res->name = "Legacy IO"; 1415 res->flags = IORESOURCE_IO; 1416 res->start = offset; 1417 res->end = (offset + 0xfff) & 0xfffffffful; 1418 pr_debug("Candidate legacy IO: %pR\n", res); 1419 if (request_resource(&hose->io_resource, res)) { 1420 printk(KERN_DEBUG 1421 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1422 pci_domain_nr(bus), bus->number, res); 1423 kfree(res); 1424 } 1425 1426 no_io: 1427 /* Check for memory */ 1428 offset = hose->pci_mem_offset; 1429 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); 1430 for (i = 0; i < 3; i++) { 1431 pres = &hose->mem_resources[i]; 1432 if (!(pres->flags & IORESOURCE_MEM)) 1433 continue; 1434 pr_debug("hose mem res: %pR\n", pres); 1435 if ((pres->start - offset) <= 0xa0000 && 1436 (pres->end - offset) >= 0xbffff) 1437 break; 1438 } 1439 if (i >= 3) 1440 return; 1441 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1442 BUG_ON(res == NULL); 1443 res->name = "Legacy VGA memory"; 1444 res->flags = IORESOURCE_MEM; 1445 res->start = 0xa0000 + offset; 1446 res->end = 0xbffff + offset; 1447 pr_debug("Candidate VGA memory: %pR\n", res); 1448 if (request_resource(pres, res)) { 1449 printk(KERN_DEBUG 1450 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1451 pci_domain_nr(bus), bus->number, res); 1452 kfree(res); 1453 } 1454 } 1455 1456 void __init pcibios_resource_survey(void) 1457 { 1458 struct pci_bus *b; 1459 1460 /* Allocate and assign resources. If we re-assign everything, then 1461 * we skip the allocate phase 1462 */ 1463 list_for_each_entry(b, &pci_root_buses, node) 1464 pcibios_allocate_bus_resources(b); 1465 1466 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { 1467 pcibios_allocate_resources(0); 1468 pcibios_allocate_resources(1); 1469 } 1470 1471 /* Before we start assigning unassigned resource, we try to reserve 1472 * the low IO area and the VGA memory area if they intersect the 1473 * bus available resources to avoid allocating things on top of them 1474 */ 1475 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1476 list_for_each_entry(b, &pci_root_buses, node) 1477 pcibios_reserve_legacy_regions(b); 1478 } 1479 1480 /* Now, if the platform didn't decide to blindly trust the firmware, 1481 * we proceed to assigning things that were left unassigned 1482 */ 1483 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1484 pr_debug("PCI: Assigning unassigned resources...\n"); 1485 pci_assign_unassigned_resources(); 1486 } 1487 1488 /* Call machine dependent fixup */ 1489 if (ppc_md.pcibios_fixup) 1490 ppc_md.pcibios_fixup(); 1491 } 1492 1493 #ifdef CONFIG_HOTPLUG 1494 1495 /* This is used by the PCI hotplug driver to allocate resource 1496 * of newly plugged busses. We can try to consolidate with the 1497 * rest of the code later, for now, keep it as-is as our main 1498 * resource allocation function doesn't deal with sub-trees yet. 1499 */ 1500 void pcibios_claim_one_bus(struct pci_bus *bus) 1501 { 1502 struct pci_dev *dev; 1503 struct pci_bus *child_bus; 1504 1505 list_for_each_entry(dev, &bus->devices, bus_list) { 1506 int i; 1507 1508 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1509 struct resource *r = &dev->resource[i]; 1510 1511 if (r->parent || !r->start || !r->flags) 1512 continue; 1513 1514 pr_debug("PCI: Claiming %s: " 1515 "Resource %d: %016llx..%016llx [%x]\n", 1516 pci_name(dev), i, 1517 (unsigned long long)r->start, 1518 (unsigned long long)r->end, 1519 (unsigned int)r->flags); 1520 1521 pci_claim_resource(dev, i); 1522 } 1523 } 1524 1525 list_for_each_entry(child_bus, &bus->children, node) 1526 pcibios_claim_one_bus(child_bus); 1527 } 1528 1529 1530 /* pcibios_finish_adding_to_bus 1531 * 1532 * This is to be called by the hotplug code after devices have been 1533 * added to a bus, this include calling it for a PHB that is just 1534 * being added 1535 */ 1536 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1537 { 1538 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1539 pci_domain_nr(bus), bus->number); 1540 1541 /* Allocate bus and devices resources */ 1542 pcibios_allocate_bus_resources(bus); 1543 pcibios_claim_one_bus(bus); 1544 1545 /* Add new devices to global lists. Register in proc, sysfs. */ 1546 pci_bus_add_devices(bus); 1547 1548 /* Fixup EEH */ 1549 eeh_add_device_tree_late(bus); 1550 } 1551 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1552 1553 #endif /* CONFIG_HOTPLUG */ 1554 1555 int pcibios_enable_device(struct pci_dev *dev, int mask) 1556 { 1557 if (ppc_md.pcibios_enable_device_hook) 1558 if (ppc_md.pcibios_enable_device_hook(dev)) 1559 return -EINVAL; 1560 1561 return pci_enable_resources(dev, mask); 1562 } 1563 1564 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) 1565 { 1566 struct pci_bus *bus = hose->bus; 1567 struct resource *res; 1568 int i; 1569 1570 /* Hookup PHB IO resource */ 1571 bus->resource[0] = res = &hose->io_resource; 1572 1573 if (!res->flags) { 1574 printk(KERN_WARNING "PCI: I/O resource not set for host" 1575 " bridge %s (domain %d)\n", 1576 hose->dn->full_name, hose->global_number); 1577 #ifdef CONFIG_PPC32 1578 /* Workaround for lack of IO resource only on 32-bit */ 1579 res->start = (unsigned long)hose->io_base_virt - isa_io_base; 1580 res->end = res->start + IO_SPACE_LIMIT; 1581 res->flags = IORESOURCE_IO; 1582 #endif /* CONFIG_PPC32 */ 1583 } 1584 1585 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1586 (unsigned long long)res->start, 1587 (unsigned long long)res->end, 1588 (unsigned long)res->flags); 1589 1590 /* Hookup PHB Memory resources */ 1591 for (i = 0; i < 3; ++i) { 1592 res = &hose->mem_resources[i]; 1593 if (!res->flags) { 1594 if (i > 0) 1595 continue; 1596 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1597 "host bridge %s (domain %d)\n", 1598 hose->dn->full_name, hose->global_number); 1599 #ifdef CONFIG_PPC32 1600 /* Workaround for lack of MEM resource only on 32-bit */ 1601 res->start = hose->pci_mem_offset; 1602 res->end = (resource_size_t)-1LL; 1603 res->flags = IORESOURCE_MEM; 1604 #endif /* CONFIG_PPC32 */ 1605 } 1606 bus->resource[i+1] = res; 1607 1608 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1609 (unsigned long long)res->start, 1610 (unsigned long long)res->end, 1611 (unsigned long)res->flags); 1612 } 1613 1614 pr_debug("PCI: PHB MEM offset = %016llx\n", 1615 (unsigned long long)hose->pci_mem_offset); 1616 pr_debug("PCI: PHB IO offset = %08lx\n", 1617 (unsigned long)hose->io_base_virt - _IO_BASE); 1618 1619 } 1620 1621 /* 1622 * Null PCI config access functions, for the case when we can't 1623 * find a hose. 1624 */ 1625 #define NULL_PCI_OP(rw, size, type) \ 1626 static int \ 1627 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1628 { \ 1629 return PCIBIOS_DEVICE_NOT_FOUND; \ 1630 } 1631 1632 static int 1633 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1634 int len, u32 *val) 1635 { 1636 return PCIBIOS_DEVICE_NOT_FOUND; 1637 } 1638 1639 static int 1640 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1641 int len, u32 val) 1642 { 1643 return PCIBIOS_DEVICE_NOT_FOUND; 1644 } 1645 1646 static struct pci_ops null_pci_ops = 1647 { 1648 .read = null_read_config, 1649 .write = null_write_config, 1650 }; 1651 1652 /* 1653 * These functions are used early on before PCI scanning is done 1654 * and all of the pci_dev and pci_bus structures have been created. 1655 */ 1656 static struct pci_bus * 1657 fake_pci_bus(struct pci_controller *hose, int busnr) 1658 { 1659 static struct pci_bus bus; 1660 1661 if (hose == 0) { 1662 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1663 } 1664 bus.number = busnr; 1665 bus.sysdata = hose; 1666 bus.ops = hose? hose->ops: &null_pci_ops; 1667 return &bus; 1668 } 1669 1670 #define EARLY_PCI_OP(rw, size, type) \ 1671 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1672 int devfn, int offset, type value) \ 1673 { \ 1674 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1675 devfn, offset, value); \ 1676 } 1677 1678 EARLY_PCI_OP(read, byte, u8 *) 1679 EARLY_PCI_OP(read, word, u16 *) 1680 EARLY_PCI_OP(read, dword, u32 *) 1681 EARLY_PCI_OP(write, byte, u8) 1682 EARLY_PCI_OP(write, word, u16) 1683 EARLY_PCI_OP(write, dword, u32) 1684 1685 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1686 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1687 int cap) 1688 { 1689 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1690 } 1691 1692 /** 1693 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1694 * @hose: Pointer to the PCI host controller instance structure 1695 * @sysdata: value to use for sysdata pointer. ppc32 and ppc64 differ here 1696 * 1697 * Note: the 'data' pointer is a temporary measure. As 32 and 64 bit 1698 * pci code gets merged, this parameter should become unnecessary because 1699 * both will use the same value. 1700 */ 1701 void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata) 1702 { 1703 struct pci_bus *bus; 1704 struct device_node *node = hose->dn; 1705 int mode; 1706 1707 pr_debug("PCI: Scanning PHB %s\n", 1708 node ? node->full_name : "<NO NAME>"); 1709 1710 /* Create an empty bus for the toplevel */ 1711 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, 1712 sysdata); 1713 if (bus == NULL) { 1714 pr_err("Failed to create bus for PCI domain %04x\n", 1715 hose->global_number); 1716 return; 1717 } 1718 bus->secondary = hose->first_busno; 1719 hose->bus = bus; 1720 1721 /* Get some IO space for the new PHB */ 1722 pcibios_setup_phb_io_space(hose); 1723 1724 /* Wire up PHB bus resources */ 1725 pcibios_setup_phb_resources(hose); 1726 1727 /* Get probe mode and perform scan */ 1728 mode = PCI_PROBE_NORMAL; 1729 if (node && ppc_md.pci_probe_mode) 1730 mode = ppc_md.pci_probe_mode(bus); 1731 pr_debug(" probe mode: %d\n", mode); 1732 if (mode == PCI_PROBE_DEVTREE) { 1733 bus->subordinate = hose->last_busno; 1734 of_scan_bus(node, bus); 1735 } 1736 1737 if (mode == PCI_PROBE_NORMAL) 1738 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 1739 } 1740