xref: /openbmc/linux/arch/powerpc/kernel/pci-common.c (revision c819e2cf)
1 /*
2  * Contains common pci routines for ALL ppc platform
3  * (based on pci_32.c and pci_64.c)
4  *
5  * Port for PPC64 David Engebretsen, IBM Corp.
6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7  *
8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9  *   Rework, based on alpha PCI code.
10  *
11  * Common pmac/prep/chrp pci routines. -- Cort
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version
16  * 2 of the License, or (at your option) any later version.
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
27 #include <linux/mm.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 
35 #include <asm/processor.h>
36 #include <asm/io.h>
37 #include <asm/prom.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
42 #include <asm/eeh.h>
43 
44 static DEFINE_SPINLOCK(hose_spinlock);
45 LIST_HEAD(hose_list);
46 
47 /* XXX kill that some day ... */
48 static int global_phb_number;		/* Global phb counter */
49 
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
52 
53 
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
55 
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
57 {
58 	pci_dma_ops = dma_ops;
59 }
60 
61 struct dma_map_ops *get_pci_dma_ops(void)
62 {
63 	return pci_dma_ops;
64 }
65 EXPORT_SYMBOL(get_pci_dma_ops);
66 
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
68 {
69 	struct pci_controller *phb;
70 
71 	phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
72 	if (phb == NULL)
73 		return NULL;
74 	spin_lock(&hose_spinlock);
75 	phb->global_number = global_phb_number++;
76 	list_add_tail(&phb->list_node, &hose_list);
77 	spin_unlock(&hose_spinlock);
78 	phb->dn = dev;
79 	phb->is_dynamic = mem_init_done;
80 #ifdef CONFIG_PPC64
81 	if (dev) {
82 		int nid = of_node_to_nid(dev);
83 
84 		if (nid < 0 || !node_online(nid))
85 			nid = -1;
86 
87 		PHB_SET_NODE(phb, nid);
88 	}
89 #endif
90 	return phb;
91 }
92 
93 void pcibios_free_controller(struct pci_controller *phb)
94 {
95 	spin_lock(&hose_spinlock);
96 	list_del(&phb->list_node);
97 	spin_unlock(&hose_spinlock);
98 
99 	if (phb->is_dynamic)
100 		kfree(phb);
101 }
102 
103 /*
104  * The function is used to return the minimal alignment
105  * for memory or I/O windows of the associated P2P bridge.
106  * By default, 4KiB alignment for I/O windows and 1MiB for
107  * memory windows.
108  */
109 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
110 					 unsigned long type)
111 {
112 	if (ppc_md.pcibios_window_alignment)
113 		return ppc_md.pcibios_window_alignment(bus, type);
114 
115 	/*
116 	 * PCI core will figure out the default
117 	 * alignment: 4KiB for I/O and 1MiB for
118 	 * memory window.
119 	 */
120 	return 1;
121 }
122 
123 void pcibios_reset_secondary_bus(struct pci_dev *dev)
124 {
125 	if (ppc_md.pcibios_reset_secondary_bus) {
126 		ppc_md.pcibios_reset_secondary_bus(dev);
127 		return;
128 	}
129 
130 	pci_reset_secondary_bus(dev);
131 }
132 
133 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
134 {
135 #ifdef CONFIG_PPC64
136 	return hose->pci_io_size;
137 #else
138 	return resource_size(&hose->io_resource);
139 #endif
140 }
141 
142 int pcibios_vaddr_is_ioport(void __iomem *address)
143 {
144 	int ret = 0;
145 	struct pci_controller *hose;
146 	resource_size_t size;
147 
148 	spin_lock(&hose_spinlock);
149 	list_for_each_entry(hose, &hose_list, list_node) {
150 		size = pcibios_io_size(hose);
151 		if (address >= hose->io_base_virt &&
152 		    address < (hose->io_base_virt + size)) {
153 			ret = 1;
154 			break;
155 		}
156 	}
157 	spin_unlock(&hose_spinlock);
158 	return ret;
159 }
160 
161 unsigned long pci_address_to_pio(phys_addr_t address)
162 {
163 	struct pci_controller *hose;
164 	resource_size_t size;
165 	unsigned long ret = ~0;
166 
167 	spin_lock(&hose_spinlock);
168 	list_for_each_entry(hose, &hose_list, list_node) {
169 		size = pcibios_io_size(hose);
170 		if (address >= hose->io_base_phys &&
171 		    address < (hose->io_base_phys + size)) {
172 			unsigned long base =
173 				(unsigned long)hose->io_base_virt - _IO_BASE;
174 			ret = base + (address - hose->io_base_phys);
175 			break;
176 		}
177 	}
178 	spin_unlock(&hose_spinlock);
179 
180 	return ret;
181 }
182 EXPORT_SYMBOL_GPL(pci_address_to_pio);
183 
184 /*
185  * Return the domain number for this bus.
186  */
187 int pci_domain_nr(struct pci_bus *bus)
188 {
189 	struct pci_controller *hose = pci_bus_to_host(bus);
190 
191 	return hose->global_number;
192 }
193 EXPORT_SYMBOL(pci_domain_nr);
194 
195 /* This routine is meant to be used early during boot, when the
196  * PCI bus numbers have not yet been assigned, and you need to
197  * issue PCI config cycles to an OF device.
198  * It could also be used to "fix" RTAS config cycles if you want
199  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
200  * config cycles.
201  */
202 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
203 {
204 	while(node) {
205 		struct pci_controller *hose, *tmp;
206 		list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
207 			if (hose->dn == node)
208 				return hose;
209 		node = node->parent;
210 	}
211 	return NULL;
212 }
213 
214 /*
215  * Reads the interrupt pin to determine if interrupt is use by card.
216  * If the interrupt is used, then gets the interrupt line from the
217  * openfirmware and sets it in the pci_dev and pci_config line.
218  */
219 static int pci_read_irq_line(struct pci_dev *pci_dev)
220 {
221 	struct of_phandle_args oirq;
222 	unsigned int virq;
223 
224 	pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
225 
226 #ifdef DEBUG
227 	memset(&oirq, 0xff, sizeof(oirq));
228 #endif
229 	/* Try to get a mapping from the device-tree */
230 	if (of_irq_parse_pci(pci_dev, &oirq)) {
231 		u8 line, pin;
232 
233 		/* If that fails, lets fallback to what is in the config
234 		 * space and map that through the default controller. We
235 		 * also set the type to level low since that's what PCI
236 		 * interrupts are. If your platform does differently, then
237 		 * either provide a proper interrupt tree or don't use this
238 		 * function.
239 		 */
240 		if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
241 			return -1;
242 		if (pin == 0)
243 			return -1;
244 		if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
245 		    line == 0xff || line == 0) {
246 			return -1;
247 		}
248 		pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
249 			 line, pin);
250 
251 		virq = irq_create_mapping(NULL, line);
252 		if (virq != NO_IRQ)
253 			irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
254 	} else {
255 		pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
256 			 oirq.args_count, oirq.args[0], oirq.args[1],
257 			 of_node_full_name(oirq.np));
258 
259 		virq = irq_create_of_mapping(&oirq);
260 	}
261 	if(virq == NO_IRQ) {
262 		pr_debug(" Failed to map !\n");
263 		return -1;
264 	}
265 
266 	pr_debug(" Mapped to linux irq %d\n", virq);
267 
268 	pci_dev->irq = virq;
269 
270 	return 0;
271 }
272 
273 /*
274  * Platform support for /proc/bus/pci/X/Y mmap()s,
275  * modelled on the sparc64 implementation by Dave Miller.
276  *  -- paulus.
277  */
278 
279 /*
280  * Adjust vm_pgoff of VMA such that it is the physical page offset
281  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
282  *
283  * Basically, the user finds the base address for his device which he wishes
284  * to mmap.  They read the 32-bit value from the config space base register,
285  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
286  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
287  *
288  * Returns negative error code on failure, zero on success.
289  */
290 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
291 					       resource_size_t *offset,
292 					       enum pci_mmap_state mmap_state)
293 {
294 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
295 	unsigned long io_offset = 0;
296 	int i, res_bit;
297 
298 	if (hose == NULL)
299 		return NULL;		/* should never happen */
300 
301 	/* If memory, add on the PCI bridge address offset */
302 	if (mmap_state == pci_mmap_mem) {
303 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
304 		*offset += hose->pci_mem_offset;
305 #endif
306 		res_bit = IORESOURCE_MEM;
307 	} else {
308 		io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
309 		*offset += io_offset;
310 		res_bit = IORESOURCE_IO;
311 	}
312 
313 	/*
314 	 * Check that the offset requested corresponds to one of the
315 	 * resources of the device.
316 	 */
317 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
318 		struct resource *rp = &dev->resource[i];
319 		int flags = rp->flags;
320 
321 		/* treat ROM as memory (should be already) */
322 		if (i == PCI_ROM_RESOURCE)
323 			flags |= IORESOURCE_MEM;
324 
325 		/* Active and same type? */
326 		if ((flags & res_bit) == 0)
327 			continue;
328 
329 		/* In the range of this resource? */
330 		if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
331 			continue;
332 
333 		/* found it! construct the final physical address */
334 		if (mmap_state == pci_mmap_io)
335 			*offset += hose->io_base_phys - io_offset;
336 		return rp;
337 	}
338 
339 	return NULL;
340 }
341 
342 /*
343  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
344  * device mapping.
345  */
346 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
347 				      pgprot_t protection,
348 				      enum pci_mmap_state mmap_state,
349 				      int write_combine)
350 {
351 
352 	/* Write combine is always 0 on non-memory space mappings. On
353 	 * memory space, if the user didn't pass 1, we check for a
354 	 * "prefetchable" resource. This is a bit hackish, but we use
355 	 * this to workaround the inability of /sysfs to provide a write
356 	 * combine bit
357 	 */
358 	if (mmap_state != pci_mmap_mem)
359 		write_combine = 0;
360 	else if (write_combine == 0) {
361 		if (rp->flags & IORESOURCE_PREFETCH)
362 			write_combine = 1;
363 	}
364 
365 	/* XXX would be nice to have a way to ask for write-through */
366 	if (write_combine)
367 		return pgprot_noncached_wc(protection);
368 	else
369 		return pgprot_noncached(protection);
370 }
371 
372 /*
373  * This one is used by /dev/mem and fbdev who have no clue about the
374  * PCI device, it tries to find the PCI device first and calls the
375  * above routine
376  */
377 pgprot_t pci_phys_mem_access_prot(struct file *file,
378 				  unsigned long pfn,
379 				  unsigned long size,
380 				  pgprot_t prot)
381 {
382 	struct pci_dev *pdev = NULL;
383 	struct resource *found = NULL;
384 	resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
385 	int i;
386 
387 	if (page_is_ram(pfn))
388 		return prot;
389 
390 	prot = pgprot_noncached(prot);
391 	for_each_pci_dev(pdev) {
392 		for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
393 			struct resource *rp = &pdev->resource[i];
394 			int flags = rp->flags;
395 
396 			/* Active and same type? */
397 			if ((flags & IORESOURCE_MEM) == 0)
398 				continue;
399 			/* In the range of this resource? */
400 			if (offset < (rp->start & PAGE_MASK) ||
401 			    offset > rp->end)
402 				continue;
403 			found = rp;
404 			break;
405 		}
406 		if (found)
407 			break;
408 	}
409 	if (found) {
410 		if (found->flags & IORESOURCE_PREFETCH)
411 			prot = pgprot_noncached_wc(prot);
412 		pci_dev_put(pdev);
413 	}
414 
415 	pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
416 		 (unsigned long long)offset, pgprot_val(prot));
417 
418 	return prot;
419 }
420 
421 
422 /*
423  * Perform the actual remap of the pages for a PCI device mapping, as
424  * appropriate for this architecture.  The region in the process to map
425  * is described by vm_start and vm_end members of VMA, the base physical
426  * address is found in vm_pgoff.
427  * The pci device structure is provided so that architectures may make mapping
428  * decisions on a per-device or per-bus basis.
429  *
430  * Returns a negative error code on failure, zero on success.
431  */
432 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
433 			enum pci_mmap_state mmap_state, int write_combine)
434 {
435 	resource_size_t offset =
436 		((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
437 	struct resource *rp;
438 	int ret;
439 
440 	rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
441 	if (rp == NULL)
442 		return -EINVAL;
443 
444 	vma->vm_pgoff = offset >> PAGE_SHIFT;
445 	vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
446 						  vma->vm_page_prot,
447 						  mmap_state, write_combine);
448 
449 	ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
450 			       vma->vm_end - vma->vm_start, vma->vm_page_prot);
451 
452 	return ret;
453 }
454 
455 /* This provides legacy IO read access on a bus */
456 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
457 {
458 	unsigned long offset;
459 	struct pci_controller *hose = pci_bus_to_host(bus);
460 	struct resource *rp = &hose->io_resource;
461 	void __iomem *addr;
462 
463 	/* Check if port can be supported by that bus. We only check
464 	 * the ranges of the PHB though, not the bus itself as the rules
465 	 * for forwarding legacy cycles down bridges are not our problem
466 	 * here. So if the host bridge supports it, we do it.
467 	 */
468 	offset = (unsigned long)hose->io_base_virt - _IO_BASE;
469 	offset += port;
470 
471 	if (!(rp->flags & IORESOURCE_IO))
472 		return -ENXIO;
473 	if (offset < rp->start || (offset + size) > rp->end)
474 		return -ENXIO;
475 	addr = hose->io_base_virt + port;
476 
477 	switch(size) {
478 	case 1:
479 		*((u8 *)val) = in_8(addr);
480 		return 1;
481 	case 2:
482 		if (port & 1)
483 			return -EINVAL;
484 		*((u16 *)val) = in_le16(addr);
485 		return 2;
486 	case 4:
487 		if (port & 3)
488 			return -EINVAL;
489 		*((u32 *)val) = in_le32(addr);
490 		return 4;
491 	}
492 	return -EINVAL;
493 }
494 
495 /* This provides legacy IO write access on a bus */
496 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
497 {
498 	unsigned long offset;
499 	struct pci_controller *hose = pci_bus_to_host(bus);
500 	struct resource *rp = &hose->io_resource;
501 	void __iomem *addr;
502 
503 	/* Check if port can be supported by that bus. We only check
504 	 * the ranges of the PHB though, not the bus itself as the rules
505 	 * for forwarding legacy cycles down bridges are not our problem
506 	 * here. So if the host bridge supports it, we do it.
507 	 */
508 	offset = (unsigned long)hose->io_base_virt - _IO_BASE;
509 	offset += port;
510 
511 	if (!(rp->flags & IORESOURCE_IO))
512 		return -ENXIO;
513 	if (offset < rp->start || (offset + size) > rp->end)
514 		return -ENXIO;
515 	addr = hose->io_base_virt + port;
516 
517 	/* WARNING: The generic code is idiotic. It gets passed a pointer
518 	 * to what can be a 1, 2 or 4 byte quantity and always reads that
519 	 * as a u32, which means that we have to correct the location of
520 	 * the data read within those 32 bits for size 1 and 2
521 	 */
522 	switch(size) {
523 	case 1:
524 		out_8(addr, val >> 24);
525 		return 1;
526 	case 2:
527 		if (port & 1)
528 			return -EINVAL;
529 		out_le16(addr, val >> 16);
530 		return 2;
531 	case 4:
532 		if (port & 3)
533 			return -EINVAL;
534 		out_le32(addr, val);
535 		return 4;
536 	}
537 	return -EINVAL;
538 }
539 
540 /* This provides legacy IO or memory mmap access on a bus */
541 int pci_mmap_legacy_page_range(struct pci_bus *bus,
542 			       struct vm_area_struct *vma,
543 			       enum pci_mmap_state mmap_state)
544 {
545 	struct pci_controller *hose = pci_bus_to_host(bus);
546 	resource_size_t offset =
547 		((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
548 	resource_size_t size = vma->vm_end - vma->vm_start;
549 	struct resource *rp;
550 
551 	pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
552 		 pci_domain_nr(bus), bus->number,
553 		 mmap_state == pci_mmap_mem ? "MEM" : "IO",
554 		 (unsigned long long)offset,
555 		 (unsigned long long)(offset + size - 1));
556 
557 	if (mmap_state == pci_mmap_mem) {
558 		/* Hack alert !
559 		 *
560 		 * Because X is lame and can fail starting if it gets an error trying
561 		 * to mmap legacy_mem (instead of just moving on without legacy memory
562 		 * access) we fake it here by giving it anonymous memory, effectively
563 		 * behaving just like /dev/zero
564 		 */
565 		if ((offset + size) > hose->isa_mem_size) {
566 			printk(KERN_DEBUG
567 			       "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
568 			       current->comm, current->pid, pci_domain_nr(bus), bus->number);
569 			if (vma->vm_flags & VM_SHARED)
570 				return shmem_zero_setup(vma);
571 			return 0;
572 		}
573 		offset += hose->isa_mem_phys;
574 	} else {
575 		unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
576 		unsigned long roffset = offset + io_offset;
577 		rp = &hose->io_resource;
578 		if (!(rp->flags & IORESOURCE_IO))
579 			return -ENXIO;
580 		if (roffset < rp->start || (roffset + size) > rp->end)
581 			return -ENXIO;
582 		offset += hose->io_base_phys;
583 	}
584 	pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
585 
586 	vma->vm_pgoff = offset >> PAGE_SHIFT;
587 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
588 	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
589 			       vma->vm_end - vma->vm_start,
590 			       vma->vm_page_prot);
591 }
592 
593 void pci_resource_to_user(const struct pci_dev *dev, int bar,
594 			  const struct resource *rsrc,
595 			  resource_size_t *start, resource_size_t *end)
596 {
597 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
598 	resource_size_t offset = 0;
599 
600 	if (hose == NULL)
601 		return;
602 
603 	if (rsrc->flags & IORESOURCE_IO)
604 		offset = (unsigned long)hose->io_base_virt - _IO_BASE;
605 
606 	/* We pass a fully fixed up address to userland for MMIO instead of
607 	 * a BAR value because X is lame and expects to be able to use that
608 	 * to pass to /dev/mem !
609 	 *
610 	 * That means that we'll have potentially 64 bits values where some
611 	 * userland apps only expect 32 (like X itself since it thinks only
612 	 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
613 	 * 32 bits CHRPs :-(
614 	 *
615 	 * Hopefully, the sysfs insterface is immune to that gunk. Once X
616 	 * has been fixed (and the fix spread enough), we can re-enable the
617 	 * 2 lines below and pass down a BAR value to userland. In that case
618 	 * we'll also have to re-enable the matching code in
619 	 * __pci_mmap_make_offset().
620 	 *
621 	 * BenH.
622 	 */
623 #if 0
624 	else if (rsrc->flags & IORESOURCE_MEM)
625 		offset = hose->pci_mem_offset;
626 #endif
627 
628 	*start = rsrc->start - offset;
629 	*end = rsrc->end - offset;
630 }
631 
632 /**
633  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
634  * @hose: newly allocated pci_controller to be setup
635  * @dev: device node of the host bridge
636  * @primary: set if primary bus (32 bits only, soon to be deprecated)
637  *
638  * This function will parse the "ranges" property of a PCI host bridge device
639  * node and setup the resource mapping of a pci controller based on its
640  * content.
641  *
642  * Life would be boring if it wasn't for a few issues that we have to deal
643  * with here:
644  *
645  *   - We can only cope with one IO space range and up to 3 Memory space
646  *     ranges. However, some machines (thanks Apple !) tend to split their
647  *     space into lots of small contiguous ranges. So we have to coalesce.
648  *
649  *   - Some busses have IO space not starting at 0, which causes trouble with
650  *     the way we do our IO resource renumbering. The code somewhat deals with
651  *     it for 64 bits but I would expect problems on 32 bits.
652  *
653  *   - Some 32 bits platforms such as 4xx can have physical space larger than
654  *     32 bits so we need to use 64 bits values for the parsing
655  */
656 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
657 				  struct device_node *dev, int primary)
658 {
659 	int memno = 0;
660 	struct resource *res;
661 	struct of_pci_range range;
662 	struct of_pci_range_parser parser;
663 
664 	printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
665 	       dev->full_name, primary ? "(primary)" : "");
666 
667 	/* Check for ranges property */
668 	if (of_pci_range_parser_init(&parser, dev))
669 		return;
670 
671 	/* Parse it */
672 	for_each_of_pci_range(&parser, &range) {
673 		/* If we failed translation or got a zero-sized region
674 		 * (some FW try to feed us with non sensical zero sized regions
675 		 * such as power3 which look like some kind of attempt at exposing
676 		 * the VGA memory hole)
677 		 */
678 		if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
679 			continue;
680 
681 		/* Act based on address space type */
682 		res = NULL;
683 		switch (range.flags & IORESOURCE_TYPE_BITS) {
684 		case IORESOURCE_IO:
685 			printk(KERN_INFO
686 			       "  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
687 			       range.cpu_addr, range.cpu_addr + range.size - 1,
688 			       range.pci_addr);
689 
690 			/* We support only one IO range */
691 			if (hose->pci_io_size) {
692 				printk(KERN_INFO
693 				       " \\--> Skipped (too many) !\n");
694 				continue;
695 			}
696 #ifdef CONFIG_PPC32
697 			/* On 32 bits, limit I/O space to 16MB */
698 			if (range.size > 0x01000000)
699 				range.size = 0x01000000;
700 
701 			/* 32 bits needs to map IOs here */
702 			hose->io_base_virt = ioremap(range.cpu_addr,
703 						range.size);
704 
705 			/* Expect trouble if pci_addr is not 0 */
706 			if (primary)
707 				isa_io_base =
708 					(unsigned long)hose->io_base_virt;
709 #endif /* CONFIG_PPC32 */
710 			/* pci_io_size and io_base_phys always represent IO
711 			 * space starting at 0 so we factor in pci_addr
712 			 */
713 			hose->pci_io_size = range.pci_addr + range.size;
714 			hose->io_base_phys = range.cpu_addr - range.pci_addr;
715 
716 			/* Build resource */
717 			res = &hose->io_resource;
718 			range.cpu_addr = range.pci_addr;
719 			break;
720 		case IORESOURCE_MEM:
721 			printk(KERN_INFO
722 			       " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
723 			       range.cpu_addr, range.cpu_addr + range.size - 1,
724 			       range.pci_addr,
725 			       (range.pci_space & 0x40000000) ?
726 			       "Prefetch" : "");
727 
728 			/* We support only 3 memory ranges */
729 			if (memno >= 3) {
730 				printk(KERN_INFO
731 				       " \\--> Skipped (too many) !\n");
732 				continue;
733 			}
734 			/* Handles ISA memory hole space here */
735 			if (range.pci_addr == 0) {
736 				if (primary || isa_mem_base == 0)
737 					isa_mem_base = range.cpu_addr;
738 				hose->isa_mem_phys = range.cpu_addr;
739 				hose->isa_mem_size = range.size;
740 			}
741 
742 			/* Build resource */
743 			hose->mem_offset[memno] = range.cpu_addr -
744 							range.pci_addr;
745 			res = &hose->mem_resources[memno++];
746 			break;
747 		}
748 		if (res != NULL) {
749 			res->name = dev->full_name;
750 			res->flags = range.flags;
751 			res->start = range.cpu_addr;
752 			res->end = range.cpu_addr + range.size - 1;
753 			res->parent = res->child = res->sibling = NULL;
754 		}
755 	}
756 }
757 
758 /* Decide whether to display the domain number in /proc */
759 int pci_proc_domain(struct pci_bus *bus)
760 {
761 	struct pci_controller *hose = pci_bus_to_host(bus);
762 
763 	if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
764 		return 0;
765 	if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
766 		return hose->global_number != 0;
767 	return 1;
768 }
769 
770 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
771 {
772 	if (ppc_md.pcibios_root_bridge_prepare)
773 		return ppc_md.pcibios_root_bridge_prepare(bridge);
774 
775 	return 0;
776 }
777 
778 /* This header fixup will do the resource fixup for all devices as they are
779  * probed, but not for bridge ranges
780  */
781 static void pcibios_fixup_resources(struct pci_dev *dev)
782 {
783 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
784 	int i;
785 
786 	if (!hose) {
787 		printk(KERN_ERR "No host bridge for PCI dev %s !\n",
788 		       pci_name(dev));
789 		return;
790 	}
791 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
792 		struct resource *res = dev->resource + i;
793 		struct pci_bus_region reg;
794 		if (!res->flags)
795 			continue;
796 
797 		/* If we're going to re-assign everything, we mark all resources
798 		 * as unset (and 0-base them). In addition, we mark BARs starting
799 		 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
800 		 * since in that case, we don't want to re-assign anything
801 		 */
802 		pcibios_resource_to_bus(dev->bus, &reg, res);
803 		if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
804 		    (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
805 			/* Only print message if not re-assigning */
806 			if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
807 				pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
808 					 "is unassigned\n",
809 					 pci_name(dev), i,
810 					 (unsigned long long)res->start,
811 					 (unsigned long long)res->end,
812 					 (unsigned int)res->flags);
813 			res->end -= res->start;
814 			res->start = 0;
815 			res->flags |= IORESOURCE_UNSET;
816 			continue;
817 		}
818 
819 		pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
820 			 pci_name(dev), i,
821 			 (unsigned long long)res->start,\
822 			 (unsigned long long)res->end,
823 			 (unsigned int)res->flags);
824 	}
825 
826 	/* Call machine specific resource fixup */
827 	if (ppc_md.pcibios_fixup_resources)
828 		ppc_md.pcibios_fixup_resources(dev);
829 }
830 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
831 
832 /* This function tries to figure out if a bridge resource has been initialized
833  * by the firmware or not. It doesn't have to be absolutely bullet proof, but
834  * things go more smoothly when it gets it right. It should covers cases such
835  * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
836  */
837 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
838 						 struct resource *res)
839 {
840 	struct pci_controller *hose = pci_bus_to_host(bus);
841 	struct pci_dev *dev = bus->self;
842 	resource_size_t offset;
843 	struct pci_bus_region region;
844 	u16 command;
845 	int i;
846 
847 	/* We don't do anything if PCI_PROBE_ONLY is set */
848 	if (pci_has_flag(PCI_PROBE_ONLY))
849 		return 0;
850 
851 	/* Job is a bit different between memory and IO */
852 	if (res->flags & IORESOURCE_MEM) {
853 		pcibios_resource_to_bus(dev->bus, &region, res);
854 
855 		/* If the BAR is non-0 then it's probably been initialized */
856 		if (region.start != 0)
857 			return 0;
858 
859 		/* The BAR is 0, let's check if memory decoding is enabled on
860 		 * the bridge. If not, we consider it unassigned
861 		 */
862 		pci_read_config_word(dev, PCI_COMMAND, &command);
863 		if ((command & PCI_COMMAND_MEMORY) == 0)
864 			return 1;
865 
866 		/* Memory decoding is enabled and the BAR is 0. If any of the bridge
867 		 * resources covers that starting address (0 then it's good enough for
868 		 * us for memory space)
869 		 */
870 		for (i = 0; i < 3; i++) {
871 			if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
872 			    hose->mem_resources[i].start == hose->mem_offset[i])
873 				return 0;
874 		}
875 
876 		/* Well, it starts at 0 and we know it will collide so we may as
877 		 * well consider it as unassigned. That covers the Apple case.
878 		 */
879 		return 1;
880 	} else {
881 		/* If the BAR is non-0, then we consider it assigned */
882 		offset = (unsigned long)hose->io_base_virt - _IO_BASE;
883 		if (((res->start - offset) & 0xfffffffful) != 0)
884 			return 0;
885 
886 		/* Here, we are a bit different than memory as typically IO space
887 		 * starting at low addresses -is- valid. What we do instead if that
888 		 * we consider as unassigned anything that doesn't have IO enabled
889 		 * in the PCI command register, and that's it.
890 		 */
891 		pci_read_config_word(dev, PCI_COMMAND, &command);
892 		if (command & PCI_COMMAND_IO)
893 			return 0;
894 
895 		/* It's starting at 0 and IO is disabled in the bridge, consider
896 		 * it unassigned
897 		 */
898 		return 1;
899 	}
900 }
901 
902 /* Fixup resources of a PCI<->PCI bridge */
903 static void pcibios_fixup_bridge(struct pci_bus *bus)
904 {
905 	struct resource *res;
906 	int i;
907 
908 	struct pci_dev *dev = bus->self;
909 
910 	pci_bus_for_each_resource(bus, res, i) {
911 		if (!res || !res->flags)
912 			continue;
913 		if (i >= 3 && bus->self->transparent)
914 			continue;
915 
916 		/* If we're going to reassign everything, we can
917 		 * shrink the P2P resource to have size as being
918 		 * of 0 in order to save space.
919 		 */
920 		if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
921 			res->flags |= IORESOURCE_UNSET;
922 			res->start = 0;
923 			res->end = -1;
924 			continue;
925 		}
926 
927 		pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
928 			 pci_name(dev), i,
929 			 (unsigned long long)res->start,\
930 			 (unsigned long long)res->end,
931 			 (unsigned int)res->flags);
932 
933 		/* Try to detect uninitialized P2P bridge resources,
934 		 * and clear them out so they get re-assigned later
935 		 */
936 		if (pcibios_uninitialized_bridge_resource(bus, res)) {
937 			res->flags = 0;
938 			pr_debug("PCI:%s            (unassigned)\n", pci_name(dev));
939 		}
940 	}
941 }
942 
943 void pcibios_setup_bus_self(struct pci_bus *bus)
944 {
945 	/* Fix up the bus resources for P2P bridges */
946 	if (bus->self != NULL)
947 		pcibios_fixup_bridge(bus);
948 
949 	/* Platform specific bus fixups. This is currently only used
950 	 * by fsl_pci and I'm hoping to get rid of it at some point
951 	 */
952 	if (ppc_md.pcibios_fixup_bus)
953 		ppc_md.pcibios_fixup_bus(bus);
954 
955 	/* Setup bus DMA mappings */
956 	if (ppc_md.pci_dma_bus_setup)
957 		ppc_md.pci_dma_bus_setup(bus);
958 }
959 
960 static void pcibios_setup_device(struct pci_dev *dev)
961 {
962 	/* Fixup NUMA node as it may not be setup yet by the generic
963 	 * code and is needed by the DMA init
964 	 */
965 	set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
966 
967 	/* Hook up default DMA ops */
968 	set_dma_ops(&dev->dev, pci_dma_ops);
969 	set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
970 
971 	/* Additional platform DMA/iommu setup */
972 	if (ppc_md.pci_dma_dev_setup)
973 		ppc_md.pci_dma_dev_setup(dev);
974 
975 	/* Read default IRQs and fixup if necessary */
976 	pci_read_irq_line(dev);
977 	if (ppc_md.pci_irq_fixup)
978 		ppc_md.pci_irq_fixup(dev);
979 }
980 
981 int pcibios_add_device(struct pci_dev *dev)
982 {
983 	/*
984 	 * We can only call pcibios_setup_device() after bus setup is complete,
985 	 * since some of the platform specific DMA setup code depends on it.
986 	 */
987 	if (dev->bus->is_added)
988 		pcibios_setup_device(dev);
989 	return 0;
990 }
991 
992 void pcibios_setup_bus_devices(struct pci_bus *bus)
993 {
994 	struct pci_dev *dev;
995 
996 	pr_debug("PCI: Fixup bus devices %d (%s)\n",
997 		 bus->number, bus->self ? pci_name(bus->self) : "PHB");
998 
999 	list_for_each_entry(dev, &bus->devices, bus_list) {
1000 		/* Cardbus can call us to add new devices to a bus, so ignore
1001 		 * those who are already fully discovered
1002 		 */
1003 		if (dev->is_added)
1004 			continue;
1005 
1006 		pcibios_setup_device(dev);
1007 	}
1008 }
1009 
1010 void pcibios_set_master(struct pci_dev *dev)
1011 {
1012 	/* No special bus mastering setup handling */
1013 }
1014 
1015 void pcibios_fixup_bus(struct pci_bus *bus)
1016 {
1017 	/* When called from the generic PCI probe, read PCI<->PCI bridge
1018 	 * bases. This is -not- called when generating the PCI tree from
1019 	 * the OF device-tree.
1020 	 */
1021 	pci_read_bridge_bases(bus);
1022 
1023 	/* Now fixup the bus bus */
1024 	pcibios_setup_bus_self(bus);
1025 
1026 	/* Now fixup devices on that bus */
1027 	pcibios_setup_bus_devices(bus);
1028 }
1029 EXPORT_SYMBOL(pcibios_fixup_bus);
1030 
1031 void pci_fixup_cardbus(struct pci_bus *bus)
1032 {
1033 	/* Now fixup devices on that bus */
1034 	pcibios_setup_bus_devices(bus);
1035 }
1036 
1037 
1038 static int skip_isa_ioresource_align(struct pci_dev *dev)
1039 {
1040 	if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1041 	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1042 		return 1;
1043 	return 0;
1044 }
1045 
1046 /*
1047  * We need to avoid collisions with `mirrored' VGA ports
1048  * and other strange ISA hardware, so we always want the
1049  * addresses to be allocated in the 0x000-0x0ff region
1050  * modulo 0x400.
1051  *
1052  * Why? Because some silly external IO cards only decode
1053  * the low 10 bits of the IO address. The 0x00-0xff region
1054  * is reserved for motherboard devices that decode all 16
1055  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1056  * but we want to try to avoid allocating at 0x2900-0x2bff
1057  * which might have be mirrored at 0x0100-0x03ff..
1058  */
1059 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1060 				resource_size_t size, resource_size_t align)
1061 {
1062 	struct pci_dev *dev = data;
1063 	resource_size_t start = res->start;
1064 
1065 	if (res->flags & IORESOURCE_IO) {
1066 		if (skip_isa_ioresource_align(dev))
1067 			return start;
1068 		if (start & 0x300)
1069 			start = (start + 0x3ff) & ~0x3ff;
1070 	}
1071 
1072 	return start;
1073 }
1074 EXPORT_SYMBOL(pcibios_align_resource);
1075 
1076 /*
1077  * Reparent resource children of pr that conflict with res
1078  * under res, and make res replace those children.
1079  */
1080 static int reparent_resources(struct resource *parent,
1081 				     struct resource *res)
1082 {
1083 	struct resource *p, **pp;
1084 	struct resource **firstpp = NULL;
1085 
1086 	for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1087 		if (p->end < res->start)
1088 			continue;
1089 		if (res->end < p->start)
1090 			break;
1091 		if (p->start < res->start || p->end > res->end)
1092 			return -1;	/* not completely contained */
1093 		if (firstpp == NULL)
1094 			firstpp = pp;
1095 	}
1096 	if (firstpp == NULL)
1097 		return -1;	/* didn't find any conflicting entries? */
1098 	res->parent = parent;
1099 	res->child = *firstpp;
1100 	res->sibling = *pp;
1101 	*firstpp = res;
1102 	*pp = NULL;
1103 	for (p = res->child; p != NULL; p = p->sibling) {
1104 		p->parent = res;
1105 		pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1106 			 p->name,
1107 			 (unsigned long long)p->start,
1108 			 (unsigned long long)p->end, res->name);
1109 	}
1110 	return 0;
1111 }
1112 
1113 /*
1114  *  Handle resources of PCI devices.  If the world were perfect, we could
1115  *  just allocate all the resource regions and do nothing more.  It isn't.
1116  *  On the other hand, we cannot just re-allocate all devices, as it would
1117  *  require us to know lots of host bridge internals.  So we attempt to
1118  *  keep as much of the original configuration as possible, but tweak it
1119  *  when it's found to be wrong.
1120  *
1121  *  Known BIOS problems we have to work around:
1122  *	- I/O or memory regions not configured
1123  *	- regions configured, but not enabled in the command register
1124  *	- bogus I/O addresses above 64K used
1125  *	- expansion ROMs left enabled (this may sound harmless, but given
1126  *	  the fact the PCI specs explicitly allow address decoders to be
1127  *	  shared between expansion ROMs and other resource regions, it's
1128  *	  at least dangerous)
1129  *
1130  *  Our solution:
1131  *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
1132  *	    This gives us fixed barriers on where we can allocate.
1133  *	(2) Allocate resources for all enabled devices.  If there is
1134  *	    a collision, just mark the resource as unallocated. Also
1135  *	    disable expansion ROMs during this step.
1136  *	(3) Try to allocate resources for disabled devices.  If the
1137  *	    resources were assigned correctly, everything goes well,
1138  *	    if they weren't, they won't disturb allocation of other
1139  *	    resources.
1140  *	(4) Assign new addresses to resources which were either
1141  *	    not configured at all or misconfigured.  If explicitly
1142  *	    requested by the user, configure expansion ROM address
1143  *	    as well.
1144  */
1145 
1146 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1147 {
1148 	struct pci_bus *b;
1149 	int i;
1150 	struct resource *res, *pr;
1151 
1152 	pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1153 		 pci_domain_nr(bus), bus->number);
1154 
1155 	pci_bus_for_each_resource(bus, res, i) {
1156 		if (!res || !res->flags || res->start > res->end || res->parent)
1157 			continue;
1158 
1159 		/* If the resource was left unset at this point, we clear it */
1160 		if (res->flags & IORESOURCE_UNSET)
1161 			goto clear_resource;
1162 
1163 		if (bus->parent == NULL)
1164 			pr = (res->flags & IORESOURCE_IO) ?
1165 				&ioport_resource : &iomem_resource;
1166 		else {
1167 			pr = pci_find_parent_resource(bus->self, res);
1168 			if (pr == res) {
1169 				/* this happens when the generic PCI
1170 				 * code (wrongly) decides that this
1171 				 * bridge is transparent  -- paulus
1172 				 */
1173 				continue;
1174 			}
1175 		}
1176 
1177 		pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1178 			 "[0x%x], parent %p (%s)\n",
1179 			 bus->self ? pci_name(bus->self) : "PHB",
1180 			 bus->number, i,
1181 			 (unsigned long long)res->start,
1182 			 (unsigned long long)res->end,
1183 			 (unsigned int)res->flags,
1184 			 pr, (pr && pr->name) ? pr->name : "nil");
1185 
1186 		if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1187 			struct pci_dev *dev = bus->self;
1188 
1189 			if (request_resource(pr, res) == 0)
1190 				continue;
1191 			/*
1192 			 * Must be a conflict with an existing entry.
1193 			 * Move that entry (or entries) under the
1194 			 * bridge resource and try again.
1195 			 */
1196 			if (reparent_resources(pr, res) == 0)
1197 				continue;
1198 
1199 			if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1200 			    pci_claim_bridge_resource(dev,
1201 						i + PCI_BRIDGE_RESOURCES) == 0)
1202 				continue;
1203 		}
1204 		pr_warning("PCI: Cannot allocate resource region "
1205 			   "%d of PCI bridge %d, will remap\n", i, bus->number);
1206 	clear_resource:
1207 		/* The resource might be figured out when doing
1208 		 * reassignment based on the resources required
1209 		 * by the downstream PCI devices. Here we set
1210 		 * the size of the resource to be 0 in order to
1211 		 * save more space.
1212 		 */
1213 		res->start = 0;
1214 		res->end = -1;
1215 		res->flags = 0;
1216 	}
1217 
1218 	list_for_each_entry(b, &bus->children, node)
1219 		pcibios_allocate_bus_resources(b);
1220 }
1221 
1222 static inline void alloc_resource(struct pci_dev *dev, int idx)
1223 {
1224 	struct resource *pr, *r = &dev->resource[idx];
1225 
1226 	pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1227 		 pci_name(dev), idx,
1228 		 (unsigned long long)r->start,
1229 		 (unsigned long long)r->end,
1230 		 (unsigned int)r->flags);
1231 
1232 	pr = pci_find_parent_resource(dev, r);
1233 	if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1234 	    request_resource(pr, r) < 0) {
1235 		printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1236 		       " of device %s, will remap\n", idx, pci_name(dev));
1237 		if (pr)
1238 			pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
1239 				 pr,
1240 				 (unsigned long long)pr->start,
1241 				 (unsigned long long)pr->end,
1242 				 (unsigned int)pr->flags);
1243 		/* We'll assign a new address later */
1244 		r->flags |= IORESOURCE_UNSET;
1245 		r->end -= r->start;
1246 		r->start = 0;
1247 	}
1248 }
1249 
1250 static void __init pcibios_allocate_resources(int pass)
1251 {
1252 	struct pci_dev *dev = NULL;
1253 	int idx, disabled;
1254 	u16 command;
1255 	struct resource *r;
1256 
1257 	for_each_pci_dev(dev) {
1258 		pci_read_config_word(dev, PCI_COMMAND, &command);
1259 		for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1260 			r = &dev->resource[idx];
1261 			if (r->parent)		/* Already allocated */
1262 				continue;
1263 			if (!r->flags || (r->flags & IORESOURCE_UNSET))
1264 				continue;	/* Not assigned at all */
1265 			/* We only allocate ROMs on pass 1 just in case they
1266 			 * have been screwed up by firmware
1267 			 */
1268 			if (idx == PCI_ROM_RESOURCE )
1269 				disabled = 1;
1270 			if (r->flags & IORESOURCE_IO)
1271 				disabled = !(command & PCI_COMMAND_IO);
1272 			else
1273 				disabled = !(command & PCI_COMMAND_MEMORY);
1274 			if (pass == disabled)
1275 				alloc_resource(dev, idx);
1276 		}
1277 		if (pass)
1278 			continue;
1279 		r = &dev->resource[PCI_ROM_RESOURCE];
1280 		if (r->flags) {
1281 			/* Turn the ROM off, leave the resource region,
1282 			 * but keep it unregistered.
1283 			 */
1284 			u32 reg;
1285 			pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1286 			if (reg & PCI_ROM_ADDRESS_ENABLE) {
1287 				pr_debug("PCI: Switching off ROM of %s\n",
1288 					 pci_name(dev));
1289 				r->flags &= ~IORESOURCE_ROM_ENABLE;
1290 				pci_write_config_dword(dev, dev->rom_base_reg,
1291 						       reg & ~PCI_ROM_ADDRESS_ENABLE);
1292 			}
1293 		}
1294 	}
1295 }
1296 
1297 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1298 {
1299 	struct pci_controller *hose = pci_bus_to_host(bus);
1300 	resource_size_t	offset;
1301 	struct resource *res, *pres;
1302 	int i;
1303 
1304 	pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1305 
1306 	/* Check for IO */
1307 	if (!(hose->io_resource.flags & IORESOURCE_IO))
1308 		goto no_io;
1309 	offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1310 	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1311 	BUG_ON(res == NULL);
1312 	res->name = "Legacy IO";
1313 	res->flags = IORESOURCE_IO;
1314 	res->start = offset;
1315 	res->end = (offset + 0xfff) & 0xfffffffful;
1316 	pr_debug("Candidate legacy IO: %pR\n", res);
1317 	if (request_resource(&hose->io_resource, res)) {
1318 		printk(KERN_DEBUG
1319 		       "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1320 		       pci_domain_nr(bus), bus->number, res);
1321 		kfree(res);
1322 	}
1323 
1324  no_io:
1325 	/* Check for memory */
1326 	for (i = 0; i < 3; i++) {
1327 		pres = &hose->mem_resources[i];
1328 		offset = hose->mem_offset[i];
1329 		if (!(pres->flags & IORESOURCE_MEM))
1330 			continue;
1331 		pr_debug("hose mem res: %pR\n", pres);
1332 		if ((pres->start - offset) <= 0xa0000 &&
1333 		    (pres->end - offset) >= 0xbffff)
1334 			break;
1335 	}
1336 	if (i >= 3)
1337 		return;
1338 	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1339 	BUG_ON(res == NULL);
1340 	res->name = "Legacy VGA memory";
1341 	res->flags = IORESOURCE_MEM;
1342 	res->start = 0xa0000 + offset;
1343 	res->end = 0xbffff + offset;
1344 	pr_debug("Candidate VGA memory: %pR\n", res);
1345 	if (request_resource(pres, res)) {
1346 		printk(KERN_DEBUG
1347 		       "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1348 		       pci_domain_nr(bus), bus->number, res);
1349 		kfree(res);
1350 	}
1351 }
1352 
1353 void __init pcibios_resource_survey(void)
1354 {
1355 	struct pci_bus *b;
1356 
1357 	/* Allocate and assign resources */
1358 	list_for_each_entry(b, &pci_root_buses, node)
1359 		pcibios_allocate_bus_resources(b);
1360 	pcibios_allocate_resources(0);
1361 	pcibios_allocate_resources(1);
1362 
1363 	/* Before we start assigning unassigned resource, we try to reserve
1364 	 * the low IO area and the VGA memory area if they intersect the
1365 	 * bus available resources to avoid allocating things on top of them
1366 	 */
1367 	if (!pci_has_flag(PCI_PROBE_ONLY)) {
1368 		list_for_each_entry(b, &pci_root_buses, node)
1369 			pcibios_reserve_legacy_regions(b);
1370 	}
1371 
1372 	/* Now, if the platform didn't decide to blindly trust the firmware,
1373 	 * we proceed to assigning things that were left unassigned
1374 	 */
1375 	if (!pci_has_flag(PCI_PROBE_ONLY)) {
1376 		pr_debug("PCI: Assigning unassigned resources...\n");
1377 		pci_assign_unassigned_resources();
1378 	}
1379 
1380 	/* Call machine dependent fixup */
1381 	if (ppc_md.pcibios_fixup)
1382 		ppc_md.pcibios_fixup();
1383 }
1384 
1385 /* This is used by the PCI hotplug driver to allocate resource
1386  * of newly plugged busses. We can try to consolidate with the
1387  * rest of the code later, for now, keep it as-is as our main
1388  * resource allocation function doesn't deal with sub-trees yet.
1389  */
1390 void pcibios_claim_one_bus(struct pci_bus *bus)
1391 {
1392 	struct pci_dev *dev;
1393 	struct pci_bus *child_bus;
1394 
1395 	list_for_each_entry(dev, &bus->devices, bus_list) {
1396 		int i;
1397 
1398 		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1399 			struct resource *r = &dev->resource[i];
1400 
1401 			if (r->parent || !r->start || !r->flags)
1402 				continue;
1403 
1404 			pr_debug("PCI: Claiming %s: "
1405 				 "Resource %d: %016llx..%016llx [%x]\n",
1406 				 pci_name(dev), i,
1407 				 (unsigned long long)r->start,
1408 				 (unsigned long long)r->end,
1409 				 (unsigned int)r->flags);
1410 
1411 			if (pci_claim_resource(dev, i) == 0)
1412 				continue;
1413 
1414 			pci_claim_bridge_resource(dev, i);
1415 		}
1416 	}
1417 
1418 	list_for_each_entry(child_bus, &bus->children, node)
1419 		pcibios_claim_one_bus(child_bus);
1420 }
1421 
1422 
1423 /* pcibios_finish_adding_to_bus
1424  *
1425  * This is to be called by the hotplug code after devices have been
1426  * added to a bus, this include calling it for a PHB that is just
1427  * being added
1428  */
1429 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1430 {
1431 	pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1432 		 pci_domain_nr(bus), bus->number);
1433 
1434 	/* Allocate bus and devices resources */
1435 	pcibios_allocate_bus_resources(bus);
1436 	pcibios_claim_one_bus(bus);
1437 	if (!pci_has_flag(PCI_PROBE_ONLY))
1438 		pci_assign_unassigned_bus_resources(bus);
1439 
1440 	/* Fixup EEH */
1441 	eeh_add_device_tree_late(bus);
1442 
1443 	/* Add new devices to global lists.  Register in proc, sysfs. */
1444 	pci_bus_add_devices(bus);
1445 
1446 	/* sysfs files should only be added after devices are added */
1447 	eeh_add_sysfs_files(bus);
1448 }
1449 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1450 
1451 int pcibios_enable_device(struct pci_dev *dev, int mask)
1452 {
1453 	if (ppc_md.pcibios_enable_device_hook)
1454 		if (ppc_md.pcibios_enable_device_hook(dev))
1455 			return -EINVAL;
1456 
1457 	return pci_enable_resources(dev, mask);
1458 }
1459 
1460 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1461 {
1462 	return (unsigned long) hose->io_base_virt - _IO_BASE;
1463 }
1464 
1465 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1466 					struct list_head *resources)
1467 {
1468 	struct resource *res;
1469 	resource_size_t offset;
1470 	int i;
1471 
1472 	/* Hookup PHB IO resource */
1473 	res = &hose->io_resource;
1474 
1475 	if (!res->flags) {
1476 		pr_info("PCI: I/O resource not set for host"
1477 		       " bridge %s (domain %d)\n",
1478 		       hose->dn->full_name, hose->global_number);
1479 	} else {
1480 		offset = pcibios_io_space_offset(hose);
1481 
1482 		pr_debug("PCI: PHB IO resource    = %08llx-%08llx [%lx] off 0x%08llx\n",
1483 			 (unsigned long long)res->start,
1484 			 (unsigned long long)res->end,
1485 			 (unsigned long)res->flags,
1486 			 (unsigned long long)offset);
1487 		pci_add_resource_offset(resources, res, offset);
1488 	}
1489 
1490 	/* Hookup PHB Memory resources */
1491 	for (i = 0; i < 3; ++i) {
1492 		res = &hose->mem_resources[i];
1493 		if (!res->flags) {
1494 			if (i == 0)
1495 				printk(KERN_ERR "PCI: Memory resource 0 not set for "
1496 				       "host bridge %s (domain %d)\n",
1497 				       hose->dn->full_name, hose->global_number);
1498 			continue;
1499 		}
1500 		offset = hose->mem_offset[i];
1501 
1502 
1503 		pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1504 			 (unsigned long long)res->start,
1505 			 (unsigned long long)res->end,
1506 			 (unsigned long)res->flags,
1507 			 (unsigned long long)offset);
1508 
1509 		pci_add_resource_offset(resources, res, offset);
1510 	}
1511 }
1512 
1513 /*
1514  * Null PCI config access functions, for the case when we can't
1515  * find a hose.
1516  */
1517 #define NULL_PCI_OP(rw, size, type)					\
1518 static int								\
1519 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)	\
1520 {									\
1521 	return PCIBIOS_DEVICE_NOT_FOUND;    				\
1522 }
1523 
1524 static int
1525 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1526 		 int len, u32 *val)
1527 {
1528 	return PCIBIOS_DEVICE_NOT_FOUND;
1529 }
1530 
1531 static int
1532 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1533 		  int len, u32 val)
1534 {
1535 	return PCIBIOS_DEVICE_NOT_FOUND;
1536 }
1537 
1538 static struct pci_ops null_pci_ops =
1539 {
1540 	.read = null_read_config,
1541 	.write = null_write_config,
1542 };
1543 
1544 /*
1545  * These functions are used early on before PCI scanning is done
1546  * and all of the pci_dev and pci_bus structures have been created.
1547  */
1548 static struct pci_bus *
1549 fake_pci_bus(struct pci_controller *hose, int busnr)
1550 {
1551 	static struct pci_bus bus;
1552 
1553 	if (hose == NULL) {
1554 		printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1555 	}
1556 	bus.number = busnr;
1557 	bus.sysdata = hose;
1558 	bus.ops = hose? hose->ops: &null_pci_ops;
1559 	return &bus;
1560 }
1561 
1562 #define EARLY_PCI_OP(rw, size, type)					\
1563 int early_##rw##_config_##size(struct pci_controller *hose, int bus,	\
1564 			       int devfn, int offset, type value)	\
1565 {									\
1566 	return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),	\
1567 					    devfn, offset, value);	\
1568 }
1569 
1570 EARLY_PCI_OP(read, byte, u8 *)
1571 EARLY_PCI_OP(read, word, u16 *)
1572 EARLY_PCI_OP(read, dword, u32 *)
1573 EARLY_PCI_OP(write, byte, u8)
1574 EARLY_PCI_OP(write, word, u16)
1575 EARLY_PCI_OP(write, dword, u32)
1576 
1577 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1578 			  int cap)
1579 {
1580 	return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1581 }
1582 
1583 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1584 {
1585 	struct pci_controller *hose = bus->sysdata;
1586 
1587 	return of_node_get(hose->dn);
1588 }
1589 
1590 /**
1591  * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1592  * @hose: Pointer to the PCI host controller instance structure
1593  */
1594 void pcibios_scan_phb(struct pci_controller *hose)
1595 {
1596 	LIST_HEAD(resources);
1597 	struct pci_bus *bus;
1598 	struct device_node *node = hose->dn;
1599 	int mode;
1600 
1601 	pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1602 
1603 	/* Get some IO space for the new PHB */
1604 	pcibios_setup_phb_io_space(hose);
1605 
1606 	/* Wire up PHB bus resources */
1607 	pcibios_setup_phb_resources(hose, &resources);
1608 
1609 	hose->busn.start = hose->first_busno;
1610 	hose->busn.end	 = hose->last_busno;
1611 	hose->busn.flags = IORESOURCE_BUS;
1612 	pci_add_resource(&resources, &hose->busn);
1613 
1614 	/* Create an empty bus for the toplevel */
1615 	bus = pci_create_root_bus(hose->parent, hose->first_busno,
1616 				  hose->ops, hose, &resources);
1617 	if (bus == NULL) {
1618 		pr_err("Failed to create bus for PCI domain %04x\n",
1619 			hose->global_number);
1620 		pci_free_resource_list(&resources);
1621 		return;
1622 	}
1623 	hose->bus = bus;
1624 
1625 	/* Get probe mode and perform scan */
1626 	mode = PCI_PROBE_NORMAL;
1627 	if (node && ppc_md.pci_probe_mode)
1628 		mode = ppc_md.pci_probe_mode(bus);
1629 	pr_debug("    probe mode: %d\n", mode);
1630 	if (mode == PCI_PROBE_DEVTREE)
1631 		of_scan_bus(node, bus);
1632 
1633 	if (mode == PCI_PROBE_NORMAL) {
1634 		pci_bus_update_busn_res_end(bus, 255);
1635 		hose->last_busno = pci_scan_child_bus(bus);
1636 		pci_bus_update_busn_res_end(bus, hose->last_busno);
1637 	}
1638 
1639 	/* Platform gets a chance to do some global fixups before
1640 	 * we proceed to resource allocation
1641 	 */
1642 	if (ppc_md.pcibios_fixup_phb)
1643 		ppc_md.pcibios_fixup_phb(hose);
1644 
1645 	/* Configure PCI Express settings */
1646 	if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1647 		struct pci_bus *child;
1648 		list_for_each_entry(child, &bus->children, node)
1649 			pcie_bus_configure_settings(child);
1650 	}
1651 }
1652 
1653 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1654 {
1655 	int i, class = dev->class >> 8;
1656 	/* When configured as agent, programing interface = 1 */
1657 	int prog_if = dev->class & 0xf;
1658 
1659 	if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1660 	     class == PCI_CLASS_BRIDGE_OTHER) &&
1661 		(dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1662 		(prog_if == 0) &&
1663 		(dev->bus->parent == NULL)) {
1664 		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1665 			dev->resource[i].start = 0;
1666 			dev->resource[i].end = 0;
1667 			dev->resource[i].flags = 0;
1668 		}
1669 	}
1670 }
1671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1673 
1674 static void fixup_vga(struct pci_dev *pdev)
1675 {
1676 	u16 cmd;
1677 
1678 	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1679 	if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1680 		vga_set_default_device(pdev);
1681 
1682 }
1683 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1684 			      PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);
1685