1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/shmem_fs.h> 29 #include <linux/list.h> 30 #include <linux/syscalls.h> 31 #include <linux/irq.h> 32 #include <linux/vmalloc.h> 33 #include <linux/slab.h> 34 #include <linux/vgaarb.h> 35 36 #include <asm/processor.h> 37 #include <asm/io.h> 38 #include <asm/prom.h> 39 #include <asm/pci-bridge.h> 40 #include <asm/byteorder.h> 41 #include <asm/machdep.h> 42 #include <asm/ppc-pci.h> 43 #include <asm/eeh.h> 44 45 /* hose_spinlock protects accesses to the the phb_bitmap. */ 46 static DEFINE_SPINLOCK(hose_spinlock); 47 LIST_HEAD(hose_list); 48 49 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */ 50 #define MAX_PHBS 0x10000 51 52 /* 53 * For dynamic PHB numbering: used/free PHBs tracking bitmap. 54 * Accesses to this bitmap should be protected by hose_spinlock. 55 */ 56 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS); 57 58 /* ISA Memory physical address */ 59 resource_size_t isa_mem_base; 60 EXPORT_SYMBOL(isa_mem_base); 61 62 63 static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops; 64 65 void set_pci_dma_ops(const struct dma_map_ops *dma_ops) 66 { 67 pci_dma_ops = dma_ops; 68 } 69 70 const struct dma_map_ops *get_pci_dma_ops(void) 71 { 72 return pci_dma_ops; 73 } 74 EXPORT_SYMBOL(get_pci_dma_ops); 75 76 /* 77 * This function should run under locking protection, specifically 78 * hose_spinlock. 79 */ 80 static int get_phb_number(struct device_node *dn) 81 { 82 int ret, phb_id = -1; 83 u32 prop_32; 84 u64 prop; 85 86 /* 87 * Try fixed PHB numbering first, by checking archs and reading 88 * the respective device-tree properties. Firstly, try powernv by 89 * reading "ibm,opal-phbid", only present in OPAL environment. 90 */ 91 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); 92 if (ret) { 93 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32); 94 prop = prop_32; 95 } 96 97 if (!ret) 98 phb_id = (int)(prop & (MAX_PHBS - 1)); 99 100 /* We need to be sure to not use the same PHB number twice. */ 101 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap)) 102 return phb_id; 103 104 /* 105 * If not pseries nor powernv, or if fixed PHB numbering tried to add 106 * the same PHB number twice, then fallback to dynamic PHB numbering. 107 */ 108 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS); 109 BUG_ON(phb_id >= MAX_PHBS); 110 set_bit(phb_id, phb_bitmap); 111 112 return phb_id; 113 } 114 115 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 116 { 117 struct pci_controller *phb; 118 119 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 120 if (phb == NULL) 121 return NULL; 122 spin_lock(&hose_spinlock); 123 phb->global_number = get_phb_number(dev); 124 list_add_tail(&phb->list_node, &hose_list); 125 spin_unlock(&hose_spinlock); 126 phb->dn = dev; 127 phb->is_dynamic = slab_is_available(); 128 #ifdef CONFIG_PPC64 129 if (dev) { 130 int nid = of_node_to_nid(dev); 131 132 if (nid < 0 || !node_online(nid)) 133 nid = -1; 134 135 PHB_SET_NODE(phb, nid); 136 } 137 #endif 138 return phb; 139 } 140 EXPORT_SYMBOL_GPL(pcibios_alloc_controller); 141 142 void pcibios_free_controller(struct pci_controller *phb) 143 { 144 spin_lock(&hose_spinlock); 145 146 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ 147 if (phb->global_number < MAX_PHBS) 148 clear_bit(phb->global_number, phb_bitmap); 149 150 list_del(&phb->list_node); 151 spin_unlock(&hose_spinlock); 152 153 if (phb->is_dynamic) 154 kfree(phb); 155 } 156 EXPORT_SYMBOL_GPL(pcibios_free_controller); 157 158 /* 159 * This function is used to call pcibios_free_controller() 160 * in a deferred manner: a callback from the PCI subsystem. 161 * 162 * _*DO NOT*_ call pcibios_free_controller() explicitly if 163 * this is used (or it may access an invalid *phb pointer). 164 * 165 * The callback occurs when all references to the root bus 166 * are dropped (e.g., child buses/devices and their users). 167 * 168 * It's called as .release_fn() of 'struct pci_host_bridge' 169 * which is associated with the 'struct pci_controller.bus' 170 * (root bus) - it expects .release_data to hold a pointer 171 * to 'struct pci_controller'. 172 * 173 * In order to use it, register .release_fn()/release_data 174 * like this: 175 * 176 * pci_set_host_bridge_release(bridge, 177 * pcibios_free_controller_deferred 178 * (void *) phb); 179 * 180 * e.g. in the pcibios_root_bridge_prepare() callback from 181 * pci_create_root_bus(). 182 */ 183 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge) 184 { 185 struct pci_controller *phb = (struct pci_controller *) 186 bridge->release_data; 187 188 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); 189 190 pcibios_free_controller(phb); 191 } 192 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred); 193 194 /* 195 * The function is used to return the minimal alignment 196 * for memory or I/O windows of the associated P2P bridge. 197 * By default, 4KiB alignment for I/O windows and 1MiB for 198 * memory windows. 199 */ 200 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 201 unsigned long type) 202 { 203 struct pci_controller *phb = pci_bus_to_host(bus); 204 205 if (phb->controller_ops.window_alignment) 206 return phb->controller_ops.window_alignment(bus, type); 207 208 /* 209 * PCI core will figure out the default 210 * alignment: 4KiB for I/O and 1MiB for 211 * memory window. 212 */ 213 return 1; 214 } 215 216 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 217 { 218 struct pci_controller *hose = pci_bus_to_host(bus); 219 220 if (hose->controller_ops.setup_bridge) 221 hose->controller_ops.setup_bridge(bus, type); 222 } 223 224 void pcibios_reset_secondary_bus(struct pci_dev *dev) 225 { 226 struct pci_controller *phb = pci_bus_to_host(dev->bus); 227 228 if (phb->controller_ops.reset_secondary_bus) { 229 phb->controller_ops.reset_secondary_bus(dev); 230 return; 231 } 232 233 pci_reset_secondary_bus(dev); 234 } 235 236 resource_size_t pcibios_default_alignment(void) 237 { 238 if (ppc_md.pcibios_default_alignment) 239 return ppc_md.pcibios_default_alignment(); 240 241 return 0; 242 } 243 244 #ifdef CONFIG_PCI_IOV 245 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) 246 { 247 if (ppc_md.pcibios_iov_resource_alignment) 248 return ppc_md.pcibios_iov_resource_alignment(pdev, resno); 249 250 return pci_iov_resource_size(pdev, resno); 251 } 252 253 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 254 { 255 if (ppc_md.pcibios_sriov_enable) 256 return ppc_md.pcibios_sriov_enable(pdev, num_vfs); 257 258 return 0; 259 } 260 261 int pcibios_sriov_disable(struct pci_dev *pdev) 262 { 263 if (ppc_md.pcibios_sriov_disable) 264 return ppc_md.pcibios_sriov_disable(pdev); 265 266 return 0; 267 } 268 269 #endif /* CONFIG_PCI_IOV */ 270 271 void pcibios_bus_add_device(struct pci_dev *pdev) 272 { 273 if (ppc_md.pcibios_bus_add_device) 274 ppc_md.pcibios_bus_add_device(pdev); 275 } 276 277 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 278 { 279 #ifdef CONFIG_PPC64 280 return hose->pci_io_size; 281 #else 282 return resource_size(&hose->io_resource); 283 #endif 284 } 285 286 int pcibios_vaddr_is_ioport(void __iomem *address) 287 { 288 int ret = 0; 289 struct pci_controller *hose; 290 resource_size_t size; 291 292 spin_lock(&hose_spinlock); 293 list_for_each_entry(hose, &hose_list, list_node) { 294 size = pcibios_io_size(hose); 295 if (address >= hose->io_base_virt && 296 address < (hose->io_base_virt + size)) { 297 ret = 1; 298 break; 299 } 300 } 301 spin_unlock(&hose_spinlock); 302 return ret; 303 } 304 305 unsigned long pci_address_to_pio(phys_addr_t address) 306 { 307 struct pci_controller *hose; 308 resource_size_t size; 309 unsigned long ret = ~0; 310 311 spin_lock(&hose_spinlock); 312 list_for_each_entry(hose, &hose_list, list_node) { 313 size = pcibios_io_size(hose); 314 if (address >= hose->io_base_phys && 315 address < (hose->io_base_phys + size)) { 316 unsigned long base = 317 (unsigned long)hose->io_base_virt - _IO_BASE; 318 ret = base + (address - hose->io_base_phys); 319 break; 320 } 321 } 322 spin_unlock(&hose_spinlock); 323 324 return ret; 325 } 326 EXPORT_SYMBOL_GPL(pci_address_to_pio); 327 328 /* 329 * Return the domain number for this bus. 330 */ 331 int pci_domain_nr(struct pci_bus *bus) 332 { 333 struct pci_controller *hose = pci_bus_to_host(bus); 334 335 return hose->global_number; 336 } 337 EXPORT_SYMBOL(pci_domain_nr); 338 339 /* This routine is meant to be used early during boot, when the 340 * PCI bus numbers have not yet been assigned, and you need to 341 * issue PCI config cycles to an OF device. 342 * It could also be used to "fix" RTAS config cycles if you want 343 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 344 * config cycles. 345 */ 346 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 347 { 348 while(node) { 349 struct pci_controller *hose, *tmp; 350 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 351 if (hose->dn == node) 352 return hose; 353 node = node->parent; 354 } 355 return NULL; 356 } 357 358 /* 359 * Reads the interrupt pin to determine if interrupt is use by card. 360 * If the interrupt is used, then gets the interrupt line from the 361 * openfirmware and sets it in the pci_dev and pci_config line. 362 */ 363 static int pci_read_irq_line(struct pci_dev *pci_dev) 364 { 365 int virq; 366 367 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 368 369 #ifdef DEBUG 370 memset(&oirq, 0xff, sizeof(oirq)); 371 #endif 372 /* Try to get a mapping from the device-tree */ 373 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0); 374 if (virq <= 0) { 375 u8 line, pin; 376 377 /* If that fails, lets fallback to what is in the config 378 * space and map that through the default controller. We 379 * also set the type to level low since that's what PCI 380 * interrupts are. If your platform does differently, then 381 * either provide a proper interrupt tree or don't use this 382 * function. 383 */ 384 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 385 return -1; 386 if (pin == 0) 387 return -1; 388 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 389 line == 0xff || line == 0) { 390 return -1; 391 } 392 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 393 line, pin); 394 395 virq = irq_create_mapping(NULL, line); 396 if (virq) 397 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 398 } 399 400 if (!virq) { 401 pr_debug(" Failed to map !\n"); 402 return -1; 403 } 404 405 pr_debug(" Mapped to linux irq %d\n", virq); 406 407 pci_dev->irq = virq; 408 409 return 0; 410 } 411 412 /* 413 * Platform support for /proc/bus/pci/X/Y mmap()s, 414 * modelled on the sparc64 implementation by Dave Miller. 415 * -- paulus. 416 */ 417 418 /* 419 * Adjust vm_pgoff of VMA such that it is the physical page offset 420 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 421 * 422 * Basically, the user finds the base address for his device which he wishes 423 * to mmap. They read the 32-bit value from the config space base register, 424 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 425 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 426 * 427 * Returns negative error code on failure, zero on success. 428 */ 429 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 430 resource_size_t *offset, 431 enum pci_mmap_state mmap_state) 432 { 433 struct pci_controller *hose = pci_bus_to_host(dev->bus); 434 unsigned long io_offset = 0; 435 int i, res_bit; 436 437 if (hose == NULL) 438 return NULL; /* should never happen */ 439 440 /* If memory, add on the PCI bridge address offset */ 441 if (mmap_state == pci_mmap_mem) { 442 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 443 *offset += hose->pci_mem_offset; 444 #endif 445 res_bit = IORESOURCE_MEM; 446 } else { 447 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 448 *offset += io_offset; 449 res_bit = IORESOURCE_IO; 450 } 451 452 /* 453 * Check that the offset requested corresponds to one of the 454 * resources of the device. 455 */ 456 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 457 struct resource *rp = &dev->resource[i]; 458 int flags = rp->flags; 459 460 /* treat ROM as memory (should be already) */ 461 if (i == PCI_ROM_RESOURCE) 462 flags |= IORESOURCE_MEM; 463 464 /* Active and same type? */ 465 if ((flags & res_bit) == 0) 466 continue; 467 468 /* In the range of this resource? */ 469 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 470 continue; 471 472 /* found it! construct the final physical address */ 473 if (mmap_state == pci_mmap_io) 474 *offset += hose->io_base_phys - io_offset; 475 return rp; 476 } 477 478 return NULL; 479 } 480 481 /* 482 * This one is used by /dev/mem and fbdev who have no clue about the 483 * PCI device, it tries to find the PCI device first and calls the 484 * above routine 485 */ 486 pgprot_t pci_phys_mem_access_prot(struct file *file, 487 unsigned long pfn, 488 unsigned long size, 489 pgprot_t prot) 490 { 491 struct pci_dev *pdev = NULL; 492 struct resource *found = NULL; 493 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 494 int i; 495 496 if (page_is_ram(pfn)) 497 return prot; 498 499 prot = pgprot_noncached(prot); 500 for_each_pci_dev(pdev) { 501 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 502 struct resource *rp = &pdev->resource[i]; 503 int flags = rp->flags; 504 505 /* Active and same type? */ 506 if ((flags & IORESOURCE_MEM) == 0) 507 continue; 508 /* In the range of this resource? */ 509 if (offset < (rp->start & PAGE_MASK) || 510 offset > rp->end) 511 continue; 512 found = rp; 513 break; 514 } 515 if (found) 516 break; 517 } 518 if (found) { 519 if (found->flags & IORESOURCE_PREFETCH) 520 prot = pgprot_noncached_wc(prot); 521 pci_dev_put(pdev); 522 } 523 524 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 525 (unsigned long long)offset, pgprot_val(prot)); 526 527 return prot; 528 } 529 530 531 /* 532 * Perform the actual remap of the pages for a PCI device mapping, as 533 * appropriate for this architecture. The region in the process to map 534 * is described by vm_start and vm_end members of VMA, the base physical 535 * address is found in vm_pgoff. 536 * The pci device structure is provided so that architectures may make mapping 537 * decisions on a per-device or per-bus basis. 538 * 539 * Returns a negative error code on failure, zero on success. 540 */ 541 int pci_mmap_page_range(struct pci_dev *dev, int bar, 542 struct vm_area_struct *vma, 543 enum pci_mmap_state mmap_state, int write_combine) 544 { 545 resource_size_t offset = 546 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 547 struct resource *rp; 548 int ret; 549 550 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 551 if (rp == NULL) 552 return -EINVAL; 553 554 vma->vm_pgoff = offset >> PAGE_SHIFT; 555 if (write_combine) 556 vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot); 557 else 558 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 559 560 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 561 vma->vm_end - vma->vm_start, vma->vm_page_prot); 562 563 return ret; 564 } 565 566 /* This provides legacy IO read access on a bus */ 567 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 568 { 569 unsigned long offset; 570 struct pci_controller *hose = pci_bus_to_host(bus); 571 struct resource *rp = &hose->io_resource; 572 void __iomem *addr; 573 574 /* Check if port can be supported by that bus. We only check 575 * the ranges of the PHB though, not the bus itself as the rules 576 * for forwarding legacy cycles down bridges are not our problem 577 * here. So if the host bridge supports it, we do it. 578 */ 579 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 580 offset += port; 581 582 if (!(rp->flags & IORESOURCE_IO)) 583 return -ENXIO; 584 if (offset < rp->start || (offset + size) > rp->end) 585 return -ENXIO; 586 addr = hose->io_base_virt + port; 587 588 switch(size) { 589 case 1: 590 *((u8 *)val) = in_8(addr); 591 return 1; 592 case 2: 593 if (port & 1) 594 return -EINVAL; 595 *((u16 *)val) = in_le16(addr); 596 return 2; 597 case 4: 598 if (port & 3) 599 return -EINVAL; 600 *((u32 *)val) = in_le32(addr); 601 return 4; 602 } 603 return -EINVAL; 604 } 605 606 /* This provides legacy IO write access on a bus */ 607 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 608 { 609 unsigned long offset; 610 struct pci_controller *hose = pci_bus_to_host(bus); 611 struct resource *rp = &hose->io_resource; 612 void __iomem *addr; 613 614 /* Check if port can be supported by that bus. We only check 615 * the ranges of the PHB though, not the bus itself as the rules 616 * for forwarding legacy cycles down bridges are not our problem 617 * here. So if the host bridge supports it, we do it. 618 */ 619 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 620 offset += port; 621 622 if (!(rp->flags & IORESOURCE_IO)) 623 return -ENXIO; 624 if (offset < rp->start || (offset + size) > rp->end) 625 return -ENXIO; 626 addr = hose->io_base_virt + port; 627 628 /* WARNING: The generic code is idiotic. It gets passed a pointer 629 * to what can be a 1, 2 or 4 byte quantity and always reads that 630 * as a u32, which means that we have to correct the location of 631 * the data read within those 32 bits for size 1 and 2 632 */ 633 switch(size) { 634 case 1: 635 out_8(addr, val >> 24); 636 return 1; 637 case 2: 638 if (port & 1) 639 return -EINVAL; 640 out_le16(addr, val >> 16); 641 return 2; 642 case 4: 643 if (port & 3) 644 return -EINVAL; 645 out_le32(addr, val); 646 return 4; 647 } 648 return -EINVAL; 649 } 650 651 /* This provides legacy IO or memory mmap access on a bus */ 652 int pci_mmap_legacy_page_range(struct pci_bus *bus, 653 struct vm_area_struct *vma, 654 enum pci_mmap_state mmap_state) 655 { 656 struct pci_controller *hose = pci_bus_to_host(bus); 657 resource_size_t offset = 658 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 659 resource_size_t size = vma->vm_end - vma->vm_start; 660 struct resource *rp; 661 662 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 663 pci_domain_nr(bus), bus->number, 664 mmap_state == pci_mmap_mem ? "MEM" : "IO", 665 (unsigned long long)offset, 666 (unsigned long long)(offset + size - 1)); 667 668 if (mmap_state == pci_mmap_mem) { 669 /* Hack alert ! 670 * 671 * Because X is lame and can fail starting if it gets an error trying 672 * to mmap legacy_mem (instead of just moving on without legacy memory 673 * access) we fake it here by giving it anonymous memory, effectively 674 * behaving just like /dev/zero 675 */ 676 if ((offset + size) > hose->isa_mem_size) { 677 printk(KERN_DEBUG 678 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 679 current->comm, current->pid, pci_domain_nr(bus), bus->number); 680 if (vma->vm_flags & VM_SHARED) 681 return shmem_zero_setup(vma); 682 return 0; 683 } 684 offset += hose->isa_mem_phys; 685 } else { 686 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 687 unsigned long roffset = offset + io_offset; 688 rp = &hose->io_resource; 689 if (!(rp->flags & IORESOURCE_IO)) 690 return -ENXIO; 691 if (roffset < rp->start || (roffset + size) > rp->end) 692 return -ENXIO; 693 offset += hose->io_base_phys; 694 } 695 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 696 697 vma->vm_pgoff = offset >> PAGE_SHIFT; 698 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 699 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 700 vma->vm_end - vma->vm_start, 701 vma->vm_page_prot); 702 } 703 704 void pci_resource_to_user(const struct pci_dev *dev, int bar, 705 const struct resource *rsrc, 706 resource_size_t *start, resource_size_t *end) 707 { 708 struct pci_bus_region region; 709 710 if (rsrc->flags & IORESOURCE_IO) { 711 pcibios_resource_to_bus(dev->bus, ®ion, 712 (struct resource *) rsrc); 713 *start = region.start; 714 *end = region.end; 715 return; 716 } 717 718 /* We pass a CPU physical address to userland for MMIO instead of a 719 * BAR value because X is lame and expects to be able to use that 720 * to pass to /dev/mem! 721 * 722 * That means we may have 64-bit values where some apps only expect 723 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). 724 */ 725 *start = rsrc->start; 726 *end = rsrc->end; 727 } 728 729 /** 730 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 731 * @hose: newly allocated pci_controller to be setup 732 * @dev: device node of the host bridge 733 * @primary: set if primary bus (32 bits only, soon to be deprecated) 734 * 735 * This function will parse the "ranges" property of a PCI host bridge device 736 * node and setup the resource mapping of a pci controller based on its 737 * content. 738 * 739 * Life would be boring if it wasn't for a few issues that we have to deal 740 * with here: 741 * 742 * - We can only cope with one IO space range and up to 3 Memory space 743 * ranges. However, some machines (thanks Apple !) tend to split their 744 * space into lots of small contiguous ranges. So we have to coalesce. 745 * 746 * - Some busses have IO space not starting at 0, which causes trouble with 747 * the way we do our IO resource renumbering. The code somewhat deals with 748 * it for 64 bits but I would expect problems on 32 bits. 749 * 750 * - Some 32 bits platforms such as 4xx can have physical space larger than 751 * 32 bits so we need to use 64 bits values for the parsing 752 */ 753 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 754 struct device_node *dev, int primary) 755 { 756 int memno = 0; 757 struct resource *res; 758 struct of_pci_range range; 759 struct of_pci_range_parser parser; 760 761 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n", 762 dev, primary ? "(primary)" : ""); 763 764 /* Check for ranges property */ 765 if (of_pci_range_parser_init(&parser, dev)) 766 return; 767 768 /* Parse it */ 769 for_each_of_pci_range(&parser, &range) { 770 /* If we failed translation or got a zero-sized region 771 * (some FW try to feed us with non sensical zero sized regions 772 * such as power3 which look like some kind of attempt at exposing 773 * the VGA memory hole) 774 */ 775 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 776 continue; 777 778 /* Act based on address space type */ 779 res = NULL; 780 switch (range.flags & IORESOURCE_TYPE_BITS) { 781 case IORESOURCE_IO: 782 printk(KERN_INFO 783 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 784 range.cpu_addr, range.cpu_addr + range.size - 1, 785 range.pci_addr); 786 787 /* We support only one IO range */ 788 if (hose->pci_io_size) { 789 printk(KERN_INFO 790 " \\--> Skipped (too many) !\n"); 791 continue; 792 } 793 #ifdef CONFIG_PPC32 794 /* On 32 bits, limit I/O space to 16MB */ 795 if (range.size > 0x01000000) 796 range.size = 0x01000000; 797 798 /* 32 bits needs to map IOs here */ 799 hose->io_base_virt = ioremap(range.cpu_addr, 800 range.size); 801 802 /* Expect trouble if pci_addr is not 0 */ 803 if (primary) 804 isa_io_base = 805 (unsigned long)hose->io_base_virt; 806 #endif /* CONFIG_PPC32 */ 807 /* pci_io_size and io_base_phys always represent IO 808 * space starting at 0 so we factor in pci_addr 809 */ 810 hose->pci_io_size = range.pci_addr + range.size; 811 hose->io_base_phys = range.cpu_addr - range.pci_addr; 812 813 /* Build resource */ 814 res = &hose->io_resource; 815 range.cpu_addr = range.pci_addr; 816 break; 817 case IORESOURCE_MEM: 818 printk(KERN_INFO 819 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 820 range.cpu_addr, range.cpu_addr + range.size - 1, 821 range.pci_addr, 822 (range.pci_space & 0x40000000) ? 823 "Prefetch" : ""); 824 825 /* We support only 3 memory ranges */ 826 if (memno >= 3) { 827 printk(KERN_INFO 828 " \\--> Skipped (too many) !\n"); 829 continue; 830 } 831 /* Handles ISA memory hole space here */ 832 if (range.pci_addr == 0) { 833 if (primary || isa_mem_base == 0) 834 isa_mem_base = range.cpu_addr; 835 hose->isa_mem_phys = range.cpu_addr; 836 hose->isa_mem_size = range.size; 837 } 838 839 /* Build resource */ 840 hose->mem_offset[memno] = range.cpu_addr - 841 range.pci_addr; 842 res = &hose->mem_resources[memno++]; 843 break; 844 } 845 if (res != NULL) { 846 res->name = dev->full_name; 847 res->flags = range.flags; 848 res->start = range.cpu_addr; 849 res->end = range.cpu_addr + range.size - 1; 850 res->parent = res->child = res->sibling = NULL; 851 } 852 } 853 } 854 855 /* Decide whether to display the domain number in /proc */ 856 int pci_proc_domain(struct pci_bus *bus) 857 { 858 struct pci_controller *hose = pci_bus_to_host(bus); 859 860 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 861 return 0; 862 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 863 return hose->global_number != 0; 864 return 1; 865 } 866 867 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 868 { 869 if (ppc_md.pcibios_root_bridge_prepare) 870 return ppc_md.pcibios_root_bridge_prepare(bridge); 871 872 return 0; 873 } 874 875 /* This header fixup will do the resource fixup for all devices as they are 876 * probed, but not for bridge ranges 877 */ 878 static void pcibios_fixup_resources(struct pci_dev *dev) 879 { 880 struct pci_controller *hose = pci_bus_to_host(dev->bus); 881 int i; 882 883 if (!hose) { 884 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 885 pci_name(dev)); 886 return; 887 } 888 889 if (dev->is_virtfn) 890 return; 891 892 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 893 struct resource *res = dev->resource + i; 894 struct pci_bus_region reg; 895 if (!res->flags) 896 continue; 897 898 /* If we're going to re-assign everything, we mark all resources 899 * as unset (and 0-base them). In addition, we mark BARs starting 900 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 901 * since in that case, we don't want to re-assign anything 902 */ 903 pcibios_resource_to_bus(dev->bus, ®, res); 904 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 905 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 906 /* Only print message if not re-assigning */ 907 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 908 pr_debug("PCI:%s Resource %d %pR is unassigned\n", 909 pci_name(dev), i, res); 910 res->end -= res->start; 911 res->start = 0; 912 res->flags |= IORESOURCE_UNSET; 913 continue; 914 } 915 916 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); 917 } 918 919 /* Call machine specific resource fixup */ 920 if (ppc_md.pcibios_fixup_resources) 921 ppc_md.pcibios_fixup_resources(dev); 922 } 923 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 924 925 /* This function tries to figure out if a bridge resource has been initialized 926 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 927 * things go more smoothly when it gets it right. It should covers cases such 928 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 929 */ 930 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 931 struct resource *res) 932 { 933 struct pci_controller *hose = pci_bus_to_host(bus); 934 struct pci_dev *dev = bus->self; 935 resource_size_t offset; 936 struct pci_bus_region region; 937 u16 command; 938 int i; 939 940 /* We don't do anything if PCI_PROBE_ONLY is set */ 941 if (pci_has_flag(PCI_PROBE_ONLY)) 942 return 0; 943 944 /* Job is a bit different between memory and IO */ 945 if (res->flags & IORESOURCE_MEM) { 946 pcibios_resource_to_bus(dev->bus, ®ion, res); 947 948 /* If the BAR is non-0 then it's probably been initialized */ 949 if (region.start != 0) 950 return 0; 951 952 /* The BAR is 0, let's check if memory decoding is enabled on 953 * the bridge. If not, we consider it unassigned 954 */ 955 pci_read_config_word(dev, PCI_COMMAND, &command); 956 if ((command & PCI_COMMAND_MEMORY) == 0) 957 return 1; 958 959 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 960 * resources covers that starting address (0 then it's good enough for 961 * us for memory space) 962 */ 963 for (i = 0; i < 3; i++) { 964 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 965 hose->mem_resources[i].start == hose->mem_offset[i]) 966 return 0; 967 } 968 969 /* Well, it starts at 0 and we know it will collide so we may as 970 * well consider it as unassigned. That covers the Apple case. 971 */ 972 return 1; 973 } else { 974 /* If the BAR is non-0, then we consider it assigned */ 975 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 976 if (((res->start - offset) & 0xfffffffful) != 0) 977 return 0; 978 979 /* Here, we are a bit different than memory as typically IO space 980 * starting at low addresses -is- valid. What we do instead if that 981 * we consider as unassigned anything that doesn't have IO enabled 982 * in the PCI command register, and that's it. 983 */ 984 pci_read_config_word(dev, PCI_COMMAND, &command); 985 if (command & PCI_COMMAND_IO) 986 return 0; 987 988 /* It's starting at 0 and IO is disabled in the bridge, consider 989 * it unassigned 990 */ 991 return 1; 992 } 993 } 994 995 /* Fixup resources of a PCI<->PCI bridge */ 996 static void pcibios_fixup_bridge(struct pci_bus *bus) 997 { 998 struct resource *res; 999 int i; 1000 1001 struct pci_dev *dev = bus->self; 1002 1003 pci_bus_for_each_resource(bus, res, i) { 1004 if (!res || !res->flags) 1005 continue; 1006 if (i >= 3 && bus->self->transparent) 1007 continue; 1008 1009 /* If we're going to reassign everything, we can 1010 * shrink the P2P resource to have size as being 1011 * of 0 in order to save space. 1012 */ 1013 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1014 res->flags |= IORESOURCE_UNSET; 1015 res->start = 0; 1016 res->end = -1; 1017 continue; 1018 } 1019 1020 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); 1021 1022 /* Try to detect uninitialized P2P bridge resources, 1023 * and clear them out so they get re-assigned later 1024 */ 1025 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1026 res->flags = 0; 1027 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1028 } 1029 } 1030 } 1031 1032 void pcibios_setup_bus_self(struct pci_bus *bus) 1033 { 1034 struct pci_controller *phb; 1035 1036 /* Fix up the bus resources for P2P bridges */ 1037 if (bus->self != NULL) 1038 pcibios_fixup_bridge(bus); 1039 1040 /* Platform specific bus fixups. This is currently only used 1041 * by fsl_pci and I'm hoping to get rid of it at some point 1042 */ 1043 if (ppc_md.pcibios_fixup_bus) 1044 ppc_md.pcibios_fixup_bus(bus); 1045 1046 /* Setup bus DMA mappings */ 1047 phb = pci_bus_to_host(bus); 1048 if (phb->controller_ops.dma_bus_setup) 1049 phb->controller_ops.dma_bus_setup(bus); 1050 } 1051 1052 static void pcibios_setup_device(struct pci_dev *dev) 1053 { 1054 struct pci_controller *phb; 1055 /* Fixup NUMA node as it may not be setup yet by the generic 1056 * code and is needed by the DMA init 1057 */ 1058 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1059 1060 /* Hook up default DMA ops */ 1061 set_dma_ops(&dev->dev, pci_dma_ops); 1062 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1063 1064 /* Additional platform DMA/iommu setup */ 1065 phb = pci_bus_to_host(dev->bus); 1066 if (phb->controller_ops.dma_dev_setup) 1067 phb->controller_ops.dma_dev_setup(dev); 1068 1069 /* Read default IRQs and fixup if necessary */ 1070 pci_read_irq_line(dev); 1071 if (ppc_md.pci_irq_fixup) 1072 ppc_md.pci_irq_fixup(dev); 1073 } 1074 1075 int pcibios_add_device(struct pci_dev *dev) 1076 { 1077 /* 1078 * We can only call pcibios_setup_device() after bus setup is complete, 1079 * since some of the platform specific DMA setup code depends on it. 1080 */ 1081 if (dev->bus->is_added) 1082 pcibios_setup_device(dev); 1083 1084 #ifdef CONFIG_PCI_IOV 1085 if (ppc_md.pcibios_fixup_sriov) 1086 ppc_md.pcibios_fixup_sriov(dev); 1087 #endif /* CONFIG_PCI_IOV */ 1088 1089 return 0; 1090 } 1091 1092 void pcibios_setup_bus_devices(struct pci_bus *bus) 1093 { 1094 struct pci_dev *dev; 1095 1096 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1097 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1098 1099 list_for_each_entry(dev, &bus->devices, bus_list) { 1100 /* Cardbus can call us to add new devices to a bus, so ignore 1101 * those who are already fully discovered 1102 */ 1103 if (dev->is_added) 1104 continue; 1105 1106 pcibios_setup_device(dev); 1107 } 1108 } 1109 1110 void pcibios_set_master(struct pci_dev *dev) 1111 { 1112 /* No special bus mastering setup handling */ 1113 } 1114 1115 void pcibios_fixup_bus(struct pci_bus *bus) 1116 { 1117 /* When called from the generic PCI probe, read PCI<->PCI bridge 1118 * bases. This is -not- called when generating the PCI tree from 1119 * the OF device-tree. 1120 */ 1121 pci_read_bridge_bases(bus); 1122 1123 /* Now fixup the bus bus */ 1124 pcibios_setup_bus_self(bus); 1125 1126 /* Now fixup devices on that bus */ 1127 pcibios_setup_bus_devices(bus); 1128 } 1129 EXPORT_SYMBOL(pcibios_fixup_bus); 1130 1131 void pci_fixup_cardbus(struct pci_bus *bus) 1132 { 1133 /* Now fixup devices on that bus */ 1134 pcibios_setup_bus_devices(bus); 1135 } 1136 1137 1138 static int skip_isa_ioresource_align(struct pci_dev *dev) 1139 { 1140 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1141 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1142 return 1; 1143 return 0; 1144 } 1145 1146 /* 1147 * We need to avoid collisions with `mirrored' VGA ports 1148 * and other strange ISA hardware, so we always want the 1149 * addresses to be allocated in the 0x000-0x0ff region 1150 * modulo 0x400. 1151 * 1152 * Why? Because some silly external IO cards only decode 1153 * the low 10 bits of the IO address. The 0x00-0xff region 1154 * is reserved for motherboard devices that decode all 16 1155 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1156 * but we want to try to avoid allocating at 0x2900-0x2bff 1157 * which might have be mirrored at 0x0100-0x03ff.. 1158 */ 1159 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1160 resource_size_t size, resource_size_t align) 1161 { 1162 struct pci_dev *dev = data; 1163 resource_size_t start = res->start; 1164 1165 if (res->flags & IORESOURCE_IO) { 1166 if (skip_isa_ioresource_align(dev)) 1167 return start; 1168 if (start & 0x300) 1169 start = (start + 0x3ff) & ~0x3ff; 1170 } 1171 1172 return start; 1173 } 1174 EXPORT_SYMBOL(pcibios_align_resource); 1175 1176 /* 1177 * Reparent resource children of pr that conflict with res 1178 * under res, and make res replace those children. 1179 */ 1180 static int reparent_resources(struct resource *parent, 1181 struct resource *res) 1182 { 1183 struct resource *p, **pp; 1184 struct resource **firstpp = NULL; 1185 1186 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1187 if (p->end < res->start) 1188 continue; 1189 if (res->end < p->start) 1190 break; 1191 if (p->start < res->start || p->end > res->end) 1192 return -1; /* not completely contained */ 1193 if (firstpp == NULL) 1194 firstpp = pp; 1195 } 1196 if (firstpp == NULL) 1197 return -1; /* didn't find any conflicting entries? */ 1198 res->parent = parent; 1199 res->child = *firstpp; 1200 res->sibling = *pp; 1201 *firstpp = res; 1202 *pp = NULL; 1203 for (p = res->child; p != NULL; p = p->sibling) { 1204 p->parent = res; 1205 pr_debug("PCI: Reparented %s %pR under %s\n", 1206 p->name, p, res->name); 1207 } 1208 return 0; 1209 } 1210 1211 /* 1212 * Handle resources of PCI devices. If the world were perfect, we could 1213 * just allocate all the resource regions and do nothing more. It isn't. 1214 * On the other hand, we cannot just re-allocate all devices, as it would 1215 * require us to know lots of host bridge internals. So we attempt to 1216 * keep as much of the original configuration as possible, but tweak it 1217 * when it's found to be wrong. 1218 * 1219 * Known BIOS problems we have to work around: 1220 * - I/O or memory regions not configured 1221 * - regions configured, but not enabled in the command register 1222 * - bogus I/O addresses above 64K used 1223 * - expansion ROMs left enabled (this may sound harmless, but given 1224 * the fact the PCI specs explicitly allow address decoders to be 1225 * shared between expansion ROMs and other resource regions, it's 1226 * at least dangerous) 1227 * 1228 * Our solution: 1229 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1230 * This gives us fixed barriers on where we can allocate. 1231 * (2) Allocate resources for all enabled devices. If there is 1232 * a collision, just mark the resource as unallocated. Also 1233 * disable expansion ROMs during this step. 1234 * (3) Try to allocate resources for disabled devices. If the 1235 * resources were assigned correctly, everything goes well, 1236 * if they weren't, they won't disturb allocation of other 1237 * resources. 1238 * (4) Assign new addresses to resources which were either 1239 * not configured at all or misconfigured. If explicitly 1240 * requested by the user, configure expansion ROM address 1241 * as well. 1242 */ 1243 1244 static void pcibios_allocate_bus_resources(struct pci_bus *bus) 1245 { 1246 struct pci_bus *b; 1247 int i; 1248 struct resource *res, *pr; 1249 1250 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1251 pci_domain_nr(bus), bus->number); 1252 1253 pci_bus_for_each_resource(bus, res, i) { 1254 if (!res || !res->flags || res->start > res->end || res->parent) 1255 continue; 1256 1257 /* If the resource was left unset at this point, we clear it */ 1258 if (res->flags & IORESOURCE_UNSET) 1259 goto clear_resource; 1260 1261 if (bus->parent == NULL) 1262 pr = (res->flags & IORESOURCE_IO) ? 1263 &ioport_resource : &iomem_resource; 1264 else { 1265 pr = pci_find_parent_resource(bus->self, res); 1266 if (pr == res) { 1267 /* this happens when the generic PCI 1268 * code (wrongly) decides that this 1269 * bridge is transparent -- paulus 1270 */ 1271 continue; 1272 } 1273 } 1274 1275 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", 1276 bus->self ? pci_name(bus->self) : "PHB", bus->number, 1277 i, res, pr, (pr && pr->name) ? pr->name : "nil"); 1278 1279 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1280 struct pci_dev *dev = bus->self; 1281 1282 if (request_resource(pr, res) == 0) 1283 continue; 1284 /* 1285 * Must be a conflict with an existing entry. 1286 * Move that entry (or entries) under the 1287 * bridge resource and try again. 1288 */ 1289 if (reparent_resources(pr, res) == 0) 1290 continue; 1291 1292 if (dev && i < PCI_BRIDGE_RESOURCE_NUM && 1293 pci_claim_bridge_resource(dev, 1294 i + PCI_BRIDGE_RESOURCES) == 0) 1295 continue; 1296 } 1297 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n", 1298 i, bus->number); 1299 clear_resource: 1300 /* The resource might be figured out when doing 1301 * reassignment based on the resources required 1302 * by the downstream PCI devices. Here we set 1303 * the size of the resource to be 0 in order to 1304 * save more space. 1305 */ 1306 res->start = 0; 1307 res->end = -1; 1308 res->flags = 0; 1309 } 1310 1311 list_for_each_entry(b, &bus->children, node) 1312 pcibios_allocate_bus_resources(b); 1313 } 1314 1315 static inline void alloc_resource(struct pci_dev *dev, int idx) 1316 { 1317 struct resource *pr, *r = &dev->resource[idx]; 1318 1319 pr_debug("PCI: Allocating %s: Resource %d: %pR\n", 1320 pci_name(dev), idx, r); 1321 1322 pr = pci_find_parent_resource(dev, r); 1323 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1324 request_resource(pr, r) < 0) { 1325 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1326 " of device %s, will remap\n", idx, pci_name(dev)); 1327 if (pr) 1328 pr_debug("PCI: parent is %p: %pR\n", pr, pr); 1329 /* We'll assign a new address later */ 1330 r->flags |= IORESOURCE_UNSET; 1331 r->end -= r->start; 1332 r->start = 0; 1333 } 1334 } 1335 1336 static void __init pcibios_allocate_resources(int pass) 1337 { 1338 struct pci_dev *dev = NULL; 1339 int idx, disabled; 1340 u16 command; 1341 struct resource *r; 1342 1343 for_each_pci_dev(dev) { 1344 pci_read_config_word(dev, PCI_COMMAND, &command); 1345 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1346 r = &dev->resource[idx]; 1347 if (r->parent) /* Already allocated */ 1348 continue; 1349 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1350 continue; /* Not assigned at all */ 1351 /* We only allocate ROMs on pass 1 just in case they 1352 * have been screwed up by firmware 1353 */ 1354 if (idx == PCI_ROM_RESOURCE ) 1355 disabled = 1; 1356 if (r->flags & IORESOURCE_IO) 1357 disabled = !(command & PCI_COMMAND_IO); 1358 else 1359 disabled = !(command & PCI_COMMAND_MEMORY); 1360 if (pass == disabled) 1361 alloc_resource(dev, idx); 1362 } 1363 if (pass) 1364 continue; 1365 r = &dev->resource[PCI_ROM_RESOURCE]; 1366 if (r->flags) { 1367 /* Turn the ROM off, leave the resource region, 1368 * but keep it unregistered. 1369 */ 1370 u32 reg; 1371 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1372 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1373 pr_debug("PCI: Switching off ROM of %s\n", 1374 pci_name(dev)); 1375 r->flags &= ~IORESOURCE_ROM_ENABLE; 1376 pci_write_config_dword(dev, dev->rom_base_reg, 1377 reg & ~PCI_ROM_ADDRESS_ENABLE); 1378 } 1379 } 1380 } 1381 } 1382 1383 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1384 { 1385 struct pci_controller *hose = pci_bus_to_host(bus); 1386 resource_size_t offset; 1387 struct resource *res, *pres; 1388 int i; 1389 1390 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1391 1392 /* Check for IO */ 1393 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1394 goto no_io; 1395 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1396 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1397 BUG_ON(res == NULL); 1398 res->name = "Legacy IO"; 1399 res->flags = IORESOURCE_IO; 1400 res->start = offset; 1401 res->end = (offset + 0xfff) & 0xfffffffful; 1402 pr_debug("Candidate legacy IO: %pR\n", res); 1403 if (request_resource(&hose->io_resource, res)) { 1404 printk(KERN_DEBUG 1405 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1406 pci_domain_nr(bus), bus->number, res); 1407 kfree(res); 1408 } 1409 1410 no_io: 1411 /* Check for memory */ 1412 for (i = 0; i < 3; i++) { 1413 pres = &hose->mem_resources[i]; 1414 offset = hose->mem_offset[i]; 1415 if (!(pres->flags & IORESOURCE_MEM)) 1416 continue; 1417 pr_debug("hose mem res: %pR\n", pres); 1418 if ((pres->start - offset) <= 0xa0000 && 1419 (pres->end - offset) >= 0xbffff) 1420 break; 1421 } 1422 if (i >= 3) 1423 return; 1424 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1425 BUG_ON(res == NULL); 1426 res->name = "Legacy VGA memory"; 1427 res->flags = IORESOURCE_MEM; 1428 res->start = 0xa0000 + offset; 1429 res->end = 0xbffff + offset; 1430 pr_debug("Candidate VGA memory: %pR\n", res); 1431 if (request_resource(pres, res)) { 1432 printk(KERN_DEBUG 1433 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1434 pci_domain_nr(bus), bus->number, res); 1435 kfree(res); 1436 } 1437 } 1438 1439 void __init pcibios_resource_survey(void) 1440 { 1441 struct pci_bus *b; 1442 1443 /* Allocate and assign resources */ 1444 list_for_each_entry(b, &pci_root_buses, node) 1445 pcibios_allocate_bus_resources(b); 1446 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1447 pcibios_allocate_resources(0); 1448 pcibios_allocate_resources(1); 1449 } 1450 1451 /* Before we start assigning unassigned resource, we try to reserve 1452 * the low IO area and the VGA memory area if they intersect the 1453 * bus available resources to avoid allocating things on top of them 1454 */ 1455 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1456 list_for_each_entry(b, &pci_root_buses, node) 1457 pcibios_reserve_legacy_regions(b); 1458 } 1459 1460 /* Now, if the platform didn't decide to blindly trust the firmware, 1461 * we proceed to assigning things that were left unassigned 1462 */ 1463 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1464 pr_debug("PCI: Assigning unassigned resources...\n"); 1465 pci_assign_unassigned_resources(); 1466 } 1467 1468 /* Call machine dependent fixup */ 1469 if (ppc_md.pcibios_fixup) 1470 ppc_md.pcibios_fixup(); 1471 } 1472 1473 /* This is used by the PCI hotplug driver to allocate resource 1474 * of newly plugged busses. We can try to consolidate with the 1475 * rest of the code later, for now, keep it as-is as our main 1476 * resource allocation function doesn't deal with sub-trees yet. 1477 */ 1478 void pcibios_claim_one_bus(struct pci_bus *bus) 1479 { 1480 struct pci_dev *dev; 1481 struct pci_bus *child_bus; 1482 1483 list_for_each_entry(dev, &bus->devices, bus_list) { 1484 int i; 1485 1486 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1487 struct resource *r = &dev->resource[i]; 1488 1489 if (r->parent || !r->start || !r->flags) 1490 continue; 1491 1492 pr_debug("PCI: Claiming %s: Resource %d: %pR\n", 1493 pci_name(dev), i, r); 1494 1495 if (pci_claim_resource(dev, i) == 0) 1496 continue; 1497 1498 pci_claim_bridge_resource(dev, i); 1499 } 1500 } 1501 1502 list_for_each_entry(child_bus, &bus->children, node) 1503 pcibios_claim_one_bus(child_bus); 1504 } 1505 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1506 1507 1508 /* pcibios_finish_adding_to_bus 1509 * 1510 * This is to be called by the hotplug code after devices have been 1511 * added to a bus, this include calling it for a PHB that is just 1512 * being added 1513 */ 1514 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1515 { 1516 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1517 pci_domain_nr(bus), bus->number); 1518 1519 /* Allocate bus and devices resources */ 1520 pcibios_allocate_bus_resources(bus); 1521 pcibios_claim_one_bus(bus); 1522 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1523 if (bus->self) 1524 pci_assign_unassigned_bridge_resources(bus->self); 1525 else 1526 pci_assign_unassigned_bus_resources(bus); 1527 } 1528 1529 /* Fixup EEH */ 1530 eeh_add_device_tree_late(bus); 1531 1532 /* Add new devices to global lists. Register in proc, sysfs. */ 1533 pci_bus_add_devices(bus); 1534 1535 /* sysfs files should only be added after devices are added */ 1536 eeh_add_sysfs_files(bus); 1537 } 1538 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1539 1540 int pcibios_enable_device(struct pci_dev *dev, int mask) 1541 { 1542 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1543 1544 if (phb->controller_ops.enable_device_hook) 1545 if (!phb->controller_ops.enable_device_hook(dev)) 1546 return -EINVAL; 1547 1548 return pci_enable_resources(dev, mask); 1549 } 1550 1551 void pcibios_disable_device(struct pci_dev *dev) 1552 { 1553 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1554 1555 if (phb->controller_ops.disable_device) 1556 phb->controller_ops.disable_device(dev); 1557 } 1558 1559 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1560 { 1561 return (unsigned long) hose->io_base_virt - _IO_BASE; 1562 } 1563 1564 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1565 struct list_head *resources) 1566 { 1567 struct resource *res; 1568 resource_size_t offset; 1569 int i; 1570 1571 /* Hookup PHB IO resource */ 1572 res = &hose->io_resource; 1573 1574 if (!res->flags) { 1575 pr_debug("PCI: I/O resource not set for host" 1576 " bridge %pOF (domain %d)\n", 1577 hose->dn, hose->global_number); 1578 } else { 1579 offset = pcibios_io_space_offset(hose); 1580 1581 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", 1582 res, (unsigned long long)offset); 1583 pci_add_resource_offset(resources, res, offset); 1584 } 1585 1586 /* Hookup PHB Memory resources */ 1587 for (i = 0; i < 3; ++i) { 1588 res = &hose->mem_resources[i]; 1589 if (!res->flags) 1590 continue; 1591 1592 offset = hose->mem_offset[i]; 1593 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, 1594 res, (unsigned long long)offset); 1595 1596 pci_add_resource_offset(resources, res, offset); 1597 } 1598 } 1599 1600 /* 1601 * Null PCI config access functions, for the case when we can't 1602 * find a hose. 1603 */ 1604 #define NULL_PCI_OP(rw, size, type) \ 1605 static int \ 1606 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1607 { \ 1608 return PCIBIOS_DEVICE_NOT_FOUND; \ 1609 } 1610 1611 static int 1612 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1613 int len, u32 *val) 1614 { 1615 return PCIBIOS_DEVICE_NOT_FOUND; 1616 } 1617 1618 static int 1619 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1620 int len, u32 val) 1621 { 1622 return PCIBIOS_DEVICE_NOT_FOUND; 1623 } 1624 1625 static struct pci_ops null_pci_ops = 1626 { 1627 .read = null_read_config, 1628 .write = null_write_config, 1629 }; 1630 1631 /* 1632 * These functions are used early on before PCI scanning is done 1633 * and all of the pci_dev and pci_bus structures have been created. 1634 */ 1635 static struct pci_bus * 1636 fake_pci_bus(struct pci_controller *hose, int busnr) 1637 { 1638 static struct pci_bus bus; 1639 1640 if (hose == NULL) { 1641 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1642 } 1643 bus.number = busnr; 1644 bus.sysdata = hose; 1645 bus.ops = hose? hose->ops: &null_pci_ops; 1646 return &bus; 1647 } 1648 1649 #define EARLY_PCI_OP(rw, size, type) \ 1650 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1651 int devfn, int offset, type value) \ 1652 { \ 1653 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1654 devfn, offset, value); \ 1655 } 1656 1657 EARLY_PCI_OP(read, byte, u8 *) 1658 EARLY_PCI_OP(read, word, u16 *) 1659 EARLY_PCI_OP(read, dword, u32 *) 1660 EARLY_PCI_OP(write, byte, u8) 1661 EARLY_PCI_OP(write, word, u16) 1662 EARLY_PCI_OP(write, dword, u32) 1663 1664 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1665 int cap) 1666 { 1667 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1668 } 1669 1670 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1671 { 1672 struct pci_controller *hose = bus->sysdata; 1673 1674 return of_node_get(hose->dn); 1675 } 1676 1677 /** 1678 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1679 * @hose: Pointer to the PCI host controller instance structure 1680 */ 1681 void pcibios_scan_phb(struct pci_controller *hose) 1682 { 1683 LIST_HEAD(resources); 1684 struct pci_bus *bus; 1685 struct device_node *node = hose->dn; 1686 int mode; 1687 1688 pr_debug("PCI: Scanning PHB %pOF\n", node); 1689 1690 /* Get some IO space for the new PHB */ 1691 pcibios_setup_phb_io_space(hose); 1692 1693 /* Wire up PHB bus resources */ 1694 pcibios_setup_phb_resources(hose, &resources); 1695 1696 hose->busn.start = hose->first_busno; 1697 hose->busn.end = hose->last_busno; 1698 hose->busn.flags = IORESOURCE_BUS; 1699 pci_add_resource(&resources, &hose->busn); 1700 1701 /* Create an empty bus for the toplevel */ 1702 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1703 hose->ops, hose, &resources); 1704 if (bus == NULL) { 1705 pr_err("Failed to create bus for PCI domain %04x\n", 1706 hose->global_number); 1707 pci_free_resource_list(&resources); 1708 return; 1709 } 1710 hose->bus = bus; 1711 1712 /* Get probe mode and perform scan */ 1713 mode = PCI_PROBE_NORMAL; 1714 if (node && hose->controller_ops.probe_mode) 1715 mode = hose->controller_ops.probe_mode(bus); 1716 pr_debug(" probe mode: %d\n", mode); 1717 if (mode == PCI_PROBE_DEVTREE) 1718 of_scan_bus(node, bus); 1719 1720 if (mode == PCI_PROBE_NORMAL) { 1721 pci_bus_update_busn_res_end(bus, 255); 1722 hose->last_busno = pci_scan_child_bus(bus); 1723 pci_bus_update_busn_res_end(bus, hose->last_busno); 1724 } 1725 1726 /* Platform gets a chance to do some global fixups before 1727 * we proceed to resource allocation 1728 */ 1729 if (ppc_md.pcibios_fixup_phb) 1730 ppc_md.pcibios_fixup_phb(hose); 1731 1732 /* Configure PCI Express settings */ 1733 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1734 struct pci_bus *child; 1735 list_for_each_entry(child, &bus->children, node) 1736 pcie_bus_configure_settings(child); 1737 } 1738 } 1739 EXPORT_SYMBOL_GPL(pcibios_scan_phb); 1740 1741 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1742 { 1743 int i, class = dev->class >> 8; 1744 /* When configured as agent, programing interface = 1 */ 1745 int prog_if = dev->class & 0xf; 1746 1747 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1748 class == PCI_CLASS_BRIDGE_OTHER) && 1749 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1750 (prog_if == 0) && 1751 (dev->bus->parent == NULL)) { 1752 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1753 dev->resource[i].start = 0; 1754 dev->resource[i].end = 0; 1755 dev->resource[i].flags = 0; 1756 } 1757 } 1758 } 1759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1761