1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Contains common pci routines for ALL ppc platform 4 * (based on pci_32.c and pci_64.c) 5 * 6 * Port for PPC64 David Engebretsen, IBM Corp. 7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 8 * 9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 10 * Rework, based on alpha PCI code. 11 * 12 * Common pmac/prep/chrp pci routines. -- Cort 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/string.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/export.h> 21 #include <linux/of_address.h> 22 #include <linux/of_pci.h> 23 #include <linux/mm.h> 24 #include <linux/shmem_fs.h> 25 #include <linux/list.h> 26 #include <linux/syscalls.h> 27 #include <linux/irq.h> 28 #include <linux/vmalloc.h> 29 #include <linux/slab.h> 30 #include <linux/vgaarb.h> 31 #include <linux/numa.h> 32 #include <linux/msi.h> 33 #include <linux/irqdomain.h> 34 35 #include <asm/processor.h> 36 #include <asm/io.h> 37 #include <asm/pci-bridge.h> 38 #include <asm/byteorder.h> 39 #include <asm/machdep.h> 40 #include <asm/ppc-pci.h> 41 #include <asm/eeh.h> 42 #include <asm/setup.h> 43 44 #include "../../../drivers/pci/pci.h" 45 46 /* hose_spinlock protects accesses to the phb_bitmap. */ 47 static DEFINE_SPINLOCK(hose_spinlock); 48 LIST_HEAD(hose_list); 49 50 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */ 51 #define MAX_PHBS 0x10000 52 53 /* 54 * For dynamic PHB numbering: used/free PHBs tracking bitmap. 55 * Accesses to this bitmap should be protected by hose_spinlock. 56 */ 57 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS); 58 59 /* ISA Memory physical address */ 60 resource_size_t isa_mem_base; 61 EXPORT_SYMBOL(isa_mem_base); 62 63 64 static const struct dma_map_ops *pci_dma_ops; 65 66 void __init set_pci_dma_ops(const struct dma_map_ops *dma_ops) 67 { 68 pci_dma_ops = dma_ops; 69 } 70 71 /* 72 * This function should run under locking protection, specifically 73 * hose_spinlock. 74 */ 75 static int get_phb_number(struct device_node *dn) 76 { 77 int ret, phb_id = -1; 78 u64 prop; 79 80 /* 81 * Try fixed PHB numbering first, by checking archs and reading 82 * the respective device-tree properties. Firstly, try reading 83 * standard "linux,pci-domain", then try reading "ibm,opal-phbid" 84 * (only present in powernv OPAL environment), then try device-tree 85 * alias and as the last try to use lower bits of "reg" property. 86 */ 87 ret = of_get_pci_domain_nr(dn); 88 if (ret >= 0) { 89 prop = ret; 90 ret = 0; 91 } 92 if (ret) 93 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); 94 95 if (ret) { 96 ret = of_alias_get_id(dn, "pci"); 97 if (ret >= 0) { 98 prop = ret; 99 ret = 0; 100 } 101 } 102 if (ret) { 103 u32 prop_32; 104 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32); 105 prop = prop_32; 106 } 107 108 if (!ret) 109 phb_id = (int)(prop & (MAX_PHBS - 1)); 110 111 /* We need to be sure to not use the same PHB number twice. */ 112 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap)) 113 return phb_id; 114 115 /* If everything fails then fallback to dynamic PHB numbering. */ 116 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS); 117 BUG_ON(phb_id >= MAX_PHBS); 118 set_bit(phb_id, phb_bitmap); 119 120 return phb_id; 121 } 122 123 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 124 { 125 struct pci_controller *phb; 126 127 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 128 if (phb == NULL) 129 return NULL; 130 spin_lock(&hose_spinlock); 131 phb->global_number = get_phb_number(dev); 132 list_add_tail(&phb->list_node, &hose_list); 133 spin_unlock(&hose_spinlock); 134 phb->dn = dev; 135 phb->is_dynamic = slab_is_available(); 136 #ifdef CONFIG_PPC64 137 if (dev) { 138 int nid = of_node_to_nid(dev); 139 140 if (nid < 0 || !node_online(nid)) 141 nid = NUMA_NO_NODE; 142 143 PHB_SET_NODE(phb, nid); 144 } 145 #endif 146 return phb; 147 } 148 EXPORT_SYMBOL_GPL(pcibios_alloc_controller); 149 150 void pcibios_free_controller(struct pci_controller *phb) 151 { 152 spin_lock(&hose_spinlock); 153 154 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ 155 if (phb->global_number < MAX_PHBS) 156 clear_bit(phb->global_number, phb_bitmap); 157 158 list_del(&phb->list_node); 159 spin_unlock(&hose_spinlock); 160 161 if (phb->is_dynamic) 162 kfree(phb); 163 } 164 EXPORT_SYMBOL_GPL(pcibios_free_controller); 165 166 /* 167 * This function is used to call pcibios_free_controller() 168 * in a deferred manner: a callback from the PCI subsystem. 169 * 170 * _*DO NOT*_ call pcibios_free_controller() explicitly if 171 * this is used (or it may access an invalid *phb pointer). 172 * 173 * The callback occurs when all references to the root bus 174 * are dropped (e.g., child buses/devices and their users). 175 * 176 * It's called as .release_fn() of 'struct pci_host_bridge' 177 * which is associated with the 'struct pci_controller.bus' 178 * (root bus) - it expects .release_data to hold a pointer 179 * to 'struct pci_controller'. 180 * 181 * In order to use it, register .release_fn()/release_data 182 * like this: 183 * 184 * pci_set_host_bridge_release(bridge, 185 * pcibios_free_controller_deferred 186 * (void *) phb); 187 * 188 * e.g. in the pcibios_root_bridge_prepare() callback from 189 * pci_create_root_bus(). 190 */ 191 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge) 192 { 193 struct pci_controller *phb = (struct pci_controller *) 194 bridge->release_data; 195 196 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); 197 198 pcibios_free_controller(phb); 199 } 200 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred); 201 202 /* 203 * The function is used to return the minimal alignment 204 * for memory or I/O windows of the associated P2P bridge. 205 * By default, 4KiB alignment for I/O windows and 1MiB for 206 * memory windows. 207 */ 208 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 209 unsigned long type) 210 { 211 struct pci_controller *phb = pci_bus_to_host(bus); 212 213 if (phb->controller_ops.window_alignment) 214 return phb->controller_ops.window_alignment(bus, type); 215 216 /* 217 * PCI core will figure out the default 218 * alignment: 4KiB for I/O and 1MiB for 219 * memory window. 220 */ 221 return 1; 222 } 223 224 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 225 { 226 struct pci_controller *hose = pci_bus_to_host(bus); 227 228 if (hose->controller_ops.setup_bridge) 229 hose->controller_ops.setup_bridge(bus, type); 230 } 231 232 void pcibios_reset_secondary_bus(struct pci_dev *dev) 233 { 234 struct pci_controller *phb = pci_bus_to_host(dev->bus); 235 236 if (phb->controller_ops.reset_secondary_bus) { 237 phb->controller_ops.reset_secondary_bus(dev); 238 return; 239 } 240 241 pci_reset_secondary_bus(dev); 242 } 243 244 resource_size_t pcibios_default_alignment(void) 245 { 246 if (ppc_md.pcibios_default_alignment) 247 return ppc_md.pcibios_default_alignment(); 248 249 return 0; 250 } 251 252 #ifdef CONFIG_PCI_IOV 253 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) 254 { 255 if (ppc_md.pcibios_iov_resource_alignment) 256 return ppc_md.pcibios_iov_resource_alignment(pdev, resno); 257 258 return pci_iov_resource_size(pdev, resno); 259 } 260 261 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 262 { 263 if (ppc_md.pcibios_sriov_enable) 264 return ppc_md.pcibios_sriov_enable(pdev, num_vfs); 265 266 return 0; 267 } 268 269 int pcibios_sriov_disable(struct pci_dev *pdev) 270 { 271 if (ppc_md.pcibios_sriov_disable) 272 return ppc_md.pcibios_sriov_disable(pdev); 273 274 return 0; 275 } 276 277 #endif /* CONFIG_PCI_IOV */ 278 279 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 280 { 281 #ifdef CONFIG_PPC64 282 return hose->pci_io_size; 283 #else 284 return resource_size(&hose->io_resource); 285 #endif 286 } 287 288 int pcibios_vaddr_is_ioport(void __iomem *address) 289 { 290 int ret = 0; 291 struct pci_controller *hose; 292 resource_size_t size; 293 294 spin_lock(&hose_spinlock); 295 list_for_each_entry(hose, &hose_list, list_node) { 296 size = pcibios_io_size(hose); 297 if (address >= hose->io_base_virt && 298 address < (hose->io_base_virt + size)) { 299 ret = 1; 300 break; 301 } 302 } 303 spin_unlock(&hose_spinlock); 304 return ret; 305 } 306 307 unsigned long pci_address_to_pio(phys_addr_t address) 308 { 309 struct pci_controller *hose; 310 resource_size_t size; 311 unsigned long ret = ~0; 312 313 spin_lock(&hose_spinlock); 314 list_for_each_entry(hose, &hose_list, list_node) { 315 size = pcibios_io_size(hose); 316 if (address >= hose->io_base_phys && 317 address < (hose->io_base_phys + size)) { 318 unsigned long base = 319 (unsigned long)hose->io_base_virt - _IO_BASE; 320 ret = base + (address - hose->io_base_phys); 321 break; 322 } 323 } 324 spin_unlock(&hose_spinlock); 325 326 return ret; 327 } 328 EXPORT_SYMBOL_GPL(pci_address_to_pio); 329 330 /* 331 * Return the domain number for this bus. 332 */ 333 int pci_domain_nr(struct pci_bus *bus) 334 { 335 struct pci_controller *hose = pci_bus_to_host(bus); 336 337 return hose->global_number; 338 } 339 EXPORT_SYMBOL(pci_domain_nr); 340 341 /* This routine is meant to be used early during boot, when the 342 * PCI bus numbers have not yet been assigned, and you need to 343 * issue PCI config cycles to an OF device. 344 * It could also be used to "fix" RTAS config cycles if you want 345 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 346 * config cycles. 347 */ 348 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 349 { 350 while(node) { 351 struct pci_controller *hose, *tmp; 352 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 353 if (hose->dn == node) 354 return hose; 355 node = node->parent; 356 } 357 return NULL; 358 } 359 360 struct pci_controller *pci_find_controller_for_domain(int domain_nr) 361 { 362 struct pci_controller *hose; 363 364 list_for_each_entry(hose, &hose_list, list_node) 365 if (hose->global_number == domain_nr) 366 return hose; 367 368 return NULL; 369 } 370 371 struct pci_intx_virq { 372 int virq; 373 struct kref kref; 374 struct list_head list_node; 375 }; 376 377 static LIST_HEAD(intx_list); 378 static DEFINE_MUTEX(intx_mutex); 379 380 static void ppc_pci_intx_release(struct kref *kref) 381 { 382 struct pci_intx_virq *vi = container_of(kref, struct pci_intx_virq, kref); 383 384 list_del(&vi->list_node); 385 irq_dispose_mapping(vi->virq); 386 kfree(vi); 387 } 388 389 static int ppc_pci_unmap_irq_line(struct notifier_block *nb, 390 unsigned long action, void *data) 391 { 392 struct pci_dev *pdev = to_pci_dev(data); 393 394 if (action == BUS_NOTIFY_DEL_DEVICE) { 395 struct pci_intx_virq *vi; 396 397 mutex_lock(&intx_mutex); 398 list_for_each_entry(vi, &intx_list, list_node) { 399 if (vi->virq == pdev->irq) { 400 kref_put(&vi->kref, ppc_pci_intx_release); 401 break; 402 } 403 } 404 mutex_unlock(&intx_mutex); 405 } 406 407 return NOTIFY_DONE; 408 } 409 410 static struct notifier_block ppc_pci_unmap_irq_notifier = { 411 .notifier_call = ppc_pci_unmap_irq_line, 412 }; 413 414 static int ppc_pci_register_irq_notifier(void) 415 { 416 return bus_register_notifier(&pci_bus_type, &ppc_pci_unmap_irq_notifier); 417 } 418 arch_initcall(ppc_pci_register_irq_notifier); 419 420 /* 421 * Reads the interrupt pin to determine if interrupt is use by card. 422 * If the interrupt is used, then gets the interrupt line from the 423 * openfirmware and sets it in the pci_dev and pci_config line. 424 */ 425 static int pci_read_irq_line(struct pci_dev *pci_dev) 426 { 427 int virq; 428 struct pci_intx_virq *vi, *vitmp; 429 430 /* Preallocate vi as rewind is complex if this fails after mapping */ 431 vi = kzalloc(sizeof(struct pci_intx_virq), GFP_KERNEL); 432 if (!vi) 433 return -1; 434 435 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 436 437 /* Try to get a mapping from the device-tree */ 438 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0); 439 if (virq <= 0) { 440 u8 line, pin; 441 442 /* If that fails, lets fallback to what is in the config 443 * space and map that through the default controller. We 444 * also set the type to level low since that's what PCI 445 * interrupts are. If your platform does differently, then 446 * either provide a proper interrupt tree or don't use this 447 * function. 448 */ 449 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 450 goto error_exit; 451 if (pin == 0) 452 goto error_exit; 453 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 454 line == 0xff || line == 0) { 455 goto error_exit; 456 } 457 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 458 line, pin); 459 460 virq = irq_create_mapping(NULL, line); 461 if (virq) 462 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 463 } 464 465 if (!virq) { 466 pr_debug(" Failed to map !\n"); 467 goto error_exit; 468 } 469 470 pr_debug(" Mapped to linux irq %d\n", virq); 471 472 pci_dev->irq = virq; 473 474 mutex_lock(&intx_mutex); 475 list_for_each_entry(vitmp, &intx_list, list_node) { 476 if (vitmp->virq == virq) { 477 kref_get(&vitmp->kref); 478 kfree(vi); 479 vi = NULL; 480 break; 481 } 482 } 483 if (vi) { 484 vi->virq = virq; 485 kref_init(&vi->kref); 486 list_add_tail(&vi->list_node, &intx_list); 487 } 488 mutex_unlock(&intx_mutex); 489 490 return 0; 491 error_exit: 492 kfree(vi); 493 return -1; 494 } 495 496 /* 497 * Platform support for /proc/bus/pci/X/Y mmap()s. 498 * -- paulus. 499 */ 500 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) 501 { 502 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 503 resource_size_t ioaddr = pci_resource_start(pdev, bar); 504 505 if (!hose) 506 return -EINVAL; 507 508 /* Convert to an offset within this PCI controller */ 509 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; 510 511 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; 512 return 0; 513 } 514 515 /* 516 * This one is used by /dev/mem and fbdev who have no clue about the 517 * PCI device, it tries to find the PCI device first and calls the 518 * above routine 519 */ 520 pgprot_t pci_phys_mem_access_prot(struct file *file, 521 unsigned long pfn, 522 unsigned long size, 523 pgprot_t prot) 524 { 525 struct pci_dev *pdev = NULL; 526 struct resource *found = NULL; 527 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 528 int i; 529 530 if (page_is_ram(pfn)) 531 return prot; 532 533 prot = pgprot_noncached(prot); 534 for_each_pci_dev(pdev) { 535 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 536 struct resource *rp = &pdev->resource[i]; 537 int flags = rp->flags; 538 539 /* Active and same type? */ 540 if ((flags & IORESOURCE_MEM) == 0) 541 continue; 542 /* In the range of this resource? */ 543 if (offset < (rp->start & PAGE_MASK) || 544 offset > rp->end) 545 continue; 546 found = rp; 547 break; 548 } 549 if (found) 550 break; 551 } 552 if (found) { 553 if (found->flags & IORESOURCE_PREFETCH) 554 prot = pgprot_noncached_wc(prot); 555 pci_dev_put(pdev); 556 } 557 558 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 559 (unsigned long long)offset, pgprot_val(prot)); 560 561 return prot; 562 } 563 564 /* This provides legacy IO read access on a bus */ 565 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 566 { 567 unsigned long offset; 568 struct pci_controller *hose = pci_bus_to_host(bus); 569 struct resource *rp = &hose->io_resource; 570 void __iomem *addr; 571 572 /* Check if port can be supported by that bus. We only check 573 * the ranges of the PHB though, not the bus itself as the rules 574 * for forwarding legacy cycles down bridges are not our problem 575 * here. So if the host bridge supports it, we do it. 576 */ 577 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 578 offset += port; 579 580 if (!(rp->flags & IORESOURCE_IO)) 581 return -ENXIO; 582 if (offset < rp->start || (offset + size) > rp->end) 583 return -ENXIO; 584 addr = hose->io_base_virt + port; 585 586 switch(size) { 587 case 1: 588 *((u8 *)val) = in_8(addr); 589 return 1; 590 case 2: 591 if (port & 1) 592 return -EINVAL; 593 *((u16 *)val) = in_le16(addr); 594 return 2; 595 case 4: 596 if (port & 3) 597 return -EINVAL; 598 *((u32 *)val) = in_le32(addr); 599 return 4; 600 } 601 return -EINVAL; 602 } 603 604 /* This provides legacy IO write access on a bus */ 605 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 606 { 607 unsigned long offset; 608 struct pci_controller *hose = pci_bus_to_host(bus); 609 struct resource *rp = &hose->io_resource; 610 void __iomem *addr; 611 612 /* Check if port can be supported by that bus. We only check 613 * the ranges of the PHB though, not the bus itself as the rules 614 * for forwarding legacy cycles down bridges are not our problem 615 * here. So if the host bridge supports it, we do it. 616 */ 617 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 618 offset += port; 619 620 if (!(rp->flags & IORESOURCE_IO)) 621 return -ENXIO; 622 if (offset < rp->start || (offset + size) > rp->end) 623 return -ENXIO; 624 addr = hose->io_base_virt + port; 625 626 /* WARNING: The generic code is idiotic. It gets passed a pointer 627 * to what can be a 1, 2 or 4 byte quantity and always reads that 628 * as a u32, which means that we have to correct the location of 629 * the data read within those 32 bits for size 1 and 2 630 */ 631 switch(size) { 632 case 1: 633 out_8(addr, val >> 24); 634 return 1; 635 case 2: 636 if (port & 1) 637 return -EINVAL; 638 out_le16(addr, val >> 16); 639 return 2; 640 case 4: 641 if (port & 3) 642 return -EINVAL; 643 out_le32(addr, val); 644 return 4; 645 } 646 return -EINVAL; 647 } 648 649 /* This provides legacy IO or memory mmap access on a bus */ 650 int pci_mmap_legacy_page_range(struct pci_bus *bus, 651 struct vm_area_struct *vma, 652 enum pci_mmap_state mmap_state) 653 { 654 struct pci_controller *hose = pci_bus_to_host(bus); 655 resource_size_t offset = 656 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 657 resource_size_t size = vma->vm_end - vma->vm_start; 658 struct resource *rp; 659 660 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 661 pci_domain_nr(bus), bus->number, 662 mmap_state == pci_mmap_mem ? "MEM" : "IO", 663 (unsigned long long)offset, 664 (unsigned long long)(offset + size - 1)); 665 666 if (mmap_state == pci_mmap_mem) { 667 /* Hack alert ! 668 * 669 * Because X is lame and can fail starting if it gets an error trying 670 * to mmap legacy_mem (instead of just moving on without legacy memory 671 * access) we fake it here by giving it anonymous memory, effectively 672 * behaving just like /dev/zero 673 */ 674 if ((offset + size) > hose->isa_mem_size) { 675 printk(KERN_DEBUG 676 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 677 current->comm, current->pid, pci_domain_nr(bus), bus->number); 678 if (vma->vm_flags & VM_SHARED) 679 return shmem_zero_setup(vma); 680 return 0; 681 } 682 offset += hose->isa_mem_phys; 683 } else { 684 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 685 unsigned long roffset = offset + io_offset; 686 rp = &hose->io_resource; 687 if (!(rp->flags & IORESOURCE_IO)) 688 return -ENXIO; 689 if (roffset < rp->start || (roffset + size) > rp->end) 690 return -ENXIO; 691 offset += hose->io_base_phys; 692 } 693 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 694 695 vma->vm_pgoff = offset >> PAGE_SHIFT; 696 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 697 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 698 vma->vm_end - vma->vm_start, 699 vma->vm_page_prot); 700 } 701 702 void pci_resource_to_user(const struct pci_dev *dev, int bar, 703 const struct resource *rsrc, 704 resource_size_t *start, resource_size_t *end) 705 { 706 struct pci_bus_region region; 707 708 if (rsrc->flags & IORESOURCE_IO) { 709 pcibios_resource_to_bus(dev->bus, ®ion, 710 (struct resource *) rsrc); 711 *start = region.start; 712 *end = region.end; 713 return; 714 } 715 716 /* We pass a CPU physical address to userland for MMIO instead of a 717 * BAR value because X is lame and expects to be able to use that 718 * to pass to /dev/mem! 719 * 720 * That means we may have 64-bit values where some apps only expect 721 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). 722 */ 723 *start = rsrc->start; 724 *end = rsrc->end; 725 } 726 727 /** 728 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 729 * @hose: newly allocated pci_controller to be setup 730 * @dev: device node of the host bridge 731 * @primary: set if primary bus (32 bits only, soon to be deprecated) 732 * 733 * This function will parse the "ranges" property of a PCI host bridge device 734 * node and setup the resource mapping of a pci controller based on its 735 * content. 736 * 737 * Life would be boring if it wasn't for a few issues that we have to deal 738 * with here: 739 * 740 * - We can only cope with one IO space range and up to 3 Memory space 741 * ranges. However, some machines (thanks Apple !) tend to split their 742 * space into lots of small contiguous ranges. So we have to coalesce. 743 * 744 * - Some busses have IO space not starting at 0, which causes trouble with 745 * the way we do our IO resource renumbering. The code somewhat deals with 746 * it for 64 bits but I would expect problems on 32 bits. 747 * 748 * - Some 32 bits platforms such as 4xx can have physical space larger than 749 * 32 bits so we need to use 64 bits values for the parsing 750 */ 751 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 752 struct device_node *dev, int primary) 753 { 754 int memno = 0; 755 struct resource *res; 756 struct of_pci_range range; 757 struct of_pci_range_parser parser; 758 759 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n", 760 dev, primary ? "(primary)" : ""); 761 762 /* Check for ranges property */ 763 if (of_pci_range_parser_init(&parser, dev)) 764 return; 765 766 /* Parse it */ 767 for_each_of_pci_range(&parser, &range) { 768 /* If we failed translation or got a zero-sized region 769 * (some FW try to feed us with non sensical zero sized regions 770 * such as power3 which look like some kind of attempt at exposing 771 * the VGA memory hole) 772 */ 773 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 774 continue; 775 776 /* Act based on address space type */ 777 res = NULL; 778 switch (range.flags & IORESOURCE_TYPE_BITS) { 779 case IORESOURCE_IO: 780 printk(KERN_INFO 781 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 782 range.cpu_addr, range.cpu_addr + range.size - 1, 783 range.pci_addr); 784 785 /* We support only one IO range */ 786 if (hose->pci_io_size) { 787 printk(KERN_INFO 788 " \\--> Skipped (too many) !\n"); 789 continue; 790 } 791 #ifdef CONFIG_PPC32 792 /* On 32 bits, limit I/O space to 16MB */ 793 if (range.size > 0x01000000) 794 range.size = 0x01000000; 795 796 /* 32 bits needs to map IOs here */ 797 hose->io_base_virt = ioremap(range.cpu_addr, 798 range.size); 799 800 /* Expect trouble if pci_addr is not 0 */ 801 if (primary) 802 isa_io_base = 803 (unsigned long)hose->io_base_virt; 804 #endif /* CONFIG_PPC32 */ 805 /* pci_io_size and io_base_phys always represent IO 806 * space starting at 0 so we factor in pci_addr 807 */ 808 hose->pci_io_size = range.pci_addr + range.size; 809 hose->io_base_phys = range.cpu_addr - range.pci_addr; 810 811 /* Build resource */ 812 res = &hose->io_resource; 813 range.cpu_addr = range.pci_addr; 814 break; 815 case IORESOURCE_MEM: 816 printk(KERN_INFO 817 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 818 range.cpu_addr, range.cpu_addr + range.size - 1, 819 range.pci_addr, 820 (range.flags & IORESOURCE_PREFETCH) ? 821 "Prefetch" : ""); 822 823 /* We support only 3 memory ranges */ 824 if (memno >= 3) { 825 printk(KERN_INFO 826 " \\--> Skipped (too many) !\n"); 827 continue; 828 } 829 /* Handles ISA memory hole space here */ 830 if (range.pci_addr == 0) { 831 if (primary || isa_mem_base == 0) 832 isa_mem_base = range.cpu_addr; 833 hose->isa_mem_phys = range.cpu_addr; 834 hose->isa_mem_size = range.size; 835 } 836 837 /* Build resource */ 838 hose->mem_offset[memno] = range.cpu_addr - 839 range.pci_addr; 840 res = &hose->mem_resources[memno++]; 841 break; 842 } 843 if (res != NULL) { 844 res->name = dev->full_name; 845 res->flags = range.flags; 846 res->start = range.cpu_addr; 847 res->end = range.cpu_addr + range.size - 1; 848 res->parent = res->child = res->sibling = NULL; 849 } 850 } 851 } 852 853 /* Decide whether to display the domain number in /proc */ 854 int pci_proc_domain(struct pci_bus *bus) 855 { 856 struct pci_controller *hose = pci_bus_to_host(bus); 857 858 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 859 return 0; 860 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 861 return hose->global_number != 0; 862 return 1; 863 } 864 865 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 866 { 867 if (ppc_md.pcibios_root_bridge_prepare) 868 return ppc_md.pcibios_root_bridge_prepare(bridge); 869 870 return 0; 871 } 872 873 /* This header fixup will do the resource fixup for all devices as they are 874 * probed, but not for bridge ranges 875 */ 876 static void pcibios_fixup_resources(struct pci_dev *dev) 877 { 878 struct pci_controller *hose = pci_bus_to_host(dev->bus); 879 int i; 880 881 if (!hose) { 882 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 883 pci_name(dev)); 884 return; 885 } 886 887 if (dev->is_virtfn) 888 return; 889 890 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 891 struct resource *res = dev->resource + i; 892 struct pci_bus_region reg; 893 if (!res->flags) 894 continue; 895 896 /* If we're going to re-assign everything, we mark all resources 897 * as unset (and 0-base them). In addition, we mark BARs starting 898 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 899 * since in that case, we don't want to re-assign anything 900 */ 901 pcibios_resource_to_bus(dev->bus, ®, res); 902 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 903 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 904 /* Only print message if not re-assigning */ 905 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 906 pr_debug("PCI:%s Resource %d %pR is unassigned\n", 907 pci_name(dev), i, res); 908 res->end -= res->start; 909 res->start = 0; 910 res->flags |= IORESOURCE_UNSET; 911 continue; 912 } 913 914 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); 915 } 916 917 /* Call machine specific resource fixup */ 918 if (ppc_md.pcibios_fixup_resources) 919 ppc_md.pcibios_fixup_resources(dev); 920 } 921 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 922 923 /* This function tries to figure out if a bridge resource has been initialized 924 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 925 * things go more smoothly when it gets it right. It should covers cases such 926 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 927 */ 928 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 929 struct resource *res) 930 { 931 struct pci_controller *hose = pci_bus_to_host(bus); 932 struct pci_dev *dev = bus->self; 933 resource_size_t offset; 934 struct pci_bus_region region; 935 u16 command; 936 int i; 937 938 /* We don't do anything if PCI_PROBE_ONLY is set */ 939 if (pci_has_flag(PCI_PROBE_ONLY)) 940 return 0; 941 942 /* Job is a bit different between memory and IO */ 943 if (res->flags & IORESOURCE_MEM) { 944 pcibios_resource_to_bus(dev->bus, ®ion, res); 945 946 /* If the BAR is non-0 then it's probably been initialized */ 947 if (region.start != 0) 948 return 0; 949 950 /* The BAR is 0, let's check if memory decoding is enabled on 951 * the bridge. If not, we consider it unassigned 952 */ 953 pci_read_config_word(dev, PCI_COMMAND, &command); 954 if ((command & PCI_COMMAND_MEMORY) == 0) 955 return 1; 956 957 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 958 * resources covers that starting address (0 then it's good enough for 959 * us for memory space) 960 */ 961 for (i = 0; i < 3; i++) { 962 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 963 hose->mem_resources[i].start == hose->mem_offset[i]) 964 return 0; 965 } 966 967 /* Well, it starts at 0 and we know it will collide so we may as 968 * well consider it as unassigned. That covers the Apple case. 969 */ 970 return 1; 971 } else { 972 /* If the BAR is non-0, then we consider it assigned */ 973 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 974 if (((res->start - offset) & 0xfffffffful) != 0) 975 return 0; 976 977 /* Here, we are a bit different than memory as typically IO space 978 * starting at low addresses -is- valid. What we do instead if that 979 * we consider as unassigned anything that doesn't have IO enabled 980 * in the PCI command register, and that's it. 981 */ 982 pci_read_config_word(dev, PCI_COMMAND, &command); 983 if (command & PCI_COMMAND_IO) 984 return 0; 985 986 /* It's starting at 0 and IO is disabled in the bridge, consider 987 * it unassigned 988 */ 989 return 1; 990 } 991 } 992 993 /* Fixup resources of a PCI<->PCI bridge */ 994 static void pcibios_fixup_bridge(struct pci_bus *bus) 995 { 996 struct resource *res; 997 int i; 998 999 struct pci_dev *dev = bus->self; 1000 1001 pci_bus_for_each_resource(bus, res, i) { 1002 if (!res || !res->flags) 1003 continue; 1004 if (i >= 3 && bus->self->transparent) 1005 continue; 1006 1007 /* If we're going to reassign everything, we can 1008 * shrink the P2P resource to have size as being 1009 * of 0 in order to save space. 1010 */ 1011 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1012 res->flags |= IORESOURCE_UNSET; 1013 res->start = 0; 1014 res->end = -1; 1015 continue; 1016 } 1017 1018 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); 1019 1020 /* Try to detect uninitialized P2P bridge resources, 1021 * and clear them out so they get re-assigned later 1022 */ 1023 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1024 res->flags = 0; 1025 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1026 } 1027 } 1028 } 1029 1030 void pcibios_setup_bus_self(struct pci_bus *bus) 1031 { 1032 struct pci_controller *phb; 1033 1034 /* Fix up the bus resources for P2P bridges */ 1035 if (bus->self != NULL) 1036 pcibios_fixup_bridge(bus); 1037 1038 /* Platform specific bus fixups. This is currently only used 1039 * by fsl_pci and I'm hoping to get rid of it at some point 1040 */ 1041 if (ppc_md.pcibios_fixup_bus) 1042 ppc_md.pcibios_fixup_bus(bus); 1043 1044 /* Setup bus DMA mappings */ 1045 phb = pci_bus_to_host(bus); 1046 if (phb->controller_ops.dma_bus_setup) 1047 phb->controller_ops.dma_bus_setup(bus); 1048 } 1049 1050 void pcibios_bus_add_device(struct pci_dev *dev) 1051 { 1052 struct pci_controller *phb; 1053 /* Fixup NUMA node as it may not be setup yet by the generic 1054 * code and is needed by the DMA init 1055 */ 1056 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1057 1058 /* Hook up default DMA ops */ 1059 set_dma_ops(&dev->dev, pci_dma_ops); 1060 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; 1061 1062 /* Additional platform DMA/iommu setup */ 1063 phb = pci_bus_to_host(dev->bus); 1064 if (phb->controller_ops.dma_dev_setup) 1065 phb->controller_ops.dma_dev_setup(dev); 1066 1067 /* Read default IRQs and fixup if necessary */ 1068 pci_read_irq_line(dev); 1069 if (ppc_md.pci_irq_fixup) 1070 ppc_md.pci_irq_fixup(dev); 1071 1072 if (ppc_md.pcibios_bus_add_device) 1073 ppc_md.pcibios_bus_add_device(dev); 1074 } 1075 1076 int pcibios_device_add(struct pci_dev *dev) 1077 { 1078 struct irq_domain *d; 1079 1080 #ifdef CONFIG_PCI_IOV 1081 if (ppc_md.pcibios_fixup_sriov) 1082 ppc_md.pcibios_fixup_sriov(dev); 1083 #endif /* CONFIG_PCI_IOV */ 1084 1085 d = dev_get_msi_domain(&dev->bus->dev); 1086 if (d) 1087 dev_set_msi_domain(&dev->dev, d); 1088 return 0; 1089 } 1090 1091 void pcibios_set_master(struct pci_dev *dev) 1092 { 1093 /* No special bus mastering setup handling */ 1094 } 1095 1096 void pcibios_fixup_bus(struct pci_bus *bus) 1097 { 1098 /* When called from the generic PCI probe, read PCI<->PCI bridge 1099 * bases. This is -not- called when generating the PCI tree from 1100 * the OF device-tree. 1101 */ 1102 pci_read_bridge_bases(bus); 1103 1104 /* Now fixup the bus */ 1105 pcibios_setup_bus_self(bus); 1106 } 1107 EXPORT_SYMBOL(pcibios_fixup_bus); 1108 1109 static int skip_isa_ioresource_align(struct pci_dev *dev) 1110 { 1111 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1112 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1113 return 1; 1114 return 0; 1115 } 1116 1117 /* 1118 * We need to avoid collisions with `mirrored' VGA ports 1119 * and other strange ISA hardware, so we always want the 1120 * addresses to be allocated in the 0x000-0x0ff region 1121 * modulo 0x400. 1122 * 1123 * Why? Because some silly external IO cards only decode 1124 * the low 10 bits of the IO address. The 0x00-0xff region 1125 * is reserved for motherboard devices that decode all 16 1126 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1127 * but we want to try to avoid allocating at 0x2900-0x2bff 1128 * which might have be mirrored at 0x0100-0x03ff.. 1129 */ 1130 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1131 resource_size_t size, resource_size_t align) 1132 { 1133 struct pci_dev *dev = data; 1134 resource_size_t start = res->start; 1135 1136 if (res->flags & IORESOURCE_IO) { 1137 if (skip_isa_ioresource_align(dev)) 1138 return start; 1139 if (start & 0x300) 1140 start = (start + 0x3ff) & ~0x3ff; 1141 } 1142 1143 return start; 1144 } 1145 EXPORT_SYMBOL(pcibios_align_resource); 1146 1147 /* 1148 * Reparent resource children of pr that conflict with res 1149 * under res, and make res replace those children. 1150 */ 1151 static int reparent_resources(struct resource *parent, 1152 struct resource *res) 1153 { 1154 struct resource *p, **pp; 1155 struct resource **firstpp = NULL; 1156 1157 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1158 if (p->end < res->start) 1159 continue; 1160 if (res->end < p->start) 1161 break; 1162 if (p->start < res->start || p->end > res->end) 1163 return -1; /* not completely contained */ 1164 if (firstpp == NULL) 1165 firstpp = pp; 1166 } 1167 if (firstpp == NULL) 1168 return -1; /* didn't find any conflicting entries? */ 1169 res->parent = parent; 1170 res->child = *firstpp; 1171 res->sibling = *pp; 1172 *firstpp = res; 1173 *pp = NULL; 1174 for (p = res->child; p != NULL; p = p->sibling) { 1175 p->parent = res; 1176 pr_debug("PCI: Reparented %s %pR under %s\n", 1177 p->name, p, res->name); 1178 } 1179 return 0; 1180 } 1181 1182 /* 1183 * Handle resources of PCI devices. If the world were perfect, we could 1184 * just allocate all the resource regions and do nothing more. It isn't. 1185 * On the other hand, we cannot just re-allocate all devices, as it would 1186 * require us to know lots of host bridge internals. So we attempt to 1187 * keep as much of the original configuration as possible, but tweak it 1188 * when it's found to be wrong. 1189 * 1190 * Known BIOS problems we have to work around: 1191 * - I/O or memory regions not configured 1192 * - regions configured, but not enabled in the command register 1193 * - bogus I/O addresses above 64K used 1194 * - expansion ROMs left enabled (this may sound harmless, but given 1195 * the fact the PCI specs explicitly allow address decoders to be 1196 * shared between expansion ROMs and other resource regions, it's 1197 * at least dangerous) 1198 * 1199 * Our solution: 1200 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1201 * This gives us fixed barriers on where we can allocate. 1202 * (2) Allocate resources for all enabled devices. If there is 1203 * a collision, just mark the resource as unallocated. Also 1204 * disable expansion ROMs during this step. 1205 * (3) Try to allocate resources for disabled devices. If the 1206 * resources were assigned correctly, everything goes well, 1207 * if they weren't, they won't disturb allocation of other 1208 * resources. 1209 * (4) Assign new addresses to resources which were either 1210 * not configured at all or misconfigured. If explicitly 1211 * requested by the user, configure expansion ROM address 1212 * as well. 1213 */ 1214 1215 static void pcibios_allocate_bus_resources(struct pci_bus *bus) 1216 { 1217 struct pci_bus *b; 1218 int i; 1219 struct resource *res, *pr; 1220 1221 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1222 pci_domain_nr(bus), bus->number); 1223 1224 pci_bus_for_each_resource(bus, res, i) { 1225 if (!res || !res->flags || res->start > res->end || res->parent) 1226 continue; 1227 1228 /* If the resource was left unset at this point, we clear it */ 1229 if (res->flags & IORESOURCE_UNSET) 1230 goto clear_resource; 1231 1232 if (bus->parent == NULL) 1233 pr = (res->flags & IORESOURCE_IO) ? 1234 &ioport_resource : &iomem_resource; 1235 else { 1236 pr = pci_find_parent_resource(bus->self, res); 1237 if (pr == res) { 1238 /* this happens when the generic PCI 1239 * code (wrongly) decides that this 1240 * bridge is transparent -- paulus 1241 */ 1242 continue; 1243 } 1244 } 1245 1246 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", 1247 bus->self ? pci_name(bus->self) : "PHB", bus->number, 1248 i, res, pr, (pr && pr->name) ? pr->name : "nil"); 1249 1250 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1251 struct pci_dev *dev = bus->self; 1252 1253 if (request_resource(pr, res) == 0) 1254 continue; 1255 /* 1256 * Must be a conflict with an existing entry. 1257 * Move that entry (or entries) under the 1258 * bridge resource and try again. 1259 */ 1260 if (reparent_resources(pr, res) == 0) 1261 continue; 1262 1263 if (dev && i < PCI_BRIDGE_RESOURCE_NUM && 1264 pci_claim_bridge_resource(dev, 1265 i + PCI_BRIDGE_RESOURCES) == 0) 1266 continue; 1267 } 1268 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n", 1269 i, bus->number); 1270 clear_resource: 1271 /* The resource might be figured out when doing 1272 * reassignment based on the resources required 1273 * by the downstream PCI devices. Here we set 1274 * the size of the resource to be 0 in order to 1275 * save more space. 1276 */ 1277 res->start = 0; 1278 res->end = -1; 1279 res->flags = 0; 1280 } 1281 1282 list_for_each_entry(b, &bus->children, node) 1283 pcibios_allocate_bus_resources(b); 1284 } 1285 1286 static inline void alloc_resource(struct pci_dev *dev, int idx) 1287 { 1288 struct resource *pr, *r = &dev->resource[idx]; 1289 1290 pr_debug("PCI: Allocating %s: Resource %d: %pR\n", 1291 pci_name(dev), idx, r); 1292 1293 pr = pci_find_parent_resource(dev, r); 1294 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1295 request_resource(pr, r) < 0) { 1296 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1297 " of device %s, will remap\n", idx, pci_name(dev)); 1298 if (pr) 1299 pr_debug("PCI: parent is %p: %pR\n", pr, pr); 1300 /* We'll assign a new address later */ 1301 r->flags |= IORESOURCE_UNSET; 1302 r->end -= r->start; 1303 r->start = 0; 1304 } 1305 } 1306 1307 static void __init pcibios_allocate_resources(int pass) 1308 { 1309 struct pci_dev *dev = NULL; 1310 int idx, disabled; 1311 u16 command; 1312 struct resource *r; 1313 1314 for_each_pci_dev(dev) { 1315 pci_read_config_word(dev, PCI_COMMAND, &command); 1316 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1317 r = &dev->resource[idx]; 1318 if (r->parent) /* Already allocated */ 1319 continue; 1320 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1321 continue; /* Not assigned at all */ 1322 /* We only allocate ROMs on pass 1 just in case they 1323 * have been screwed up by firmware 1324 */ 1325 if (idx == PCI_ROM_RESOURCE ) 1326 disabled = 1; 1327 if (r->flags & IORESOURCE_IO) 1328 disabled = !(command & PCI_COMMAND_IO); 1329 else 1330 disabled = !(command & PCI_COMMAND_MEMORY); 1331 if (pass == disabled) 1332 alloc_resource(dev, idx); 1333 } 1334 if (pass) 1335 continue; 1336 r = &dev->resource[PCI_ROM_RESOURCE]; 1337 if (r->flags) { 1338 /* Turn the ROM off, leave the resource region, 1339 * but keep it unregistered. 1340 */ 1341 u32 reg; 1342 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1343 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1344 pr_debug("PCI: Switching off ROM of %s\n", 1345 pci_name(dev)); 1346 r->flags &= ~IORESOURCE_ROM_ENABLE; 1347 pci_write_config_dword(dev, dev->rom_base_reg, 1348 reg & ~PCI_ROM_ADDRESS_ENABLE); 1349 } 1350 } 1351 } 1352 } 1353 1354 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1355 { 1356 struct pci_controller *hose = pci_bus_to_host(bus); 1357 resource_size_t offset; 1358 struct resource *res, *pres; 1359 int i; 1360 1361 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1362 1363 /* Check for IO */ 1364 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1365 goto no_io; 1366 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1367 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1368 BUG_ON(res == NULL); 1369 res->name = "Legacy IO"; 1370 res->flags = IORESOURCE_IO; 1371 res->start = offset; 1372 res->end = (offset + 0xfff) & 0xfffffffful; 1373 pr_debug("Candidate legacy IO: %pR\n", res); 1374 if (request_resource(&hose->io_resource, res)) { 1375 printk(KERN_DEBUG 1376 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1377 pci_domain_nr(bus), bus->number, res); 1378 kfree(res); 1379 } 1380 1381 no_io: 1382 /* Check for memory */ 1383 for (i = 0; i < 3; i++) { 1384 pres = &hose->mem_resources[i]; 1385 offset = hose->mem_offset[i]; 1386 if (!(pres->flags & IORESOURCE_MEM)) 1387 continue; 1388 pr_debug("hose mem res: %pR\n", pres); 1389 if ((pres->start - offset) <= 0xa0000 && 1390 (pres->end - offset) >= 0xbffff) 1391 break; 1392 } 1393 if (i >= 3) 1394 return; 1395 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1396 BUG_ON(res == NULL); 1397 res->name = "Legacy VGA memory"; 1398 res->flags = IORESOURCE_MEM; 1399 res->start = 0xa0000 + offset; 1400 res->end = 0xbffff + offset; 1401 pr_debug("Candidate VGA memory: %pR\n", res); 1402 if (request_resource(pres, res)) { 1403 printk(KERN_DEBUG 1404 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1405 pci_domain_nr(bus), bus->number, res); 1406 kfree(res); 1407 } 1408 } 1409 1410 void __init pcibios_resource_survey(void) 1411 { 1412 struct pci_bus *b; 1413 1414 /* Allocate and assign resources */ 1415 list_for_each_entry(b, &pci_root_buses, node) 1416 pcibios_allocate_bus_resources(b); 1417 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1418 pcibios_allocate_resources(0); 1419 pcibios_allocate_resources(1); 1420 } 1421 1422 /* Before we start assigning unassigned resource, we try to reserve 1423 * the low IO area and the VGA memory area if they intersect the 1424 * bus available resources to avoid allocating things on top of them 1425 */ 1426 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1427 list_for_each_entry(b, &pci_root_buses, node) 1428 pcibios_reserve_legacy_regions(b); 1429 } 1430 1431 /* Now, if the platform didn't decide to blindly trust the firmware, 1432 * we proceed to assigning things that were left unassigned 1433 */ 1434 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1435 pr_debug("PCI: Assigning unassigned resources...\n"); 1436 pci_assign_unassigned_resources(); 1437 } 1438 } 1439 1440 /* This is used by the PCI hotplug driver to allocate resource 1441 * of newly plugged busses. We can try to consolidate with the 1442 * rest of the code later, for now, keep it as-is as our main 1443 * resource allocation function doesn't deal with sub-trees yet. 1444 */ 1445 void pcibios_claim_one_bus(struct pci_bus *bus) 1446 { 1447 struct pci_dev *dev; 1448 struct pci_bus *child_bus; 1449 1450 list_for_each_entry(dev, &bus->devices, bus_list) { 1451 int i; 1452 1453 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1454 struct resource *r = &dev->resource[i]; 1455 1456 if (r->parent || !r->start || !r->flags) 1457 continue; 1458 1459 pr_debug("PCI: Claiming %s: Resource %d: %pR\n", 1460 pci_name(dev), i, r); 1461 1462 if (pci_claim_resource(dev, i) == 0) 1463 continue; 1464 1465 pci_claim_bridge_resource(dev, i); 1466 } 1467 } 1468 1469 list_for_each_entry(child_bus, &bus->children, node) 1470 pcibios_claim_one_bus(child_bus); 1471 } 1472 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1473 1474 1475 /* pcibios_finish_adding_to_bus 1476 * 1477 * This is to be called by the hotplug code after devices have been 1478 * added to a bus, this include calling it for a PHB that is just 1479 * being added 1480 */ 1481 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1482 { 1483 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1484 pci_domain_nr(bus), bus->number); 1485 1486 /* Allocate bus and devices resources */ 1487 pcibios_allocate_bus_resources(bus); 1488 pcibios_claim_one_bus(bus); 1489 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1490 if (bus->self) 1491 pci_assign_unassigned_bridge_resources(bus->self); 1492 else 1493 pci_assign_unassigned_bus_resources(bus); 1494 } 1495 1496 /* Add new devices to global lists. Register in proc, sysfs. */ 1497 pci_bus_add_devices(bus); 1498 } 1499 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1500 1501 int pcibios_enable_device(struct pci_dev *dev, int mask) 1502 { 1503 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1504 1505 if (phb->controller_ops.enable_device_hook) 1506 if (!phb->controller_ops.enable_device_hook(dev)) 1507 return -EINVAL; 1508 1509 return pci_enable_resources(dev, mask); 1510 } 1511 1512 void pcibios_disable_device(struct pci_dev *dev) 1513 { 1514 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1515 1516 if (phb->controller_ops.disable_device) 1517 phb->controller_ops.disable_device(dev); 1518 } 1519 1520 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1521 { 1522 return (unsigned long) hose->io_base_virt - _IO_BASE; 1523 } 1524 1525 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1526 struct list_head *resources) 1527 { 1528 struct resource *res; 1529 resource_size_t offset; 1530 int i; 1531 1532 /* Hookup PHB IO resource */ 1533 res = &hose->io_resource; 1534 1535 if (!res->flags) { 1536 pr_debug("PCI: I/O resource not set for host" 1537 " bridge %pOF (domain %d)\n", 1538 hose->dn, hose->global_number); 1539 } else { 1540 offset = pcibios_io_space_offset(hose); 1541 1542 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", 1543 res, (unsigned long long)offset); 1544 pci_add_resource_offset(resources, res, offset); 1545 } 1546 1547 /* Hookup PHB Memory resources */ 1548 for (i = 0; i < 3; ++i) { 1549 res = &hose->mem_resources[i]; 1550 if (!res->flags) 1551 continue; 1552 1553 offset = hose->mem_offset[i]; 1554 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, 1555 res, (unsigned long long)offset); 1556 1557 pci_add_resource_offset(resources, res, offset); 1558 } 1559 } 1560 1561 /* 1562 * Null PCI config access functions, for the case when we can't 1563 * find a hose. 1564 */ 1565 #define NULL_PCI_OP(rw, size, type) \ 1566 static int \ 1567 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1568 { \ 1569 return PCIBIOS_DEVICE_NOT_FOUND; \ 1570 } 1571 1572 static int 1573 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1574 int len, u32 *val) 1575 { 1576 return PCIBIOS_DEVICE_NOT_FOUND; 1577 } 1578 1579 static int 1580 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1581 int len, u32 val) 1582 { 1583 return PCIBIOS_DEVICE_NOT_FOUND; 1584 } 1585 1586 static struct pci_ops null_pci_ops = 1587 { 1588 .read = null_read_config, 1589 .write = null_write_config, 1590 }; 1591 1592 /* 1593 * These functions are used early on before PCI scanning is done 1594 * and all of the pci_dev and pci_bus structures have been created. 1595 */ 1596 static struct pci_bus * 1597 fake_pci_bus(struct pci_controller *hose, int busnr) 1598 { 1599 static struct pci_bus bus; 1600 1601 if (hose == NULL) { 1602 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1603 } 1604 bus.number = busnr; 1605 bus.sysdata = hose; 1606 bus.ops = hose? hose->ops: &null_pci_ops; 1607 return &bus; 1608 } 1609 1610 #define EARLY_PCI_OP(rw, size, type) \ 1611 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1612 int devfn, int offset, type value) \ 1613 { \ 1614 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1615 devfn, offset, value); \ 1616 } 1617 1618 EARLY_PCI_OP(read, byte, u8 *) 1619 EARLY_PCI_OP(read, word, u16 *) 1620 EARLY_PCI_OP(read, dword, u32 *) 1621 EARLY_PCI_OP(write, byte, u8) 1622 EARLY_PCI_OP(write, word, u16) 1623 EARLY_PCI_OP(write, dword, u32) 1624 1625 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1626 int cap) 1627 { 1628 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1629 } 1630 1631 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1632 { 1633 struct pci_controller *hose = bus->sysdata; 1634 1635 return of_node_get(hose->dn); 1636 } 1637 1638 /** 1639 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1640 * @hose: Pointer to the PCI host controller instance structure 1641 */ 1642 void pcibios_scan_phb(struct pci_controller *hose) 1643 { 1644 LIST_HEAD(resources); 1645 struct pci_bus *bus; 1646 struct device_node *node = hose->dn; 1647 int mode; 1648 1649 pr_debug("PCI: Scanning PHB %pOF\n", node); 1650 1651 /* Get some IO space for the new PHB */ 1652 pcibios_setup_phb_io_space(hose); 1653 1654 /* Wire up PHB bus resources */ 1655 pcibios_setup_phb_resources(hose, &resources); 1656 1657 hose->busn.start = hose->first_busno; 1658 hose->busn.end = hose->last_busno; 1659 hose->busn.flags = IORESOURCE_BUS; 1660 pci_add_resource(&resources, &hose->busn); 1661 1662 /* Create an empty bus for the toplevel */ 1663 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1664 hose->ops, hose, &resources); 1665 if (bus == NULL) { 1666 pr_err("Failed to create bus for PCI domain %04x\n", 1667 hose->global_number); 1668 pci_free_resource_list(&resources); 1669 return; 1670 } 1671 hose->bus = bus; 1672 1673 /* Get probe mode and perform scan */ 1674 mode = PCI_PROBE_NORMAL; 1675 if (node && hose->controller_ops.probe_mode) 1676 mode = hose->controller_ops.probe_mode(bus); 1677 pr_debug(" probe mode: %d\n", mode); 1678 if (mode == PCI_PROBE_DEVTREE) 1679 of_scan_bus(node, bus); 1680 1681 if (mode == PCI_PROBE_NORMAL) { 1682 pci_bus_update_busn_res_end(bus, 255); 1683 hose->last_busno = pci_scan_child_bus(bus); 1684 pci_bus_update_busn_res_end(bus, hose->last_busno); 1685 } 1686 1687 /* Platform gets a chance to do some global fixups before 1688 * we proceed to resource allocation 1689 */ 1690 if (ppc_md.pcibios_fixup_phb) 1691 ppc_md.pcibios_fixup_phb(hose); 1692 1693 /* Configure PCI Express settings */ 1694 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1695 struct pci_bus *child; 1696 list_for_each_entry(child, &bus->children, node) 1697 pcie_bus_configure_settings(child); 1698 } 1699 } 1700 EXPORT_SYMBOL_GPL(pcibios_scan_phb); 1701 1702 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1703 { 1704 int i, class = dev->class >> 8; 1705 /* When configured as agent, programming interface = 1 */ 1706 int prog_if = dev->class & 0xf; 1707 1708 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1709 class == PCI_CLASS_BRIDGE_OTHER) && 1710 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1711 (prog_if == 0) && 1712 (dev->bus->parent == NULL)) { 1713 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1714 dev->resource[i].start = 0; 1715 dev->resource[i].end = 0; 1716 dev->resource[i].flags = 0; 1717 } 1718 } 1719 } 1720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1722 1723 1724 static int __init discover_phbs(void) 1725 { 1726 if (ppc_md.discover_phbs) 1727 ppc_md.discover_phbs(); 1728 1729 return 0; 1730 } 1731 core_initcall(discover_phbs); 1732