xref: /openbmc/linux/arch/powerpc/kernel/pci-common.c (revision 6aa7de05)
1 /*
2  * Contains common pci routines for ALL ppc platform
3  * (based on pci_32.c and pci_64.c)
4  *
5  * Port for PPC64 David Engebretsen, IBM Corp.
6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7  *
8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9  *   Rework, based on alpha PCI code.
10  *
11  * Common pmac/prep/chrp pci routines. -- Cort
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version
16  * 2 of the License, or (at your option) any later version.
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
27 #include <linux/mm.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
35 
36 #include <asm/processor.h>
37 #include <asm/io.h>
38 #include <asm/prom.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
43 #include <asm/eeh.h>
44 
45 /* hose_spinlock protects accesses to the the phb_bitmap. */
46 static DEFINE_SPINLOCK(hose_spinlock);
47 LIST_HEAD(hose_list);
48 
49 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
50 #define MAX_PHBS 0x10000
51 
52 /*
53  * For dynamic PHB numbering: used/free PHBs tracking bitmap.
54  * Accesses to this bitmap should be protected by hose_spinlock.
55  */
56 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
57 
58 /* ISA Memory physical address */
59 resource_size_t isa_mem_base;
60 EXPORT_SYMBOL(isa_mem_base);
61 
62 
63 static const struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
64 
65 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
66 {
67 	pci_dma_ops = dma_ops;
68 }
69 
70 const struct dma_map_ops *get_pci_dma_ops(void)
71 {
72 	return pci_dma_ops;
73 }
74 EXPORT_SYMBOL(get_pci_dma_ops);
75 
76 /*
77  * This function should run under locking protection, specifically
78  * hose_spinlock.
79  */
80 static int get_phb_number(struct device_node *dn)
81 {
82 	int ret, phb_id = -1;
83 	u32 prop_32;
84 	u64 prop;
85 
86 	/*
87 	 * Try fixed PHB numbering first, by checking archs and reading
88 	 * the respective device-tree properties. Firstly, try powernv by
89 	 * reading "ibm,opal-phbid", only present in OPAL environment.
90 	 */
91 	ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
92 	if (ret) {
93 		ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
94 		prop = prop_32;
95 	}
96 
97 	if (!ret)
98 		phb_id = (int)(prop & (MAX_PHBS - 1));
99 
100 	/* We need to be sure to not use the same PHB number twice. */
101 	if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
102 		return phb_id;
103 
104 	/*
105 	 * If not pseries nor powernv, or if fixed PHB numbering tried to add
106 	 * the same PHB number twice, then fallback to dynamic PHB numbering.
107 	 */
108 	phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
109 	BUG_ON(phb_id >= MAX_PHBS);
110 	set_bit(phb_id, phb_bitmap);
111 
112 	return phb_id;
113 }
114 
115 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
116 {
117 	struct pci_controller *phb;
118 
119 	phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
120 	if (phb == NULL)
121 		return NULL;
122 	spin_lock(&hose_spinlock);
123 	phb->global_number = get_phb_number(dev);
124 	list_add_tail(&phb->list_node, &hose_list);
125 	spin_unlock(&hose_spinlock);
126 	phb->dn = dev;
127 	phb->is_dynamic = slab_is_available();
128 #ifdef CONFIG_PPC64
129 	if (dev) {
130 		int nid = of_node_to_nid(dev);
131 
132 		if (nid < 0 || !node_online(nid))
133 			nid = -1;
134 
135 		PHB_SET_NODE(phb, nid);
136 	}
137 #endif
138 	return phb;
139 }
140 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
141 
142 void pcibios_free_controller(struct pci_controller *phb)
143 {
144 	spin_lock(&hose_spinlock);
145 
146 	/* Clear bit of phb_bitmap to allow reuse of this PHB number. */
147 	if (phb->global_number < MAX_PHBS)
148 		clear_bit(phb->global_number, phb_bitmap);
149 
150 	list_del(&phb->list_node);
151 	spin_unlock(&hose_spinlock);
152 
153 	if (phb->is_dynamic)
154 		kfree(phb);
155 }
156 EXPORT_SYMBOL_GPL(pcibios_free_controller);
157 
158 /*
159  * This function is used to call pcibios_free_controller()
160  * in a deferred manner: a callback from the PCI subsystem.
161  *
162  * _*DO NOT*_ call pcibios_free_controller() explicitly if
163  * this is used (or it may access an invalid *phb pointer).
164  *
165  * The callback occurs when all references to the root bus
166  * are dropped (e.g., child buses/devices and their users).
167  *
168  * It's called as .release_fn() of 'struct pci_host_bridge'
169  * which is associated with the 'struct pci_controller.bus'
170  * (root bus) - it expects .release_data to hold a pointer
171  * to 'struct pci_controller'.
172  *
173  * In order to use it, register .release_fn()/release_data
174  * like this:
175  *
176  * pci_set_host_bridge_release(bridge,
177  *                             pcibios_free_controller_deferred
178  *                             (void *) phb);
179  *
180  * e.g. in the pcibios_root_bridge_prepare() callback from
181  * pci_create_root_bus().
182  */
183 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
184 {
185 	struct pci_controller *phb = (struct pci_controller *)
186 					 bridge->release_data;
187 
188 	pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
189 
190 	pcibios_free_controller(phb);
191 }
192 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
193 
194 /*
195  * The function is used to return the minimal alignment
196  * for memory or I/O windows of the associated P2P bridge.
197  * By default, 4KiB alignment for I/O windows and 1MiB for
198  * memory windows.
199  */
200 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
201 					 unsigned long type)
202 {
203 	struct pci_controller *phb = pci_bus_to_host(bus);
204 
205 	if (phb->controller_ops.window_alignment)
206 		return phb->controller_ops.window_alignment(bus, type);
207 
208 	/*
209 	 * PCI core will figure out the default
210 	 * alignment: 4KiB for I/O and 1MiB for
211 	 * memory window.
212 	 */
213 	return 1;
214 }
215 
216 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
217 {
218 	struct pci_controller *hose = pci_bus_to_host(bus);
219 
220 	if (hose->controller_ops.setup_bridge)
221 		hose->controller_ops.setup_bridge(bus, type);
222 }
223 
224 void pcibios_reset_secondary_bus(struct pci_dev *dev)
225 {
226 	struct pci_controller *phb = pci_bus_to_host(dev->bus);
227 
228 	if (phb->controller_ops.reset_secondary_bus) {
229 		phb->controller_ops.reset_secondary_bus(dev);
230 		return;
231 	}
232 
233 	pci_reset_secondary_bus(dev);
234 }
235 
236 resource_size_t pcibios_default_alignment(void)
237 {
238 	if (ppc_md.pcibios_default_alignment)
239 		return ppc_md.pcibios_default_alignment();
240 
241 	return 0;
242 }
243 
244 #ifdef CONFIG_PCI_IOV
245 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
246 {
247 	if (ppc_md.pcibios_iov_resource_alignment)
248 		return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
249 
250 	return pci_iov_resource_size(pdev, resno);
251 }
252 #endif /* CONFIG_PCI_IOV */
253 
254 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
255 {
256 #ifdef CONFIG_PPC64
257 	return hose->pci_io_size;
258 #else
259 	return resource_size(&hose->io_resource);
260 #endif
261 }
262 
263 int pcibios_vaddr_is_ioport(void __iomem *address)
264 {
265 	int ret = 0;
266 	struct pci_controller *hose;
267 	resource_size_t size;
268 
269 	spin_lock(&hose_spinlock);
270 	list_for_each_entry(hose, &hose_list, list_node) {
271 		size = pcibios_io_size(hose);
272 		if (address >= hose->io_base_virt &&
273 		    address < (hose->io_base_virt + size)) {
274 			ret = 1;
275 			break;
276 		}
277 	}
278 	spin_unlock(&hose_spinlock);
279 	return ret;
280 }
281 
282 unsigned long pci_address_to_pio(phys_addr_t address)
283 {
284 	struct pci_controller *hose;
285 	resource_size_t size;
286 	unsigned long ret = ~0;
287 
288 	spin_lock(&hose_spinlock);
289 	list_for_each_entry(hose, &hose_list, list_node) {
290 		size = pcibios_io_size(hose);
291 		if (address >= hose->io_base_phys &&
292 		    address < (hose->io_base_phys + size)) {
293 			unsigned long base =
294 				(unsigned long)hose->io_base_virt - _IO_BASE;
295 			ret = base + (address - hose->io_base_phys);
296 			break;
297 		}
298 	}
299 	spin_unlock(&hose_spinlock);
300 
301 	return ret;
302 }
303 EXPORT_SYMBOL_GPL(pci_address_to_pio);
304 
305 /*
306  * Return the domain number for this bus.
307  */
308 int pci_domain_nr(struct pci_bus *bus)
309 {
310 	struct pci_controller *hose = pci_bus_to_host(bus);
311 
312 	return hose->global_number;
313 }
314 EXPORT_SYMBOL(pci_domain_nr);
315 
316 /* This routine is meant to be used early during boot, when the
317  * PCI bus numbers have not yet been assigned, and you need to
318  * issue PCI config cycles to an OF device.
319  * It could also be used to "fix" RTAS config cycles if you want
320  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
321  * config cycles.
322  */
323 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
324 {
325 	while(node) {
326 		struct pci_controller *hose, *tmp;
327 		list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
328 			if (hose->dn == node)
329 				return hose;
330 		node = node->parent;
331 	}
332 	return NULL;
333 }
334 
335 /*
336  * Reads the interrupt pin to determine if interrupt is use by card.
337  * If the interrupt is used, then gets the interrupt line from the
338  * openfirmware and sets it in the pci_dev and pci_config line.
339  */
340 static int pci_read_irq_line(struct pci_dev *pci_dev)
341 {
342 	struct of_phandle_args oirq;
343 	unsigned int virq;
344 
345 	pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
346 
347 #ifdef DEBUG
348 	memset(&oirq, 0xff, sizeof(oirq));
349 #endif
350 	/* Try to get a mapping from the device-tree */
351 	if (of_irq_parse_pci(pci_dev, &oirq)) {
352 		u8 line, pin;
353 
354 		/* If that fails, lets fallback to what is in the config
355 		 * space and map that through the default controller. We
356 		 * also set the type to level low since that's what PCI
357 		 * interrupts are. If your platform does differently, then
358 		 * either provide a proper interrupt tree or don't use this
359 		 * function.
360 		 */
361 		if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
362 			return -1;
363 		if (pin == 0)
364 			return -1;
365 		if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
366 		    line == 0xff || line == 0) {
367 			return -1;
368 		}
369 		pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
370 			 line, pin);
371 
372 		virq = irq_create_mapping(NULL, line);
373 		if (virq)
374 			irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
375 	} else {
376 		pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %pOF\n",
377 			 oirq.args_count, oirq.args[0], oirq.args[1], oirq.np);
378 
379 		virq = irq_create_of_mapping(&oirq);
380 	}
381 
382 	if (!virq) {
383 		pr_debug(" Failed to map !\n");
384 		return -1;
385 	}
386 
387 	pr_debug(" Mapped to linux irq %d\n", virq);
388 
389 	pci_dev->irq = virq;
390 
391 	return 0;
392 }
393 
394 /*
395  * Platform support for /proc/bus/pci/X/Y mmap()s,
396  * modelled on the sparc64 implementation by Dave Miller.
397  *  -- paulus.
398  */
399 
400 /*
401  * Adjust vm_pgoff of VMA such that it is the physical page offset
402  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
403  *
404  * Basically, the user finds the base address for his device which he wishes
405  * to mmap.  They read the 32-bit value from the config space base register,
406  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
407  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
408  *
409  * Returns negative error code on failure, zero on success.
410  */
411 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
412 					       resource_size_t *offset,
413 					       enum pci_mmap_state mmap_state)
414 {
415 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
416 	unsigned long io_offset = 0;
417 	int i, res_bit;
418 
419 	if (hose == NULL)
420 		return NULL;		/* should never happen */
421 
422 	/* If memory, add on the PCI bridge address offset */
423 	if (mmap_state == pci_mmap_mem) {
424 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
425 		*offset += hose->pci_mem_offset;
426 #endif
427 		res_bit = IORESOURCE_MEM;
428 	} else {
429 		io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
430 		*offset += io_offset;
431 		res_bit = IORESOURCE_IO;
432 	}
433 
434 	/*
435 	 * Check that the offset requested corresponds to one of the
436 	 * resources of the device.
437 	 */
438 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
439 		struct resource *rp = &dev->resource[i];
440 		int flags = rp->flags;
441 
442 		/* treat ROM as memory (should be already) */
443 		if (i == PCI_ROM_RESOURCE)
444 			flags |= IORESOURCE_MEM;
445 
446 		/* Active and same type? */
447 		if ((flags & res_bit) == 0)
448 			continue;
449 
450 		/* In the range of this resource? */
451 		if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
452 			continue;
453 
454 		/* found it! construct the final physical address */
455 		if (mmap_state == pci_mmap_io)
456 			*offset += hose->io_base_phys - io_offset;
457 		return rp;
458 	}
459 
460 	return NULL;
461 }
462 
463 /*
464  * This one is used by /dev/mem and fbdev who have no clue about the
465  * PCI device, it tries to find the PCI device first and calls the
466  * above routine
467  */
468 pgprot_t pci_phys_mem_access_prot(struct file *file,
469 				  unsigned long pfn,
470 				  unsigned long size,
471 				  pgprot_t prot)
472 {
473 	struct pci_dev *pdev = NULL;
474 	struct resource *found = NULL;
475 	resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
476 	int i;
477 
478 	if (page_is_ram(pfn))
479 		return prot;
480 
481 	prot = pgprot_noncached(prot);
482 	for_each_pci_dev(pdev) {
483 		for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
484 			struct resource *rp = &pdev->resource[i];
485 			int flags = rp->flags;
486 
487 			/* Active and same type? */
488 			if ((flags & IORESOURCE_MEM) == 0)
489 				continue;
490 			/* In the range of this resource? */
491 			if (offset < (rp->start & PAGE_MASK) ||
492 			    offset > rp->end)
493 				continue;
494 			found = rp;
495 			break;
496 		}
497 		if (found)
498 			break;
499 	}
500 	if (found) {
501 		if (found->flags & IORESOURCE_PREFETCH)
502 			prot = pgprot_noncached_wc(prot);
503 		pci_dev_put(pdev);
504 	}
505 
506 	pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
507 		 (unsigned long long)offset, pgprot_val(prot));
508 
509 	return prot;
510 }
511 
512 
513 /*
514  * Perform the actual remap of the pages for a PCI device mapping, as
515  * appropriate for this architecture.  The region in the process to map
516  * is described by vm_start and vm_end members of VMA, the base physical
517  * address is found in vm_pgoff.
518  * The pci device structure is provided so that architectures may make mapping
519  * decisions on a per-device or per-bus basis.
520  *
521  * Returns a negative error code on failure, zero on success.
522  */
523 int pci_mmap_page_range(struct pci_dev *dev, int bar,
524 			struct vm_area_struct *vma,
525 			enum pci_mmap_state mmap_state, int write_combine)
526 {
527 	resource_size_t offset =
528 		((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
529 	struct resource *rp;
530 	int ret;
531 
532 	rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
533 	if (rp == NULL)
534 		return -EINVAL;
535 
536 	vma->vm_pgoff = offset >> PAGE_SHIFT;
537 	if (write_combine)
538 		vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
539 	else
540 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
541 
542 	ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
543 			       vma->vm_end - vma->vm_start, vma->vm_page_prot);
544 
545 	return ret;
546 }
547 
548 /* This provides legacy IO read access on a bus */
549 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
550 {
551 	unsigned long offset;
552 	struct pci_controller *hose = pci_bus_to_host(bus);
553 	struct resource *rp = &hose->io_resource;
554 	void __iomem *addr;
555 
556 	/* Check if port can be supported by that bus. We only check
557 	 * the ranges of the PHB though, not the bus itself as the rules
558 	 * for forwarding legacy cycles down bridges are not our problem
559 	 * here. So if the host bridge supports it, we do it.
560 	 */
561 	offset = (unsigned long)hose->io_base_virt - _IO_BASE;
562 	offset += port;
563 
564 	if (!(rp->flags & IORESOURCE_IO))
565 		return -ENXIO;
566 	if (offset < rp->start || (offset + size) > rp->end)
567 		return -ENXIO;
568 	addr = hose->io_base_virt + port;
569 
570 	switch(size) {
571 	case 1:
572 		*((u8 *)val) = in_8(addr);
573 		return 1;
574 	case 2:
575 		if (port & 1)
576 			return -EINVAL;
577 		*((u16 *)val) = in_le16(addr);
578 		return 2;
579 	case 4:
580 		if (port & 3)
581 			return -EINVAL;
582 		*((u32 *)val) = in_le32(addr);
583 		return 4;
584 	}
585 	return -EINVAL;
586 }
587 
588 /* This provides legacy IO write access on a bus */
589 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
590 {
591 	unsigned long offset;
592 	struct pci_controller *hose = pci_bus_to_host(bus);
593 	struct resource *rp = &hose->io_resource;
594 	void __iomem *addr;
595 
596 	/* Check if port can be supported by that bus. We only check
597 	 * the ranges of the PHB though, not the bus itself as the rules
598 	 * for forwarding legacy cycles down bridges are not our problem
599 	 * here. So if the host bridge supports it, we do it.
600 	 */
601 	offset = (unsigned long)hose->io_base_virt - _IO_BASE;
602 	offset += port;
603 
604 	if (!(rp->flags & IORESOURCE_IO))
605 		return -ENXIO;
606 	if (offset < rp->start || (offset + size) > rp->end)
607 		return -ENXIO;
608 	addr = hose->io_base_virt + port;
609 
610 	/* WARNING: The generic code is idiotic. It gets passed a pointer
611 	 * to what can be a 1, 2 or 4 byte quantity and always reads that
612 	 * as a u32, which means that we have to correct the location of
613 	 * the data read within those 32 bits for size 1 and 2
614 	 */
615 	switch(size) {
616 	case 1:
617 		out_8(addr, val >> 24);
618 		return 1;
619 	case 2:
620 		if (port & 1)
621 			return -EINVAL;
622 		out_le16(addr, val >> 16);
623 		return 2;
624 	case 4:
625 		if (port & 3)
626 			return -EINVAL;
627 		out_le32(addr, val);
628 		return 4;
629 	}
630 	return -EINVAL;
631 }
632 
633 /* This provides legacy IO or memory mmap access on a bus */
634 int pci_mmap_legacy_page_range(struct pci_bus *bus,
635 			       struct vm_area_struct *vma,
636 			       enum pci_mmap_state mmap_state)
637 {
638 	struct pci_controller *hose = pci_bus_to_host(bus);
639 	resource_size_t offset =
640 		((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
641 	resource_size_t size = vma->vm_end - vma->vm_start;
642 	struct resource *rp;
643 
644 	pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
645 		 pci_domain_nr(bus), bus->number,
646 		 mmap_state == pci_mmap_mem ? "MEM" : "IO",
647 		 (unsigned long long)offset,
648 		 (unsigned long long)(offset + size - 1));
649 
650 	if (mmap_state == pci_mmap_mem) {
651 		/* Hack alert !
652 		 *
653 		 * Because X is lame and can fail starting if it gets an error trying
654 		 * to mmap legacy_mem (instead of just moving on without legacy memory
655 		 * access) we fake it here by giving it anonymous memory, effectively
656 		 * behaving just like /dev/zero
657 		 */
658 		if ((offset + size) > hose->isa_mem_size) {
659 			printk(KERN_DEBUG
660 			       "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
661 			       current->comm, current->pid, pci_domain_nr(bus), bus->number);
662 			if (vma->vm_flags & VM_SHARED)
663 				return shmem_zero_setup(vma);
664 			return 0;
665 		}
666 		offset += hose->isa_mem_phys;
667 	} else {
668 		unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
669 		unsigned long roffset = offset + io_offset;
670 		rp = &hose->io_resource;
671 		if (!(rp->flags & IORESOURCE_IO))
672 			return -ENXIO;
673 		if (roffset < rp->start || (roffset + size) > rp->end)
674 			return -ENXIO;
675 		offset += hose->io_base_phys;
676 	}
677 	pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
678 
679 	vma->vm_pgoff = offset >> PAGE_SHIFT;
680 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
681 	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
682 			       vma->vm_end - vma->vm_start,
683 			       vma->vm_page_prot);
684 }
685 
686 void pci_resource_to_user(const struct pci_dev *dev, int bar,
687 			  const struct resource *rsrc,
688 			  resource_size_t *start, resource_size_t *end)
689 {
690 	struct pci_bus_region region;
691 
692 	if (rsrc->flags & IORESOURCE_IO) {
693 		pcibios_resource_to_bus(dev->bus, &region,
694 					(struct resource *) rsrc);
695 		*start = region.start;
696 		*end = region.end;
697 		return;
698 	}
699 
700 	/* We pass a CPU physical address to userland for MMIO instead of a
701 	 * BAR value because X is lame and expects to be able to use that
702 	 * to pass to /dev/mem!
703 	 *
704 	 * That means we may have 64-bit values where some apps only expect
705 	 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
706 	 */
707 	*start = rsrc->start;
708 	*end = rsrc->end;
709 }
710 
711 /**
712  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
713  * @hose: newly allocated pci_controller to be setup
714  * @dev: device node of the host bridge
715  * @primary: set if primary bus (32 bits only, soon to be deprecated)
716  *
717  * This function will parse the "ranges" property of a PCI host bridge device
718  * node and setup the resource mapping of a pci controller based on its
719  * content.
720  *
721  * Life would be boring if it wasn't for a few issues that we have to deal
722  * with here:
723  *
724  *   - We can only cope with one IO space range and up to 3 Memory space
725  *     ranges. However, some machines (thanks Apple !) tend to split their
726  *     space into lots of small contiguous ranges. So we have to coalesce.
727  *
728  *   - Some busses have IO space not starting at 0, which causes trouble with
729  *     the way we do our IO resource renumbering. The code somewhat deals with
730  *     it for 64 bits but I would expect problems on 32 bits.
731  *
732  *   - Some 32 bits platforms such as 4xx can have physical space larger than
733  *     32 bits so we need to use 64 bits values for the parsing
734  */
735 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
736 				  struct device_node *dev, int primary)
737 {
738 	int memno = 0;
739 	struct resource *res;
740 	struct of_pci_range range;
741 	struct of_pci_range_parser parser;
742 
743 	printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
744 	       dev, primary ? "(primary)" : "");
745 
746 	/* Check for ranges property */
747 	if (of_pci_range_parser_init(&parser, dev))
748 		return;
749 
750 	/* Parse it */
751 	for_each_of_pci_range(&parser, &range) {
752 		/* If we failed translation or got a zero-sized region
753 		 * (some FW try to feed us with non sensical zero sized regions
754 		 * such as power3 which look like some kind of attempt at exposing
755 		 * the VGA memory hole)
756 		 */
757 		if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
758 			continue;
759 
760 		/* Act based on address space type */
761 		res = NULL;
762 		switch (range.flags & IORESOURCE_TYPE_BITS) {
763 		case IORESOURCE_IO:
764 			printk(KERN_INFO
765 			       "  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
766 			       range.cpu_addr, range.cpu_addr + range.size - 1,
767 			       range.pci_addr);
768 
769 			/* We support only one IO range */
770 			if (hose->pci_io_size) {
771 				printk(KERN_INFO
772 				       " \\--> Skipped (too many) !\n");
773 				continue;
774 			}
775 #ifdef CONFIG_PPC32
776 			/* On 32 bits, limit I/O space to 16MB */
777 			if (range.size > 0x01000000)
778 				range.size = 0x01000000;
779 
780 			/* 32 bits needs to map IOs here */
781 			hose->io_base_virt = ioremap(range.cpu_addr,
782 						range.size);
783 
784 			/* Expect trouble if pci_addr is not 0 */
785 			if (primary)
786 				isa_io_base =
787 					(unsigned long)hose->io_base_virt;
788 #endif /* CONFIG_PPC32 */
789 			/* pci_io_size and io_base_phys always represent IO
790 			 * space starting at 0 so we factor in pci_addr
791 			 */
792 			hose->pci_io_size = range.pci_addr + range.size;
793 			hose->io_base_phys = range.cpu_addr - range.pci_addr;
794 
795 			/* Build resource */
796 			res = &hose->io_resource;
797 			range.cpu_addr = range.pci_addr;
798 			break;
799 		case IORESOURCE_MEM:
800 			printk(KERN_INFO
801 			       " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
802 			       range.cpu_addr, range.cpu_addr + range.size - 1,
803 			       range.pci_addr,
804 			       (range.pci_space & 0x40000000) ?
805 			       "Prefetch" : "");
806 
807 			/* We support only 3 memory ranges */
808 			if (memno >= 3) {
809 				printk(KERN_INFO
810 				       " \\--> Skipped (too many) !\n");
811 				continue;
812 			}
813 			/* Handles ISA memory hole space here */
814 			if (range.pci_addr == 0) {
815 				if (primary || isa_mem_base == 0)
816 					isa_mem_base = range.cpu_addr;
817 				hose->isa_mem_phys = range.cpu_addr;
818 				hose->isa_mem_size = range.size;
819 			}
820 
821 			/* Build resource */
822 			hose->mem_offset[memno] = range.cpu_addr -
823 							range.pci_addr;
824 			res = &hose->mem_resources[memno++];
825 			break;
826 		}
827 		if (res != NULL) {
828 			res->name = dev->full_name;
829 			res->flags = range.flags;
830 			res->start = range.cpu_addr;
831 			res->end = range.cpu_addr + range.size - 1;
832 			res->parent = res->child = res->sibling = NULL;
833 		}
834 	}
835 }
836 
837 /* Decide whether to display the domain number in /proc */
838 int pci_proc_domain(struct pci_bus *bus)
839 {
840 	struct pci_controller *hose = pci_bus_to_host(bus);
841 
842 	if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
843 		return 0;
844 	if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
845 		return hose->global_number != 0;
846 	return 1;
847 }
848 
849 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
850 {
851 	if (ppc_md.pcibios_root_bridge_prepare)
852 		return ppc_md.pcibios_root_bridge_prepare(bridge);
853 
854 	return 0;
855 }
856 
857 /* This header fixup will do the resource fixup for all devices as they are
858  * probed, but not for bridge ranges
859  */
860 static void pcibios_fixup_resources(struct pci_dev *dev)
861 {
862 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
863 	int i;
864 
865 	if (!hose) {
866 		printk(KERN_ERR "No host bridge for PCI dev %s !\n",
867 		       pci_name(dev));
868 		return;
869 	}
870 
871 	if (dev->is_virtfn)
872 		return;
873 
874 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
875 		struct resource *res = dev->resource + i;
876 		struct pci_bus_region reg;
877 		if (!res->flags)
878 			continue;
879 
880 		/* If we're going to re-assign everything, we mark all resources
881 		 * as unset (and 0-base them). In addition, we mark BARs starting
882 		 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
883 		 * since in that case, we don't want to re-assign anything
884 		 */
885 		pcibios_resource_to_bus(dev->bus, &reg, res);
886 		if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
887 		    (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
888 			/* Only print message if not re-assigning */
889 			if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
890 				pr_debug("PCI:%s Resource %d %pR is unassigned\n",
891 					 pci_name(dev), i, res);
892 			res->end -= res->start;
893 			res->start = 0;
894 			res->flags |= IORESOURCE_UNSET;
895 			continue;
896 		}
897 
898 		pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
899 	}
900 
901 	/* Call machine specific resource fixup */
902 	if (ppc_md.pcibios_fixup_resources)
903 		ppc_md.pcibios_fixup_resources(dev);
904 }
905 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
906 
907 /* This function tries to figure out if a bridge resource has been initialized
908  * by the firmware or not. It doesn't have to be absolutely bullet proof, but
909  * things go more smoothly when it gets it right. It should covers cases such
910  * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
911  */
912 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
913 						 struct resource *res)
914 {
915 	struct pci_controller *hose = pci_bus_to_host(bus);
916 	struct pci_dev *dev = bus->self;
917 	resource_size_t offset;
918 	struct pci_bus_region region;
919 	u16 command;
920 	int i;
921 
922 	/* We don't do anything if PCI_PROBE_ONLY is set */
923 	if (pci_has_flag(PCI_PROBE_ONLY))
924 		return 0;
925 
926 	/* Job is a bit different between memory and IO */
927 	if (res->flags & IORESOURCE_MEM) {
928 		pcibios_resource_to_bus(dev->bus, &region, res);
929 
930 		/* If the BAR is non-0 then it's probably been initialized */
931 		if (region.start != 0)
932 			return 0;
933 
934 		/* The BAR is 0, let's check if memory decoding is enabled on
935 		 * the bridge. If not, we consider it unassigned
936 		 */
937 		pci_read_config_word(dev, PCI_COMMAND, &command);
938 		if ((command & PCI_COMMAND_MEMORY) == 0)
939 			return 1;
940 
941 		/* Memory decoding is enabled and the BAR is 0. If any of the bridge
942 		 * resources covers that starting address (0 then it's good enough for
943 		 * us for memory space)
944 		 */
945 		for (i = 0; i < 3; i++) {
946 			if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
947 			    hose->mem_resources[i].start == hose->mem_offset[i])
948 				return 0;
949 		}
950 
951 		/* Well, it starts at 0 and we know it will collide so we may as
952 		 * well consider it as unassigned. That covers the Apple case.
953 		 */
954 		return 1;
955 	} else {
956 		/* If the BAR is non-0, then we consider it assigned */
957 		offset = (unsigned long)hose->io_base_virt - _IO_BASE;
958 		if (((res->start - offset) & 0xfffffffful) != 0)
959 			return 0;
960 
961 		/* Here, we are a bit different than memory as typically IO space
962 		 * starting at low addresses -is- valid. What we do instead if that
963 		 * we consider as unassigned anything that doesn't have IO enabled
964 		 * in the PCI command register, and that's it.
965 		 */
966 		pci_read_config_word(dev, PCI_COMMAND, &command);
967 		if (command & PCI_COMMAND_IO)
968 			return 0;
969 
970 		/* It's starting at 0 and IO is disabled in the bridge, consider
971 		 * it unassigned
972 		 */
973 		return 1;
974 	}
975 }
976 
977 /* Fixup resources of a PCI<->PCI bridge */
978 static void pcibios_fixup_bridge(struct pci_bus *bus)
979 {
980 	struct resource *res;
981 	int i;
982 
983 	struct pci_dev *dev = bus->self;
984 
985 	pci_bus_for_each_resource(bus, res, i) {
986 		if (!res || !res->flags)
987 			continue;
988 		if (i >= 3 && bus->self->transparent)
989 			continue;
990 
991 		/* If we're going to reassign everything, we can
992 		 * shrink the P2P resource to have size as being
993 		 * of 0 in order to save space.
994 		 */
995 		if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
996 			res->flags |= IORESOURCE_UNSET;
997 			res->start = 0;
998 			res->end = -1;
999 			continue;
1000 		}
1001 
1002 		pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
1003 
1004 		/* Try to detect uninitialized P2P bridge resources,
1005 		 * and clear them out so they get re-assigned later
1006 		 */
1007 		if (pcibios_uninitialized_bridge_resource(bus, res)) {
1008 			res->flags = 0;
1009 			pr_debug("PCI:%s            (unassigned)\n", pci_name(dev));
1010 		}
1011 	}
1012 }
1013 
1014 void pcibios_setup_bus_self(struct pci_bus *bus)
1015 {
1016 	struct pci_controller *phb;
1017 
1018 	/* Fix up the bus resources for P2P bridges */
1019 	if (bus->self != NULL)
1020 		pcibios_fixup_bridge(bus);
1021 
1022 	/* Platform specific bus fixups. This is currently only used
1023 	 * by fsl_pci and I'm hoping to get rid of it at some point
1024 	 */
1025 	if (ppc_md.pcibios_fixup_bus)
1026 		ppc_md.pcibios_fixup_bus(bus);
1027 
1028 	/* Setup bus DMA mappings */
1029 	phb = pci_bus_to_host(bus);
1030 	if (phb->controller_ops.dma_bus_setup)
1031 		phb->controller_ops.dma_bus_setup(bus);
1032 }
1033 
1034 static void pcibios_setup_device(struct pci_dev *dev)
1035 {
1036 	struct pci_controller *phb;
1037 	/* Fixup NUMA node as it may not be setup yet by the generic
1038 	 * code and is needed by the DMA init
1039 	 */
1040 	set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1041 
1042 	/* Hook up default DMA ops */
1043 	set_dma_ops(&dev->dev, pci_dma_ops);
1044 	set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1045 
1046 	/* Additional platform DMA/iommu setup */
1047 	phb = pci_bus_to_host(dev->bus);
1048 	if (phb->controller_ops.dma_dev_setup)
1049 		phb->controller_ops.dma_dev_setup(dev);
1050 
1051 	/* Read default IRQs and fixup if necessary */
1052 	pci_read_irq_line(dev);
1053 	if (ppc_md.pci_irq_fixup)
1054 		ppc_md.pci_irq_fixup(dev);
1055 }
1056 
1057 int pcibios_add_device(struct pci_dev *dev)
1058 {
1059 	/*
1060 	 * We can only call pcibios_setup_device() after bus setup is complete,
1061 	 * since some of the platform specific DMA setup code depends on it.
1062 	 */
1063 	if (dev->bus->is_added)
1064 		pcibios_setup_device(dev);
1065 
1066 #ifdef CONFIG_PCI_IOV
1067 	if (ppc_md.pcibios_fixup_sriov)
1068 		ppc_md.pcibios_fixup_sriov(dev);
1069 #endif /* CONFIG_PCI_IOV */
1070 
1071 	return 0;
1072 }
1073 
1074 void pcibios_setup_bus_devices(struct pci_bus *bus)
1075 {
1076 	struct pci_dev *dev;
1077 
1078 	pr_debug("PCI: Fixup bus devices %d (%s)\n",
1079 		 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1080 
1081 	list_for_each_entry(dev, &bus->devices, bus_list) {
1082 		/* Cardbus can call us to add new devices to a bus, so ignore
1083 		 * those who are already fully discovered
1084 		 */
1085 		if (dev->is_added)
1086 			continue;
1087 
1088 		pcibios_setup_device(dev);
1089 	}
1090 }
1091 
1092 void pcibios_set_master(struct pci_dev *dev)
1093 {
1094 	/* No special bus mastering setup handling */
1095 }
1096 
1097 void pcibios_fixup_bus(struct pci_bus *bus)
1098 {
1099 	/* When called from the generic PCI probe, read PCI<->PCI bridge
1100 	 * bases. This is -not- called when generating the PCI tree from
1101 	 * the OF device-tree.
1102 	 */
1103 	pci_read_bridge_bases(bus);
1104 
1105 	/* Now fixup the bus bus */
1106 	pcibios_setup_bus_self(bus);
1107 
1108 	/* Now fixup devices on that bus */
1109 	pcibios_setup_bus_devices(bus);
1110 }
1111 EXPORT_SYMBOL(pcibios_fixup_bus);
1112 
1113 void pci_fixup_cardbus(struct pci_bus *bus)
1114 {
1115 	/* Now fixup devices on that bus */
1116 	pcibios_setup_bus_devices(bus);
1117 }
1118 
1119 
1120 static int skip_isa_ioresource_align(struct pci_dev *dev)
1121 {
1122 	if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1123 	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1124 		return 1;
1125 	return 0;
1126 }
1127 
1128 /*
1129  * We need to avoid collisions with `mirrored' VGA ports
1130  * and other strange ISA hardware, so we always want the
1131  * addresses to be allocated in the 0x000-0x0ff region
1132  * modulo 0x400.
1133  *
1134  * Why? Because some silly external IO cards only decode
1135  * the low 10 bits of the IO address. The 0x00-0xff region
1136  * is reserved for motherboard devices that decode all 16
1137  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1138  * but we want to try to avoid allocating at 0x2900-0x2bff
1139  * which might have be mirrored at 0x0100-0x03ff..
1140  */
1141 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1142 				resource_size_t size, resource_size_t align)
1143 {
1144 	struct pci_dev *dev = data;
1145 	resource_size_t start = res->start;
1146 
1147 	if (res->flags & IORESOURCE_IO) {
1148 		if (skip_isa_ioresource_align(dev))
1149 			return start;
1150 		if (start & 0x300)
1151 			start = (start + 0x3ff) & ~0x3ff;
1152 	}
1153 
1154 	return start;
1155 }
1156 EXPORT_SYMBOL(pcibios_align_resource);
1157 
1158 /*
1159  * Reparent resource children of pr that conflict with res
1160  * under res, and make res replace those children.
1161  */
1162 static int reparent_resources(struct resource *parent,
1163 				     struct resource *res)
1164 {
1165 	struct resource *p, **pp;
1166 	struct resource **firstpp = NULL;
1167 
1168 	for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1169 		if (p->end < res->start)
1170 			continue;
1171 		if (res->end < p->start)
1172 			break;
1173 		if (p->start < res->start || p->end > res->end)
1174 			return -1;	/* not completely contained */
1175 		if (firstpp == NULL)
1176 			firstpp = pp;
1177 	}
1178 	if (firstpp == NULL)
1179 		return -1;	/* didn't find any conflicting entries? */
1180 	res->parent = parent;
1181 	res->child = *firstpp;
1182 	res->sibling = *pp;
1183 	*firstpp = res;
1184 	*pp = NULL;
1185 	for (p = res->child; p != NULL; p = p->sibling) {
1186 		p->parent = res;
1187 		pr_debug("PCI: Reparented %s %pR under %s\n",
1188 			 p->name, p, res->name);
1189 	}
1190 	return 0;
1191 }
1192 
1193 /*
1194  *  Handle resources of PCI devices.  If the world were perfect, we could
1195  *  just allocate all the resource regions and do nothing more.  It isn't.
1196  *  On the other hand, we cannot just re-allocate all devices, as it would
1197  *  require us to know lots of host bridge internals.  So we attempt to
1198  *  keep as much of the original configuration as possible, but tweak it
1199  *  when it's found to be wrong.
1200  *
1201  *  Known BIOS problems we have to work around:
1202  *	- I/O or memory regions not configured
1203  *	- regions configured, but not enabled in the command register
1204  *	- bogus I/O addresses above 64K used
1205  *	- expansion ROMs left enabled (this may sound harmless, but given
1206  *	  the fact the PCI specs explicitly allow address decoders to be
1207  *	  shared between expansion ROMs and other resource regions, it's
1208  *	  at least dangerous)
1209  *
1210  *  Our solution:
1211  *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
1212  *	    This gives us fixed barriers on where we can allocate.
1213  *	(2) Allocate resources for all enabled devices.  If there is
1214  *	    a collision, just mark the resource as unallocated. Also
1215  *	    disable expansion ROMs during this step.
1216  *	(3) Try to allocate resources for disabled devices.  If the
1217  *	    resources were assigned correctly, everything goes well,
1218  *	    if they weren't, they won't disturb allocation of other
1219  *	    resources.
1220  *	(4) Assign new addresses to resources which were either
1221  *	    not configured at all or misconfigured.  If explicitly
1222  *	    requested by the user, configure expansion ROM address
1223  *	    as well.
1224  */
1225 
1226 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1227 {
1228 	struct pci_bus *b;
1229 	int i;
1230 	struct resource *res, *pr;
1231 
1232 	pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1233 		 pci_domain_nr(bus), bus->number);
1234 
1235 	pci_bus_for_each_resource(bus, res, i) {
1236 		if (!res || !res->flags || res->start > res->end || res->parent)
1237 			continue;
1238 
1239 		/* If the resource was left unset at this point, we clear it */
1240 		if (res->flags & IORESOURCE_UNSET)
1241 			goto clear_resource;
1242 
1243 		if (bus->parent == NULL)
1244 			pr = (res->flags & IORESOURCE_IO) ?
1245 				&ioport_resource : &iomem_resource;
1246 		else {
1247 			pr = pci_find_parent_resource(bus->self, res);
1248 			if (pr == res) {
1249 				/* this happens when the generic PCI
1250 				 * code (wrongly) decides that this
1251 				 * bridge is transparent  -- paulus
1252 				 */
1253 				continue;
1254 			}
1255 		}
1256 
1257 		pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1258 			 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1259 			 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1260 
1261 		if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1262 			struct pci_dev *dev = bus->self;
1263 
1264 			if (request_resource(pr, res) == 0)
1265 				continue;
1266 			/*
1267 			 * Must be a conflict with an existing entry.
1268 			 * Move that entry (or entries) under the
1269 			 * bridge resource and try again.
1270 			 */
1271 			if (reparent_resources(pr, res) == 0)
1272 				continue;
1273 
1274 			if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1275 			    pci_claim_bridge_resource(dev,
1276 						i + PCI_BRIDGE_RESOURCES) == 0)
1277 				continue;
1278 		}
1279 		pr_warning("PCI: Cannot allocate resource region "
1280 			   "%d of PCI bridge %d, will remap\n", i, bus->number);
1281 	clear_resource:
1282 		/* The resource might be figured out when doing
1283 		 * reassignment based on the resources required
1284 		 * by the downstream PCI devices. Here we set
1285 		 * the size of the resource to be 0 in order to
1286 		 * save more space.
1287 		 */
1288 		res->start = 0;
1289 		res->end = -1;
1290 		res->flags = 0;
1291 	}
1292 
1293 	list_for_each_entry(b, &bus->children, node)
1294 		pcibios_allocate_bus_resources(b);
1295 }
1296 
1297 static inline void alloc_resource(struct pci_dev *dev, int idx)
1298 {
1299 	struct resource *pr, *r = &dev->resource[idx];
1300 
1301 	pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1302 		 pci_name(dev), idx, r);
1303 
1304 	pr = pci_find_parent_resource(dev, r);
1305 	if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1306 	    request_resource(pr, r) < 0) {
1307 		printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1308 		       " of device %s, will remap\n", idx, pci_name(dev));
1309 		if (pr)
1310 			pr_debug("PCI:  parent is %p: %pR\n", pr, pr);
1311 		/* We'll assign a new address later */
1312 		r->flags |= IORESOURCE_UNSET;
1313 		r->end -= r->start;
1314 		r->start = 0;
1315 	}
1316 }
1317 
1318 static void __init pcibios_allocate_resources(int pass)
1319 {
1320 	struct pci_dev *dev = NULL;
1321 	int idx, disabled;
1322 	u16 command;
1323 	struct resource *r;
1324 
1325 	for_each_pci_dev(dev) {
1326 		pci_read_config_word(dev, PCI_COMMAND, &command);
1327 		for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1328 			r = &dev->resource[idx];
1329 			if (r->parent)		/* Already allocated */
1330 				continue;
1331 			if (!r->flags || (r->flags & IORESOURCE_UNSET))
1332 				continue;	/* Not assigned at all */
1333 			/* We only allocate ROMs on pass 1 just in case they
1334 			 * have been screwed up by firmware
1335 			 */
1336 			if (idx == PCI_ROM_RESOURCE )
1337 				disabled = 1;
1338 			if (r->flags & IORESOURCE_IO)
1339 				disabled = !(command & PCI_COMMAND_IO);
1340 			else
1341 				disabled = !(command & PCI_COMMAND_MEMORY);
1342 			if (pass == disabled)
1343 				alloc_resource(dev, idx);
1344 		}
1345 		if (pass)
1346 			continue;
1347 		r = &dev->resource[PCI_ROM_RESOURCE];
1348 		if (r->flags) {
1349 			/* Turn the ROM off, leave the resource region,
1350 			 * but keep it unregistered.
1351 			 */
1352 			u32 reg;
1353 			pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1354 			if (reg & PCI_ROM_ADDRESS_ENABLE) {
1355 				pr_debug("PCI: Switching off ROM of %s\n",
1356 					 pci_name(dev));
1357 				r->flags &= ~IORESOURCE_ROM_ENABLE;
1358 				pci_write_config_dword(dev, dev->rom_base_reg,
1359 						       reg & ~PCI_ROM_ADDRESS_ENABLE);
1360 			}
1361 		}
1362 	}
1363 }
1364 
1365 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1366 {
1367 	struct pci_controller *hose = pci_bus_to_host(bus);
1368 	resource_size_t	offset;
1369 	struct resource *res, *pres;
1370 	int i;
1371 
1372 	pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1373 
1374 	/* Check for IO */
1375 	if (!(hose->io_resource.flags & IORESOURCE_IO))
1376 		goto no_io;
1377 	offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1378 	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1379 	BUG_ON(res == NULL);
1380 	res->name = "Legacy IO";
1381 	res->flags = IORESOURCE_IO;
1382 	res->start = offset;
1383 	res->end = (offset + 0xfff) & 0xfffffffful;
1384 	pr_debug("Candidate legacy IO: %pR\n", res);
1385 	if (request_resource(&hose->io_resource, res)) {
1386 		printk(KERN_DEBUG
1387 		       "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1388 		       pci_domain_nr(bus), bus->number, res);
1389 		kfree(res);
1390 	}
1391 
1392  no_io:
1393 	/* Check for memory */
1394 	for (i = 0; i < 3; i++) {
1395 		pres = &hose->mem_resources[i];
1396 		offset = hose->mem_offset[i];
1397 		if (!(pres->flags & IORESOURCE_MEM))
1398 			continue;
1399 		pr_debug("hose mem res: %pR\n", pres);
1400 		if ((pres->start - offset) <= 0xa0000 &&
1401 		    (pres->end - offset) >= 0xbffff)
1402 			break;
1403 	}
1404 	if (i >= 3)
1405 		return;
1406 	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1407 	BUG_ON(res == NULL);
1408 	res->name = "Legacy VGA memory";
1409 	res->flags = IORESOURCE_MEM;
1410 	res->start = 0xa0000 + offset;
1411 	res->end = 0xbffff + offset;
1412 	pr_debug("Candidate VGA memory: %pR\n", res);
1413 	if (request_resource(pres, res)) {
1414 		printk(KERN_DEBUG
1415 		       "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1416 		       pci_domain_nr(bus), bus->number, res);
1417 		kfree(res);
1418 	}
1419 }
1420 
1421 void __init pcibios_resource_survey(void)
1422 {
1423 	struct pci_bus *b;
1424 
1425 	/* Allocate and assign resources */
1426 	list_for_each_entry(b, &pci_root_buses, node)
1427 		pcibios_allocate_bus_resources(b);
1428 	if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1429 		pcibios_allocate_resources(0);
1430 		pcibios_allocate_resources(1);
1431 	}
1432 
1433 	/* Before we start assigning unassigned resource, we try to reserve
1434 	 * the low IO area and the VGA memory area if they intersect the
1435 	 * bus available resources to avoid allocating things on top of them
1436 	 */
1437 	if (!pci_has_flag(PCI_PROBE_ONLY)) {
1438 		list_for_each_entry(b, &pci_root_buses, node)
1439 			pcibios_reserve_legacy_regions(b);
1440 	}
1441 
1442 	/* Now, if the platform didn't decide to blindly trust the firmware,
1443 	 * we proceed to assigning things that were left unassigned
1444 	 */
1445 	if (!pci_has_flag(PCI_PROBE_ONLY)) {
1446 		pr_debug("PCI: Assigning unassigned resources...\n");
1447 		pci_assign_unassigned_resources();
1448 	}
1449 
1450 	/* Call machine dependent fixup */
1451 	if (ppc_md.pcibios_fixup)
1452 		ppc_md.pcibios_fixup();
1453 }
1454 
1455 /* This is used by the PCI hotplug driver to allocate resource
1456  * of newly plugged busses. We can try to consolidate with the
1457  * rest of the code later, for now, keep it as-is as our main
1458  * resource allocation function doesn't deal with sub-trees yet.
1459  */
1460 void pcibios_claim_one_bus(struct pci_bus *bus)
1461 {
1462 	struct pci_dev *dev;
1463 	struct pci_bus *child_bus;
1464 
1465 	list_for_each_entry(dev, &bus->devices, bus_list) {
1466 		int i;
1467 
1468 		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1469 			struct resource *r = &dev->resource[i];
1470 
1471 			if (r->parent || !r->start || !r->flags)
1472 				continue;
1473 
1474 			pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1475 				 pci_name(dev), i, r);
1476 
1477 			if (pci_claim_resource(dev, i) == 0)
1478 				continue;
1479 
1480 			pci_claim_bridge_resource(dev, i);
1481 		}
1482 	}
1483 
1484 	list_for_each_entry(child_bus, &bus->children, node)
1485 		pcibios_claim_one_bus(child_bus);
1486 }
1487 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1488 
1489 
1490 /* pcibios_finish_adding_to_bus
1491  *
1492  * This is to be called by the hotplug code after devices have been
1493  * added to a bus, this include calling it for a PHB that is just
1494  * being added
1495  */
1496 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1497 {
1498 	pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1499 		 pci_domain_nr(bus), bus->number);
1500 
1501 	/* Allocate bus and devices resources */
1502 	pcibios_allocate_bus_resources(bus);
1503 	pcibios_claim_one_bus(bus);
1504 	if (!pci_has_flag(PCI_PROBE_ONLY)) {
1505 		if (bus->self)
1506 			pci_assign_unassigned_bridge_resources(bus->self);
1507 		else
1508 			pci_assign_unassigned_bus_resources(bus);
1509 	}
1510 
1511 	/* Fixup EEH */
1512 	eeh_add_device_tree_late(bus);
1513 
1514 	/* Add new devices to global lists.  Register in proc, sysfs. */
1515 	pci_bus_add_devices(bus);
1516 
1517 	/* sysfs files should only be added after devices are added */
1518 	eeh_add_sysfs_files(bus);
1519 }
1520 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1521 
1522 int pcibios_enable_device(struct pci_dev *dev, int mask)
1523 {
1524 	struct pci_controller *phb = pci_bus_to_host(dev->bus);
1525 
1526 	if (phb->controller_ops.enable_device_hook)
1527 		if (!phb->controller_ops.enable_device_hook(dev))
1528 			return -EINVAL;
1529 
1530 	return pci_enable_resources(dev, mask);
1531 }
1532 
1533 void pcibios_disable_device(struct pci_dev *dev)
1534 {
1535 	struct pci_controller *phb = pci_bus_to_host(dev->bus);
1536 
1537 	if (phb->controller_ops.disable_device)
1538 		phb->controller_ops.disable_device(dev);
1539 }
1540 
1541 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1542 {
1543 	return (unsigned long) hose->io_base_virt - _IO_BASE;
1544 }
1545 
1546 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1547 					struct list_head *resources)
1548 {
1549 	struct resource *res;
1550 	resource_size_t offset;
1551 	int i;
1552 
1553 	/* Hookup PHB IO resource */
1554 	res = &hose->io_resource;
1555 
1556 	if (!res->flags) {
1557 		pr_debug("PCI: I/O resource not set for host"
1558 			 " bridge %pOF (domain %d)\n",
1559 			 hose->dn, hose->global_number);
1560 	} else {
1561 		offset = pcibios_io_space_offset(hose);
1562 
1563 		pr_debug("PCI: PHB IO resource    = %pR off 0x%08llx\n",
1564 			 res, (unsigned long long)offset);
1565 		pci_add_resource_offset(resources, res, offset);
1566 	}
1567 
1568 	/* Hookup PHB Memory resources */
1569 	for (i = 0; i < 3; ++i) {
1570 		res = &hose->mem_resources[i];
1571 		if (!res->flags)
1572 			continue;
1573 
1574 		offset = hose->mem_offset[i];
1575 		pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1576 			 res, (unsigned long long)offset);
1577 
1578 		pci_add_resource_offset(resources, res, offset);
1579 	}
1580 }
1581 
1582 /*
1583  * Null PCI config access functions, for the case when we can't
1584  * find a hose.
1585  */
1586 #define NULL_PCI_OP(rw, size, type)					\
1587 static int								\
1588 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)	\
1589 {									\
1590 	return PCIBIOS_DEVICE_NOT_FOUND;    				\
1591 }
1592 
1593 static int
1594 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1595 		 int len, u32 *val)
1596 {
1597 	return PCIBIOS_DEVICE_NOT_FOUND;
1598 }
1599 
1600 static int
1601 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1602 		  int len, u32 val)
1603 {
1604 	return PCIBIOS_DEVICE_NOT_FOUND;
1605 }
1606 
1607 static struct pci_ops null_pci_ops =
1608 {
1609 	.read = null_read_config,
1610 	.write = null_write_config,
1611 };
1612 
1613 /*
1614  * These functions are used early on before PCI scanning is done
1615  * and all of the pci_dev and pci_bus structures have been created.
1616  */
1617 static struct pci_bus *
1618 fake_pci_bus(struct pci_controller *hose, int busnr)
1619 {
1620 	static struct pci_bus bus;
1621 
1622 	if (hose == NULL) {
1623 		printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1624 	}
1625 	bus.number = busnr;
1626 	bus.sysdata = hose;
1627 	bus.ops = hose? hose->ops: &null_pci_ops;
1628 	return &bus;
1629 }
1630 
1631 #define EARLY_PCI_OP(rw, size, type)					\
1632 int early_##rw##_config_##size(struct pci_controller *hose, int bus,	\
1633 			       int devfn, int offset, type value)	\
1634 {									\
1635 	return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),	\
1636 					    devfn, offset, value);	\
1637 }
1638 
1639 EARLY_PCI_OP(read, byte, u8 *)
1640 EARLY_PCI_OP(read, word, u16 *)
1641 EARLY_PCI_OP(read, dword, u32 *)
1642 EARLY_PCI_OP(write, byte, u8)
1643 EARLY_PCI_OP(write, word, u16)
1644 EARLY_PCI_OP(write, dword, u32)
1645 
1646 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1647 			  int cap)
1648 {
1649 	return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1650 }
1651 
1652 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1653 {
1654 	struct pci_controller *hose = bus->sysdata;
1655 
1656 	return of_node_get(hose->dn);
1657 }
1658 
1659 /**
1660  * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1661  * @hose: Pointer to the PCI host controller instance structure
1662  */
1663 void pcibios_scan_phb(struct pci_controller *hose)
1664 {
1665 	LIST_HEAD(resources);
1666 	struct pci_bus *bus;
1667 	struct device_node *node = hose->dn;
1668 	int mode;
1669 
1670 	pr_debug("PCI: Scanning PHB %pOF\n", node);
1671 
1672 	/* Get some IO space for the new PHB */
1673 	pcibios_setup_phb_io_space(hose);
1674 
1675 	/* Wire up PHB bus resources */
1676 	pcibios_setup_phb_resources(hose, &resources);
1677 
1678 	hose->busn.start = hose->first_busno;
1679 	hose->busn.end	 = hose->last_busno;
1680 	hose->busn.flags = IORESOURCE_BUS;
1681 	pci_add_resource(&resources, &hose->busn);
1682 
1683 	/* Create an empty bus for the toplevel */
1684 	bus = pci_create_root_bus(hose->parent, hose->first_busno,
1685 				  hose->ops, hose, &resources);
1686 	if (bus == NULL) {
1687 		pr_err("Failed to create bus for PCI domain %04x\n",
1688 			hose->global_number);
1689 		pci_free_resource_list(&resources);
1690 		return;
1691 	}
1692 	hose->bus = bus;
1693 
1694 	/* Get probe mode and perform scan */
1695 	mode = PCI_PROBE_NORMAL;
1696 	if (node && hose->controller_ops.probe_mode)
1697 		mode = hose->controller_ops.probe_mode(bus);
1698 	pr_debug("    probe mode: %d\n", mode);
1699 	if (mode == PCI_PROBE_DEVTREE)
1700 		of_scan_bus(node, bus);
1701 
1702 	if (mode == PCI_PROBE_NORMAL) {
1703 		pci_bus_update_busn_res_end(bus, 255);
1704 		hose->last_busno = pci_scan_child_bus(bus);
1705 		pci_bus_update_busn_res_end(bus, hose->last_busno);
1706 	}
1707 
1708 	/* Platform gets a chance to do some global fixups before
1709 	 * we proceed to resource allocation
1710 	 */
1711 	if (ppc_md.pcibios_fixup_phb)
1712 		ppc_md.pcibios_fixup_phb(hose);
1713 
1714 	/* Configure PCI Express settings */
1715 	if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1716 		struct pci_bus *child;
1717 		list_for_each_entry(child, &bus->children, node)
1718 			pcie_bus_configure_settings(child);
1719 	}
1720 }
1721 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1722 
1723 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1724 {
1725 	int i, class = dev->class >> 8;
1726 	/* When configured as agent, programing interface = 1 */
1727 	int prog_if = dev->class & 0xf;
1728 
1729 	if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1730 	     class == PCI_CLASS_BRIDGE_OTHER) &&
1731 		(dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1732 		(prog_if == 0) &&
1733 		(dev->bus->parent == NULL)) {
1734 		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1735 			dev->resource[i].start = 0;
1736 			dev->resource[i].end = 0;
1737 			dev->resource[i].flags = 0;
1738 		}
1739 	}
1740 }
1741 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1742 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1743 
1744 static void fixup_vga(struct pci_dev *pdev)
1745 {
1746 	u16 cmd;
1747 
1748 	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1749 	if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1750 		vga_set_default_device(pdev);
1751 
1752 }
1753 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1754 			      PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);
1755