1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Contains common pci routines for ALL ppc platform 4 * (based on pci_32.c and pci_64.c) 5 * 6 * Port for PPC64 David Engebretsen, IBM Corp. 7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 8 * 9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 10 * Rework, based on alpha PCI code. 11 * 12 * Common pmac/prep/chrp pci routines. -- Cort 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/string.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/export.h> 21 #include <linux/of_address.h> 22 #include <linux/of_pci.h> 23 #include <linux/mm.h> 24 #include <linux/shmem_fs.h> 25 #include <linux/list.h> 26 #include <linux/syscalls.h> 27 #include <linux/irq.h> 28 #include <linux/vmalloc.h> 29 #include <linux/slab.h> 30 #include <linux/vgaarb.h> 31 #include <linux/numa.h> 32 33 #include <asm/processor.h> 34 #include <asm/io.h> 35 #include <asm/prom.h> 36 #include <asm/pci-bridge.h> 37 #include <asm/byteorder.h> 38 #include <asm/machdep.h> 39 #include <asm/ppc-pci.h> 40 #include <asm/eeh.h> 41 42 #include "../../../drivers/pci/pci.h" 43 44 /* hose_spinlock protects accesses to the the phb_bitmap. */ 45 static DEFINE_SPINLOCK(hose_spinlock); 46 LIST_HEAD(hose_list); 47 48 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */ 49 #define MAX_PHBS 0x10000 50 51 /* 52 * For dynamic PHB numbering: used/free PHBs tracking bitmap. 53 * Accesses to this bitmap should be protected by hose_spinlock. 54 */ 55 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS); 56 57 /* ISA Memory physical address */ 58 resource_size_t isa_mem_base; 59 EXPORT_SYMBOL(isa_mem_base); 60 61 62 static const struct dma_map_ops *pci_dma_ops; 63 64 void set_pci_dma_ops(const struct dma_map_ops *dma_ops) 65 { 66 pci_dma_ops = dma_ops; 67 } 68 69 /* 70 * This function should run under locking protection, specifically 71 * hose_spinlock. 72 */ 73 static int get_phb_number(struct device_node *dn) 74 { 75 int ret, phb_id = -1; 76 u32 prop_32; 77 u64 prop; 78 79 /* 80 * Try fixed PHB numbering first, by checking archs and reading 81 * the respective device-tree properties. Firstly, try powernv by 82 * reading "ibm,opal-phbid", only present in OPAL environment. 83 */ 84 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); 85 if (ret) { 86 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32); 87 prop = prop_32; 88 } 89 90 if (!ret) 91 phb_id = (int)(prop & (MAX_PHBS - 1)); 92 93 /* We need to be sure to not use the same PHB number twice. */ 94 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap)) 95 return phb_id; 96 97 /* 98 * If not pseries nor powernv, or if fixed PHB numbering tried to add 99 * the same PHB number twice, then fallback to dynamic PHB numbering. 100 */ 101 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS); 102 BUG_ON(phb_id >= MAX_PHBS); 103 set_bit(phb_id, phb_bitmap); 104 105 return phb_id; 106 } 107 108 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 109 { 110 struct pci_controller *phb; 111 112 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 113 if (phb == NULL) 114 return NULL; 115 spin_lock(&hose_spinlock); 116 phb->global_number = get_phb_number(dev); 117 list_add_tail(&phb->list_node, &hose_list); 118 spin_unlock(&hose_spinlock); 119 phb->dn = dev; 120 phb->is_dynamic = slab_is_available(); 121 #ifdef CONFIG_PPC64 122 if (dev) { 123 int nid = of_node_to_nid(dev); 124 125 if (nid < 0 || !node_online(nid)) 126 nid = NUMA_NO_NODE; 127 128 PHB_SET_NODE(phb, nid); 129 } 130 #endif 131 return phb; 132 } 133 EXPORT_SYMBOL_GPL(pcibios_alloc_controller); 134 135 void pcibios_free_controller(struct pci_controller *phb) 136 { 137 spin_lock(&hose_spinlock); 138 139 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ 140 if (phb->global_number < MAX_PHBS) 141 clear_bit(phb->global_number, phb_bitmap); 142 143 list_del(&phb->list_node); 144 spin_unlock(&hose_spinlock); 145 146 if (phb->is_dynamic) 147 kfree(phb); 148 } 149 EXPORT_SYMBOL_GPL(pcibios_free_controller); 150 151 /* 152 * This function is used to call pcibios_free_controller() 153 * in a deferred manner: a callback from the PCI subsystem. 154 * 155 * _*DO NOT*_ call pcibios_free_controller() explicitly if 156 * this is used (or it may access an invalid *phb pointer). 157 * 158 * The callback occurs when all references to the root bus 159 * are dropped (e.g., child buses/devices and their users). 160 * 161 * It's called as .release_fn() of 'struct pci_host_bridge' 162 * which is associated with the 'struct pci_controller.bus' 163 * (root bus) - it expects .release_data to hold a pointer 164 * to 'struct pci_controller'. 165 * 166 * In order to use it, register .release_fn()/release_data 167 * like this: 168 * 169 * pci_set_host_bridge_release(bridge, 170 * pcibios_free_controller_deferred 171 * (void *) phb); 172 * 173 * e.g. in the pcibios_root_bridge_prepare() callback from 174 * pci_create_root_bus(). 175 */ 176 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge) 177 { 178 struct pci_controller *phb = (struct pci_controller *) 179 bridge->release_data; 180 181 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); 182 183 pcibios_free_controller(phb); 184 } 185 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred); 186 187 /* 188 * The function is used to return the minimal alignment 189 * for memory or I/O windows of the associated P2P bridge. 190 * By default, 4KiB alignment for I/O windows and 1MiB for 191 * memory windows. 192 */ 193 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 194 unsigned long type) 195 { 196 struct pci_controller *phb = pci_bus_to_host(bus); 197 198 if (phb->controller_ops.window_alignment) 199 return phb->controller_ops.window_alignment(bus, type); 200 201 /* 202 * PCI core will figure out the default 203 * alignment: 4KiB for I/O and 1MiB for 204 * memory window. 205 */ 206 return 1; 207 } 208 209 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 210 { 211 struct pci_controller *hose = pci_bus_to_host(bus); 212 213 if (hose->controller_ops.setup_bridge) 214 hose->controller_ops.setup_bridge(bus, type); 215 } 216 217 void pcibios_reset_secondary_bus(struct pci_dev *dev) 218 { 219 struct pci_controller *phb = pci_bus_to_host(dev->bus); 220 221 if (phb->controller_ops.reset_secondary_bus) { 222 phb->controller_ops.reset_secondary_bus(dev); 223 return; 224 } 225 226 pci_reset_secondary_bus(dev); 227 } 228 229 resource_size_t pcibios_default_alignment(void) 230 { 231 if (ppc_md.pcibios_default_alignment) 232 return ppc_md.pcibios_default_alignment(); 233 234 return 0; 235 } 236 237 #ifdef CONFIG_PCI_IOV 238 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) 239 { 240 if (ppc_md.pcibios_iov_resource_alignment) 241 return ppc_md.pcibios_iov_resource_alignment(pdev, resno); 242 243 return pci_iov_resource_size(pdev, resno); 244 } 245 246 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 247 { 248 if (ppc_md.pcibios_sriov_enable) 249 return ppc_md.pcibios_sriov_enable(pdev, num_vfs); 250 251 return 0; 252 } 253 254 int pcibios_sriov_disable(struct pci_dev *pdev) 255 { 256 if (ppc_md.pcibios_sriov_disable) 257 return ppc_md.pcibios_sriov_disable(pdev); 258 259 return 0; 260 } 261 262 #endif /* CONFIG_PCI_IOV */ 263 264 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 265 { 266 #ifdef CONFIG_PPC64 267 return hose->pci_io_size; 268 #else 269 return resource_size(&hose->io_resource); 270 #endif 271 } 272 273 int pcibios_vaddr_is_ioport(void __iomem *address) 274 { 275 int ret = 0; 276 struct pci_controller *hose; 277 resource_size_t size; 278 279 spin_lock(&hose_spinlock); 280 list_for_each_entry(hose, &hose_list, list_node) { 281 size = pcibios_io_size(hose); 282 if (address >= hose->io_base_virt && 283 address < (hose->io_base_virt + size)) { 284 ret = 1; 285 break; 286 } 287 } 288 spin_unlock(&hose_spinlock); 289 return ret; 290 } 291 292 unsigned long pci_address_to_pio(phys_addr_t address) 293 { 294 struct pci_controller *hose; 295 resource_size_t size; 296 unsigned long ret = ~0; 297 298 spin_lock(&hose_spinlock); 299 list_for_each_entry(hose, &hose_list, list_node) { 300 size = pcibios_io_size(hose); 301 if (address >= hose->io_base_phys && 302 address < (hose->io_base_phys + size)) { 303 unsigned long base = 304 (unsigned long)hose->io_base_virt - _IO_BASE; 305 ret = base + (address - hose->io_base_phys); 306 break; 307 } 308 } 309 spin_unlock(&hose_spinlock); 310 311 return ret; 312 } 313 EXPORT_SYMBOL_GPL(pci_address_to_pio); 314 315 /* 316 * Return the domain number for this bus. 317 */ 318 int pci_domain_nr(struct pci_bus *bus) 319 { 320 struct pci_controller *hose = pci_bus_to_host(bus); 321 322 return hose->global_number; 323 } 324 EXPORT_SYMBOL(pci_domain_nr); 325 326 /* This routine is meant to be used early during boot, when the 327 * PCI bus numbers have not yet been assigned, and you need to 328 * issue PCI config cycles to an OF device. 329 * It could also be used to "fix" RTAS config cycles if you want 330 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 331 * config cycles. 332 */ 333 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 334 { 335 while(node) { 336 struct pci_controller *hose, *tmp; 337 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 338 if (hose->dn == node) 339 return hose; 340 node = node->parent; 341 } 342 return NULL; 343 } 344 345 struct pci_controller *pci_find_controller_for_domain(int domain_nr) 346 { 347 struct pci_controller *hose; 348 349 list_for_each_entry(hose, &hose_list, list_node) 350 if (hose->global_number == domain_nr) 351 return hose; 352 353 return NULL; 354 } 355 356 /* 357 * Reads the interrupt pin to determine if interrupt is use by card. 358 * If the interrupt is used, then gets the interrupt line from the 359 * openfirmware and sets it in the pci_dev and pci_config line. 360 */ 361 static int pci_read_irq_line(struct pci_dev *pci_dev) 362 { 363 int virq; 364 365 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 366 367 /* Try to get a mapping from the device-tree */ 368 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0); 369 if (virq <= 0) { 370 u8 line, pin; 371 372 /* If that fails, lets fallback to what is in the config 373 * space and map that through the default controller. We 374 * also set the type to level low since that's what PCI 375 * interrupts are. If your platform does differently, then 376 * either provide a proper interrupt tree or don't use this 377 * function. 378 */ 379 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 380 return -1; 381 if (pin == 0) 382 return -1; 383 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 384 line == 0xff || line == 0) { 385 return -1; 386 } 387 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 388 line, pin); 389 390 virq = irq_create_mapping(NULL, line); 391 if (virq) 392 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 393 } 394 395 if (!virq) { 396 pr_debug(" Failed to map !\n"); 397 return -1; 398 } 399 400 pr_debug(" Mapped to linux irq %d\n", virq); 401 402 pci_dev->irq = virq; 403 404 return 0; 405 } 406 407 /* 408 * Platform support for /proc/bus/pci/X/Y mmap()s. 409 * -- paulus. 410 */ 411 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) 412 { 413 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 414 resource_size_t ioaddr = pci_resource_start(pdev, bar); 415 416 if (!hose) 417 return -EINVAL; 418 419 /* Convert to an offset within this PCI controller */ 420 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; 421 422 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; 423 return 0; 424 } 425 426 /* 427 * This one is used by /dev/mem and fbdev who have no clue about the 428 * PCI device, it tries to find the PCI device first and calls the 429 * above routine 430 */ 431 pgprot_t pci_phys_mem_access_prot(struct file *file, 432 unsigned long pfn, 433 unsigned long size, 434 pgprot_t prot) 435 { 436 struct pci_dev *pdev = NULL; 437 struct resource *found = NULL; 438 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 439 int i; 440 441 if (page_is_ram(pfn)) 442 return prot; 443 444 prot = pgprot_noncached(prot); 445 for_each_pci_dev(pdev) { 446 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 447 struct resource *rp = &pdev->resource[i]; 448 int flags = rp->flags; 449 450 /* Active and same type? */ 451 if ((flags & IORESOURCE_MEM) == 0) 452 continue; 453 /* In the range of this resource? */ 454 if (offset < (rp->start & PAGE_MASK) || 455 offset > rp->end) 456 continue; 457 found = rp; 458 break; 459 } 460 if (found) 461 break; 462 } 463 if (found) { 464 if (found->flags & IORESOURCE_PREFETCH) 465 prot = pgprot_noncached_wc(prot); 466 pci_dev_put(pdev); 467 } 468 469 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 470 (unsigned long long)offset, pgprot_val(prot)); 471 472 return prot; 473 } 474 475 /* This provides legacy IO read access on a bus */ 476 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 477 { 478 unsigned long offset; 479 struct pci_controller *hose = pci_bus_to_host(bus); 480 struct resource *rp = &hose->io_resource; 481 void __iomem *addr; 482 483 /* Check if port can be supported by that bus. We only check 484 * the ranges of the PHB though, not the bus itself as the rules 485 * for forwarding legacy cycles down bridges are not our problem 486 * here. So if the host bridge supports it, we do it. 487 */ 488 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 489 offset += port; 490 491 if (!(rp->flags & IORESOURCE_IO)) 492 return -ENXIO; 493 if (offset < rp->start || (offset + size) > rp->end) 494 return -ENXIO; 495 addr = hose->io_base_virt + port; 496 497 switch(size) { 498 case 1: 499 *((u8 *)val) = in_8(addr); 500 return 1; 501 case 2: 502 if (port & 1) 503 return -EINVAL; 504 *((u16 *)val) = in_le16(addr); 505 return 2; 506 case 4: 507 if (port & 3) 508 return -EINVAL; 509 *((u32 *)val) = in_le32(addr); 510 return 4; 511 } 512 return -EINVAL; 513 } 514 515 /* This provides legacy IO write access on a bus */ 516 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 517 { 518 unsigned long offset; 519 struct pci_controller *hose = pci_bus_to_host(bus); 520 struct resource *rp = &hose->io_resource; 521 void __iomem *addr; 522 523 /* Check if port can be supported by that bus. We only check 524 * the ranges of the PHB though, not the bus itself as the rules 525 * for forwarding legacy cycles down bridges are not our problem 526 * here. So if the host bridge supports it, we do it. 527 */ 528 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 529 offset += port; 530 531 if (!(rp->flags & IORESOURCE_IO)) 532 return -ENXIO; 533 if (offset < rp->start || (offset + size) > rp->end) 534 return -ENXIO; 535 addr = hose->io_base_virt + port; 536 537 /* WARNING: The generic code is idiotic. It gets passed a pointer 538 * to what can be a 1, 2 or 4 byte quantity and always reads that 539 * as a u32, which means that we have to correct the location of 540 * the data read within those 32 bits for size 1 and 2 541 */ 542 switch(size) { 543 case 1: 544 out_8(addr, val >> 24); 545 return 1; 546 case 2: 547 if (port & 1) 548 return -EINVAL; 549 out_le16(addr, val >> 16); 550 return 2; 551 case 4: 552 if (port & 3) 553 return -EINVAL; 554 out_le32(addr, val); 555 return 4; 556 } 557 return -EINVAL; 558 } 559 560 /* This provides legacy IO or memory mmap access on a bus */ 561 int pci_mmap_legacy_page_range(struct pci_bus *bus, 562 struct vm_area_struct *vma, 563 enum pci_mmap_state mmap_state) 564 { 565 struct pci_controller *hose = pci_bus_to_host(bus); 566 resource_size_t offset = 567 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 568 resource_size_t size = vma->vm_end - vma->vm_start; 569 struct resource *rp; 570 571 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 572 pci_domain_nr(bus), bus->number, 573 mmap_state == pci_mmap_mem ? "MEM" : "IO", 574 (unsigned long long)offset, 575 (unsigned long long)(offset + size - 1)); 576 577 if (mmap_state == pci_mmap_mem) { 578 /* Hack alert ! 579 * 580 * Because X is lame and can fail starting if it gets an error trying 581 * to mmap legacy_mem (instead of just moving on without legacy memory 582 * access) we fake it here by giving it anonymous memory, effectively 583 * behaving just like /dev/zero 584 */ 585 if ((offset + size) > hose->isa_mem_size) { 586 printk(KERN_DEBUG 587 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 588 current->comm, current->pid, pci_domain_nr(bus), bus->number); 589 if (vma->vm_flags & VM_SHARED) 590 return shmem_zero_setup(vma); 591 return 0; 592 } 593 offset += hose->isa_mem_phys; 594 } else { 595 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 596 unsigned long roffset = offset + io_offset; 597 rp = &hose->io_resource; 598 if (!(rp->flags & IORESOURCE_IO)) 599 return -ENXIO; 600 if (roffset < rp->start || (roffset + size) > rp->end) 601 return -ENXIO; 602 offset += hose->io_base_phys; 603 } 604 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 605 606 vma->vm_pgoff = offset >> PAGE_SHIFT; 607 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 608 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 609 vma->vm_end - vma->vm_start, 610 vma->vm_page_prot); 611 } 612 613 void pci_resource_to_user(const struct pci_dev *dev, int bar, 614 const struct resource *rsrc, 615 resource_size_t *start, resource_size_t *end) 616 { 617 struct pci_bus_region region; 618 619 if (rsrc->flags & IORESOURCE_IO) { 620 pcibios_resource_to_bus(dev->bus, ®ion, 621 (struct resource *) rsrc); 622 *start = region.start; 623 *end = region.end; 624 return; 625 } 626 627 /* We pass a CPU physical address to userland for MMIO instead of a 628 * BAR value because X is lame and expects to be able to use that 629 * to pass to /dev/mem! 630 * 631 * That means we may have 64-bit values where some apps only expect 632 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). 633 */ 634 *start = rsrc->start; 635 *end = rsrc->end; 636 } 637 638 /** 639 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 640 * @hose: newly allocated pci_controller to be setup 641 * @dev: device node of the host bridge 642 * @primary: set if primary bus (32 bits only, soon to be deprecated) 643 * 644 * This function will parse the "ranges" property of a PCI host bridge device 645 * node and setup the resource mapping of a pci controller based on its 646 * content. 647 * 648 * Life would be boring if it wasn't for a few issues that we have to deal 649 * with here: 650 * 651 * - We can only cope with one IO space range and up to 3 Memory space 652 * ranges. However, some machines (thanks Apple !) tend to split their 653 * space into lots of small contiguous ranges. So we have to coalesce. 654 * 655 * - Some busses have IO space not starting at 0, which causes trouble with 656 * the way we do our IO resource renumbering. The code somewhat deals with 657 * it for 64 bits but I would expect problems on 32 bits. 658 * 659 * - Some 32 bits platforms such as 4xx can have physical space larger than 660 * 32 bits so we need to use 64 bits values for the parsing 661 */ 662 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 663 struct device_node *dev, int primary) 664 { 665 int memno = 0; 666 struct resource *res; 667 struct of_pci_range range; 668 struct of_pci_range_parser parser; 669 670 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n", 671 dev, primary ? "(primary)" : ""); 672 673 /* Check for ranges property */ 674 if (of_pci_range_parser_init(&parser, dev)) 675 return; 676 677 /* Parse it */ 678 for_each_of_pci_range(&parser, &range) { 679 /* If we failed translation or got a zero-sized region 680 * (some FW try to feed us with non sensical zero sized regions 681 * such as power3 which look like some kind of attempt at exposing 682 * the VGA memory hole) 683 */ 684 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 685 continue; 686 687 /* Act based on address space type */ 688 res = NULL; 689 switch (range.flags & IORESOURCE_TYPE_BITS) { 690 case IORESOURCE_IO: 691 printk(KERN_INFO 692 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 693 range.cpu_addr, range.cpu_addr + range.size - 1, 694 range.pci_addr); 695 696 /* We support only one IO range */ 697 if (hose->pci_io_size) { 698 printk(KERN_INFO 699 " \\--> Skipped (too many) !\n"); 700 continue; 701 } 702 #ifdef CONFIG_PPC32 703 /* On 32 bits, limit I/O space to 16MB */ 704 if (range.size > 0x01000000) 705 range.size = 0x01000000; 706 707 /* 32 bits needs to map IOs here */ 708 hose->io_base_virt = ioremap(range.cpu_addr, 709 range.size); 710 711 /* Expect trouble if pci_addr is not 0 */ 712 if (primary) 713 isa_io_base = 714 (unsigned long)hose->io_base_virt; 715 #endif /* CONFIG_PPC32 */ 716 /* pci_io_size and io_base_phys always represent IO 717 * space starting at 0 so we factor in pci_addr 718 */ 719 hose->pci_io_size = range.pci_addr + range.size; 720 hose->io_base_phys = range.cpu_addr - range.pci_addr; 721 722 /* Build resource */ 723 res = &hose->io_resource; 724 range.cpu_addr = range.pci_addr; 725 break; 726 case IORESOURCE_MEM: 727 printk(KERN_INFO 728 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 729 range.cpu_addr, range.cpu_addr + range.size - 1, 730 range.pci_addr, 731 (range.pci_space & 0x40000000) ? 732 "Prefetch" : ""); 733 734 /* We support only 3 memory ranges */ 735 if (memno >= 3) { 736 printk(KERN_INFO 737 " \\--> Skipped (too many) !\n"); 738 continue; 739 } 740 /* Handles ISA memory hole space here */ 741 if (range.pci_addr == 0) { 742 if (primary || isa_mem_base == 0) 743 isa_mem_base = range.cpu_addr; 744 hose->isa_mem_phys = range.cpu_addr; 745 hose->isa_mem_size = range.size; 746 } 747 748 /* Build resource */ 749 hose->mem_offset[memno] = range.cpu_addr - 750 range.pci_addr; 751 res = &hose->mem_resources[memno++]; 752 break; 753 } 754 if (res != NULL) { 755 res->name = dev->full_name; 756 res->flags = range.flags; 757 res->start = range.cpu_addr; 758 res->end = range.cpu_addr + range.size - 1; 759 res->parent = res->child = res->sibling = NULL; 760 } 761 } 762 } 763 764 /* Decide whether to display the domain number in /proc */ 765 int pci_proc_domain(struct pci_bus *bus) 766 { 767 struct pci_controller *hose = pci_bus_to_host(bus); 768 769 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 770 return 0; 771 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 772 return hose->global_number != 0; 773 return 1; 774 } 775 776 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 777 { 778 if (ppc_md.pcibios_root_bridge_prepare) 779 return ppc_md.pcibios_root_bridge_prepare(bridge); 780 781 return 0; 782 } 783 784 /* This header fixup will do the resource fixup for all devices as they are 785 * probed, but not for bridge ranges 786 */ 787 static void pcibios_fixup_resources(struct pci_dev *dev) 788 { 789 struct pci_controller *hose = pci_bus_to_host(dev->bus); 790 int i; 791 792 if (!hose) { 793 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 794 pci_name(dev)); 795 return; 796 } 797 798 if (dev->is_virtfn) 799 return; 800 801 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 802 struct resource *res = dev->resource + i; 803 struct pci_bus_region reg; 804 if (!res->flags) 805 continue; 806 807 /* If we're going to re-assign everything, we mark all resources 808 * as unset (and 0-base them). In addition, we mark BARs starting 809 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 810 * since in that case, we don't want to re-assign anything 811 */ 812 pcibios_resource_to_bus(dev->bus, ®, res); 813 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 814 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 815 /* Only print message if not re-assigning */ 816 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 817 pr_debug("PCI:%s Resource %d %pR is unassigned\n", 818 pci_name(dev), i, res); 819 res->end -= res->start; 820 res->start = 0; 821 res->flags |= IORESOURCE_UNSET; 822 continue; 823 } 824 825 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); 826 } 827 828 /* Call machine specific resource fixup */ 829 if (ppc_md.pcibios_fixup_resources) 830 ppc_md.pcibios_fixup_resources(dev); 831 } 832 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 833 834 /* This function tries to figure out if a bridge resource has been initialized 835 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 836 * things go more smoothly when it gets it right. It should covers cases such 837 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 838 */ 839 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 840 struct resource *res) 841 { 842 struct pci_controller *hose = pci_bus_to_host(bus); 843 struct pci_dev *dev = bus->self; 844 resource_size_t offset; 845 struct pci_bus_region region; 846 u16 command; 847 int i; 848 849 /* We don't do anything if PCI_PROBE_ONLY is set */ 850 if (pci_has_flag(PCI_PROBE_ONLY)) 851 return 0; 852 853 /* Job is a bit different between memory and IO */ 854 if (res->flags & IORESOURCE_MEM) { 855 pcibios_resource_to_bus(dev->bus, ®ion, res); 856 857 /* If the BAR is non-0 then it's probably been initialized */ 858 if (region.start != 0) 859 return 0; 860 861 /* The BAR is 0, let's check if memory decoding is enabled on 862 * the bridge. If not, we consider it unassigned 863 */ 864 pci_read_config_word(dev, PCI_COMMAND, &command); 865 if ((command & PCI_COMMAND_MEMORY) == 0) 866 return 1; 867 868 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 869 * resources covers that starting address (0 then it's good enough for 870 * us for memory space) 871 */ 872 for (i = 0; i < 3; i++) { 873 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 874 hose->mem_resources[i].start == hose->mem_offset[i]) 875 return 0; 876 } 877 878 /* Well, it starts at 0 and we know it will collide so we may as 879 * well consider it as unassigned. That covers the Apple case. 880 */ 881 return 1; 882 } else { 883 /* If the BAR is non-0, then we consider it assigned */ 884 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 885 if (((res->start - offset) & 0xfffffffful) != 0) 886 return 0; 887 888 /* Here, we are a bit different than memory as typically IO space 889 * starting at low addresses -is- valid. What we do instead if that 890 * we consider as unassigned anything that doesn't have IO enabled 891 * in the PCI command register, and that's it. 892 */ 893 pci_read_config_word(dev, PCI_COMMAND, &command); 894 if (command & PCI_COMMAND_IO) 895 return 0; 896 897 /* It's starting at 0 and IO is disabled in the bridge, consider 898 * it unassigned 899 */ 900 return 1; 901 } 902 } 903 904 /* Fixup resources of a PCI<->PCI bridge */ 905 static void pcibios_fixup_bridge(struct pci_bus *bus) 906 { 907 struct resource *res; 908 int i; 909 910 struct pci_dev *dev = bus->self; 911 912 pci_bus_for_each_resource(bus, res, i) { 913 if (!res || !res->flags) 914 continue; 915 if (i >= 3 && bus->self->transparent) 916 continue; 917 918 /* If we're going to reassign everything, we can 919 * shrink the P2P resource to have size as being 920 * of 0 in order to save space. 921 */ 922 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 923 res->flags |= IORESOURCE_UNSET; 924 res->start = 0; 925 res->end = -1; 926 continue; 927 } 928 929 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); 930 931 /* Try to detect uninitialized P2P bridge resources, 932 * and clear them out so they get re-assigned later 933 */ 934 if (pcibios_uninitialized_bridge_resource(bus, res)) { 935 res->flags = 0; 936 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 937 } 938 } 939 } 940 941 void pcibios_setup_bus_self(struct pci_bus *bus) 942 { 943 struct pci_controller *phb; 944 945 /* Fix up the bus resources for P2P bridges */ 946 if (bus->self != NULL) 947 pcibios_fixup_bridge(bus); 948 949 /* Platform specific bus fixups. This is currently only used 950 * by fsl_pci and I'm hoping to get rid of it at some point 951 */ 952 if (ppc_md.pcibios_fixup_bus) 953 ppc_md.pcibios_fixup_bus(bus); 954 955 /* Setup bus DMA mappings */ 956 phb = pci_bus_to_host(bus); 957 if (phb->controller_ops.dma_bus_setup) 958 phb->controller_ops.dma_bus_setup(bus); 959 } 960 961 static void pcibios_setup_device(struct pci_dev *dev) 962 { 963 struct pci_controller *phb; 964 /* Fixup NUMA node as it may not be setup yet by the generic 965 * code and is needed by the DMA init 966 */ 967 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 968 969 /* Hook up default DMA ops */ 970 set_dma_ops(&dev->dev, pci_dma_ops); 971 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; 972 973 /* Additional platform DMA/iommu setup */ 974 phb = pci_bus_to_host(dev->bus); 975 if (phb->controller_ops.dma_dev_setup) 976 phb->controller_ops.dma_dev_setup(dev); 977 978 /* Read default IRQs and fixup if necessary */ 979 pci_read_irq_line(dev); 980 if (ppc_md.pci_irq_fixup) 981 ppc_md.pci_irq_fixup(dev); 982 } 983 984 void pcibios_bus_add_device(struct pci_dev *pdev) 985 { 986 /* Perform platform-specific device setup */ 987 pcibios_setup_device(pdev); 988 989 if (ppc_md.pcibios_bus_add_device) 990 ppc_md.pcibios_bus_add_device(pdev); 991 } 992 993 int pcibios_add_device(struct pci_dev *dev) 994 { 995 #ifdef CONFIG_PCI_IOV 996 if (ppc_md.pcibios_fixup_sriov) 997 ppc_md.pcibios_fixup_sriov(dev); 998 #endif /* CONFIG_PCI_IOV */ 999 1000 return 0; 1001 } 1002 1003 void pcibios_setup_bus_devices(struct pci_bus *bus) 1004 { 1005 struct pci_dev *dev; 1006 1007 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1008 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1009 1010 list_for_each_entry(dev, &bus->devices, bus_list) { 1011 /* Cardbus can call us to add new devices to a bus, so ignore 1012 * those who are already fully discovered 1013 */ 1014 if (pci_dev_is_added(dev)) 1015 continue; 1016 1017 pcibios_setup_device(dev); 1018 } 1019 } 1020 1021 void pcibios_set_master(struct pci_dev *dev) 1022 { 1023 /* No special bus mastering setup handling */ 1024 } 1025 1026 void pcibios_fixup_bus(struct pci_bus *bus) 1027 { 1028 /* When called from the generic PCI probe, read PCI<->PCI bridge 1029 * bases. This is -not- called when generating the PCI tree from 1030 * the OF device-tree. 1031 */ 1032 pci_read_bridge_bases(bus); 1033 1034 /* Now fixup the bus bus */ 1035 pcibios_setup_bus_self(bus); 1036 } 1037 EXPORT_SYMBOL(pcibios_fixup_bus); 1038 1039 void pci_fixup_cardbus(struct pci_bus *bus) 1040 { 1041 /* Now fixup devices on that bus */ 1042 pcibios_setup_bus_devices(bus); 1043 } 1044 1045 1046 static int skip_isa_ioresource_align(struct pci_dev *dev) 1047 { 1048 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1049 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1050 return 1; 1051 return 0; 1052 } 1053 1054 /* 1055 * We need to avoid collisions with `mirrored' VGA ports 1056 * and other strange ISA hardware, so we always want the 1057 * addresses to be allocated in the 0x000-0x0ff region 1058 * modulo 0x400. 1059 * 1060 * Why? Because some silly external IO cards only decode 1061 * the low 10 bits of the IO address. The 0x00-0xff region 1062 * is reserved for motherboard devices that decode all 16 1063 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1064 * but we want to try to avoid allocating at 0x2900-0x2bff 1065 * which might have be mirrored at 0x0100-0x03ff.. 1066 */ 1067 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1068 resource_size_t size, resource_size_t align) 1069 { 1070 struct pci_dev *dev = data; 1071 resource_size_t start = res->start; 1072 1073 if (res->flags & IORESOURCE_IO) { 1074 if (skip_isa_ioresource_align(dev)) 1075 return start; 1076 if (start & 0x300) 1077 start = (start + 0x3ff) & ~0x3ff; 1078 } 1079 1080 return start; 1081 } 1082 EXPORT_SYMBOL(pcibios_align_resource); 1083 1084 /* 1085 * Reparent resource children of pr that conflict with res 1086 * under res, and make res replace those children. 1087 */ 1088 static int reparent_resources(struct resource *parent, 1089 struct resource *res) 1090 { 1091 struct resource *p, **pp; 1092 struct resource **firstpp = NULL; 1093 1094 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1095 if (p->end < res->start) 1096 continue; 1097 if (res->end < p->start) 1098 break; 1099 if (p->start < res->start || p->end > res->end) 1100 return -1; /* not completely contained */ 1101 if (firstpp == NULL) 1102 firstpp = pp; 1103 } 1104 if (firstpp == NULL) 1105 return -1; /* didn't find any conflicting entries? */ 1106 res->parent = parent; 1107 res->child = *firstpp; 1108 res->sibling = *pp; 1109 *firstpp = res; 1110 *pp = NULL; 1111 for (p = res->child; p != NULL; p = p->sibling) { 1112 p->parent = res; 1113 pr_debug("PCI: Reparented %s %pR under %s\n", 1114 p->name, p, res->name); 1115 } 1116 return 0; 1117 } 1118 1119 /* 1120 * Handle resources of PCI devices. If the world were perfect, we could 1121 * just allocate all the resource regions and do nothing more. It isn't. 1122 * On the other hand, we cannot just re-allocate all devices, as it would 1123 * require us to know lots of host bridge internals. So we attempt to 1124 * keep as much of the original configuration as possible, but tweak it 1125 * when it's found to be wrong. 1126 * 1127 * Known BIOS problems we have to work around: 1128 * - I/O or memory regions not configured 1129 * - regions configured, but not enabled in the command register 1130 * - bogus I/O addresses above 64K used 1131 * - expansion ROMs left enabled (this may sound harmless, but given 1132 * the fact the PCI specs explicitly allow address decoders to be 1133 * shared between expansion ROMs and other resource regions, it's 1134 * at least dangerous) 1135 * 1136 * Our solution: 1137 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1138 * This gives us fixed barriers on where we can allocate. 1139 * (2) Allocate resources for all enabled devices. If there is 1140 * a collision, just mark the resource as unallocated. Also 1141 * disable expansion ROMs during this step. 1142 * (3) Try to allocate resources for disabled devices. If the 1143 * resources were assigned correctly, everything goes well, 1144 * if they weren't, they won't disturb allocation of other 1145 * resources. 1146 * (4) Assign new addresses to resources which were either 1147 * not configured at all or misconfigured. If explicitly 1148 * requested by the user, configure expansion ROM address 1149 * as well. 1150 */ 1151 1152 static void pcibios_allocate_bus_resources(struct pci_bus *bus) 1153 { 1154 struct pci_bus *b; 1155 int i; 1156 struct resource *res, *pr; 1157 1158 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1159 pci_domain_nr(bus), bus->number); 1160 1161 pci_bus_for_each_resource(bus, res, i) { 1162 if (!res || !res->flags || res->start > res->end || res->parent) 1163 continue; 1164 1165 /* If the resource was left unset at this point, we clear it */ 1166 if (res->flags & IORESOURCE_UNSET) 1167 goto clear_resource; 1168 1169 if (bus->parent == NULL) 1170 pr = (res->flags & IORESOURCE_IO) ? 1171 &ioport_resource : &iomem_resource; 1172 else { 1173 pr = pci_find_parent_resource(bus->self, res); 1174 if (pr == res) { 1175 /* this happens when the generic PCI 1176 * code (wrongly) decides that this 1177 * bridge is transparent -- paulus 1178 */ 1179 continue; 1180 } 1181 } 1182 1183 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", 1184 bus->self ? pci_name(bus->self) : "PHB", bus->number, 1185 i, res, pr, (pr && pr->name) ? pr->name : "nil"); 1186 1187 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1188 struct pci_dev *dev = bus->self; 1189 1190 if (request_resource(pr, res) == 0) 1191 continue; 1192 /* 1193 * Must be a conflict with an existing entry. 1194 * Move that entry (or entries) under the 1195 * bridge resource and try again. 1196 */ 1197 if (reparent_resources(pr, res) == 0) 1198 continue; 1199 1200 if (dev && i < PCI_BRIDGE_RESOURCE_NUM && 1201 pci_claim_bridge_resource(dev, 1202 i + PCI_BRIDGE_RESOURCES) == 0) 1203 continue; 1204 } 1205 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n", 1206 i, bus->number); 1207 clear_resource: 1208 /* The resource might be figured out when doing 1209 * reassignment based on the resources required 1210 * by the downstream PCI devices. Here we set 1211 * the size of the resource to be 0 in order to 1212 * save more space. 1213 */ 1214 res->start = 0; 1215 res->end = -1; 1216 res->flags = 0; 1217 } 1218 1219 list_for_each_entry(b, &bus->children, node) 1220 pcibios_allocate_bus_resources(b); 1221 } 1222 1223 static inline void alloc_resource(struct pci_dev *dev, int idx) 1224 { 1225 struct resource *pr, *r = &dev->resource[idx]; 1226 1227 pr_debug("PCI: Allocating %s: Resource %d: %pR\n", 1228 pci_name(dev), idx, r); 1229 1230 pr = pci_find_parent_resource(dev, r); 1231 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1232 request_resource(pr, r) < 0) { 1233 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1234 " of device %s, will remap\n", idx, pci_name(dev)); 1235 if (pr) 1236 pr_debug("PCI: parent is %p: %pR\n", pr, pr); 1237 /* We'll assign a new address later */ 1238 r->flags |= IORESOURCE_UNSET; 1239 r->end -= r->start; 1240 r->start = 0; 1241 } 1242 } 1243 1244 static void __init pcibios_allocate_resources(int pass) 1245 { 1246 struct pci_dev *dev = NULL; 1247 int idx, disabled; 1248 u16 command; 1249 struct resource *r; 1250 1251 for_each_pci_dev(dev) { 1252 pci_read_config_word(dev, PCI_COMMAND, &command); 1253 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1254 r = &dev->resource[idx]; 1255 if (r->parent) /* Already allocated */ 1256 continue; 1257 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1258 continue; /* Not assigned at all */ 1259 /* We only allocate ROMs on pass 1 just in case they 1260 * have been screwed up by firmware 1261 */ 1262 if (idx == PCI_ROM_RESOURCE ) 1263 disabled = 1; 1264 if (r->flags & IORESOURCE_IO) 1265 disabled = !(command & PCI_COMMAND_IO); 1266 else 1267 disabled = !(command & PCI_COMMAND_MEMORY); 1268 if (pass == disabled) 1269 alloc_resource(dev, idx); 1270 } 1271 if (pass) 1272 continue; 1273 r = &dev->resource[PCI_ROM_RESOURCE]; 1274 if (r->flags) { 1275 /* Turn the ROM off, leave the resource region, 1276 * but keep it unregistered. 1277 */ 1278 u32 reg; 1279 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1280 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1281 pr_debug("PCI: Switching off ROM of %s\n", 1282 pci_name(dev)); 1283 r->flags &= ~IORESOURCE_ROM_ENABLE; 1284 pci_write_config_dword(dev, dev->rom_base_reg, 1285 reg & ~PCI_ROM_ADDRESS_ENABLE); 1286 } 1287 } 1288 } 1289 } 1290 1291 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1292 { 1293 struct pci_controller *hose = pci_bus_to_host(bus); 1294 resource_size_t offset; 1295 struct resource *res, *pres; 1296 int i; 1297 1298 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1299 1300 /* Check for IO */ 1301 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1302 goto no_io; 1303 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1304 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1305 BUG_ON(res == NULL); 1306 res->name = "Legacy IO"; 1307 res->flags = IORESOURCE_IO; 1308 res->start = offset; 1309 res->end = (offset + 0xfff) & 0xfffffffful; 1310 pr_debug("Candidate legacy IO: %pR\n", res); 1311 if (request_resource(&hose->io_resource, res)) { 1312 printk(KERN_DEBUG 1313 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1314 pci_domain_nr(bus), bus->number, res); 1315 kfree(res); 1316 } 1317 1318 no_io: 1319 /* Check for memory */ 1320 for (i = 0; i < 3; i++) { 1321 pres = &hose->mem_resources[i]; 1322 offset = hose->mem_offset[i]; 1323 if (!(pres->flags & IORESOURCE_MEM)) 1324 continue; 1325 pr_debug("hose mem res: %pR\n", pres); 1326 if ((pres->start - offset) <= 0xa0000 && 1327 (pres->end - offset) >= 0xbffff) 1328 break; 1329 } 1330 if (i >= 3) 1331 return; 1332 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1333 BUG_ON(res == NULL); 1334 res->name = "Legacy VGA memory"; 1335 res->flags = IORESOURCE_MEM; 1336 res->start = 0xa0000 + offset; 1337 res->end = 0xbffff + offset; 1338 pr_debug("Candidate VGA memory: %pR\n", res); 1339 if (request_resource(pres, res)) { 1340 printk(KERN_DEBUG 1341 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1342 pci_domain_nr(bus), bus->number, res); 1343 kfree(res); 1344 } 1345 } 1346 1347 void __init pcibios_resource_survey(void) 1348 { 1349 struct pci_bus *b; 1350 1351 /* Allocate and assign resources */ 1352 list_for_each_entry(b, &pci_root_buses, node) 1353 pcibios_allocate_bus_resources(b); 1354 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1355 pcibios_allocate_resources(0); 1356 pcibios_allocate_resources(1); 1357 } 1358 1359 /* Before we start assigning unassigned resource, we try to reserve 1360 * the low IO area and the VGA memory area if they intersect the 1361 * bus available resources to avoid allocating things on top of them 1362 */ 1363 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1364 list_for_each_entry(b, &pci_root_buses, node) 1365 pcibios_reserve_legacy_regions(b); 1366 } 1367 1368 /* Now, if the platform didn't decide to blindly trust the firmware, 1369 * we proceed to assigning things that were left unassigned 1370 */ 1371 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1372 pr_debug("PCI: Assigning unassigned resources...\n"); 1373 pci_assign_unassigned_resources(); 1374 } 1375 } 1376 1377 /* This is used by the PCI hotplug driver to allocate resource 1378 * of newly plugged busses. We can try to consolidate with the 1379 * rest of the code later, for now, keep it as-is as our main 1380 * resource allocation function doesn't deal with sub-trees yet. 1381 */ 1382 void pcibios_claim_one_bus(struct pci_bus *bus) 1383 { 1384 struct pci_dev *dev; 1385 struct pci_bus *child_bus; 1386 1387 list_for_each_entry(dev, &bus->devices, bus_list) { 1388 int i; 1389 1390 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1391 struct resource *r = &dev->resource[i]; 1392 1393 if (r->parent || !r->start || !r->flags) 1394 continue; 1395 1396 pr_debug("PCI: Claiming %s: Resource %d: %pR\n", 1397 pci_name(dev), i, r); 1398 1399 if (pci_claim_resource(dev, i) == 0) 1400 continue; 1401 1402 pci_claim_bridge_resource(dev, i); 1403 } 1404 } 1405 1406 list_for_each_entry(child_bus, &bus->children, node) 1407 pcibios_claim_one_bus(child_bus); 1408 } 1409 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1410 1411 1412 /* pcibios_finish_adding_to_bus 1413 * 1414 * This is to be called by the hotplug code after devices have been 1415 * added to a bus, this include calling it for a PHB that is just 1416 * being added 1417 */ 1418 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1419 { 1420 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1421 pci_domain_nr(bus), bus->number); 1422 1423 /* Allocate bus and devices resources */ 1424 pcibios_allocate_bus_resources(bus); 1425 pcibios_claim_one_bus(bus); 1426 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1427 if (bus->self) 1428 pci_assign_unassigned_bridge_resources(bus->self); 1429 else 1430 pci_assign_unassigned_bus_resources(bus); 1431 } 1432 1433 /* Fixup EEH */ 1434 eeh_add_device_tree_late(bus); 1435 1436 /* Add new devices to global lists. Register in proc, sysfs. */ 1437 pci_bus_add_devices(bus); 1438 1439 /* sysfs files should only be added after devices are added */ 1440 eeh_add_sysfs_files(bus); 1441 } 1442 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1443 1444 int pcibios_enable_device(struct pci_dev *dev, int mask) 1445 { 1446 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1447 1448 if (phb->controller_ops.enable_device_hook) 1449 if (!phb->controller_ops.enable_device_hook(dev)) 1450 return -EINVAL; 1451 1452 return pci_enable_resources(dev, mask); 1453 } 1454 1455 void pcibios_disable_device(struct pci_dev *dev) 1456 { 1457 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1458 1459 if (phb->controller_ops.disable_device) 1460 phb->controller_ops.disable_device(dev); 1461 } 1462 1463 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1464 { 1465 return (unsigned long) hose->io_base_virt - _IO_BASE; 1466 } 1467 1468 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1469 struct list_head *resources) 1470 { 1471 struct resource *res; 1472 resource_size_t offset; 1473 int i; 1474 1475 /* Hookup PHB IO resource */ 1476 res = &hose->io_resource; 1477 1478 if (!res->flags) { 1479 pr_debug("PCI: I/O resource not set for host" 1480 " bridge %pOF (domain %d)\n", 1481 hose->dn, hose->global_number); 1482 } else { 1483 offset = pcibios_io_space_offset(hose); 1484 1485 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", 1486 res, (unsigned long long)offset); 1487 pci_add_resource_offset(resources, res, offset); 1488 } 1489 1490 /* Hookup PHB Memory resources */ 1491 for (i = 0; i < 3; ++i) { 1492 res = &hose->mem_resources[i]; 1493 if (!res->flags) 1494 continue; 1495 1496 offset = hose->mem_offset[i]; 1497 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, 1498 res, (unsigned long long)offset); 1499 1500 pci_add_resource_offset(resources, res, offset); 1501 } 1502 } 1503 1504 /* 1505 * Null PCI config access functions, for the case when we can't 1506 * find a hose. 1507 */ 1508 #define NULL_PCI_OP(rw, size, type) \ 1509 static int \ 1510 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1511 { \ 1512 return PCIBIOS_DEVICE_NOT_FOUND; \ 1513 } 1514 1515 static int 1516 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1517 int len, u32 *val) 1518 { 1519 return PCIBIOS_DEVICE_NOT_FOUND; 1520 } 1521 1522 static int 1523 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1524 int len, u32 val) 1525 { 1526 return PCIBIOS_DEVICE_NOT_FOUND; 1527 } 1528 1529 static struct pci_ops null_pci_ops = 1530 { 1531 .read = null_read_config, 1532 .write = null_write_config, 1533 }; 1534 1535 /* 1536 * These functions are used early on before PCI scanning is done 1537 * and all of the pci_dev and pci_bus structures have been created. 1538 */ 1539 static struct pci_bus * 1540 fake_pci_bus(struct pci_controller *hose, int busnr) 1541 { 1542 static struct pci_bus bus; 1543 1544 if (hose == NULL) { 1545 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1546 } 1547 bus.number = busnr; 1548 bus.sysdata = hose; 1549 bus.ops = hose? hose->ops: &null_pci_ops; 1550 return &bus; 1551 } 1552 1553 #define EARLY_PCI_OP(rw, size, type) \ 1554 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1555 int devfn, int offset, type value) \ 1556 { \ 1557 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1558 devfn, offset, value); \ 1559 } 1560 1561 EARLY_PCI_OP(read, byte, u8 *) 1562 EARLY_PCI_OP(read, word, u16 *) 1563 EARLY_PCI_OP(read, dword, u32 *) 1564 EARLY_PCI_OP(write, byte, u8) 1565 EARLY_PCI_OP(write, word, u16) 1566 EARLY_PCI_OP(write, dword, u32) 1567 1568 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1569 int cap) 1570 { 1571 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1572 } 1573 1574 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1575 { 1576 struct pci_controller *hose = bus->sysdata; 1577 1578 return of_node_get(hose->dn); 1579 } 1580 1581 /** 1582 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1583 * @hose: Pointer to the PCI host controller instance structure 1584 */ 1585 void pcibios_scan_phb(struct pci_controller *hose) 1586 { 1587 LIST_HEAD(resources); 1588 struct pci_bus *bus; 1589 struct device_node *node = hose->dn; 1590 int mode; 1591 1592 pr_debug("PCI: Scanning PHB %pOF\n", node); 1593 1594 /* Get some IO space for the new PHB */ 1595 pcibios_setup_phb_io_space(hose); 1596 1597 /* Wire up PHB bus resources */ 1598 pcibios_setup_phb_resources(hose, &resources); 1599 1600 hose->busn.start = hose->first_busno; 1601 hose->busn.end = hose->last_busno; 1602 hose->busn.flags = IORESOURCE_BUS; 1603 pci_add_resource(&resources, &hose->busn); 1604 1605 /* Create an empty bus for the toplevel */ 1606 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1607 hose->ops, hose, &resources); 1608 if (bus == NULL) { 1609 pr_err("Failed to create bus for PCI domain %04x\n", 1610 hose->global_number); 1611 pci_free_resource_list(&resources); 1612 return; 1613 } 1614 hose->bus = bus; 1615 1616 /* Get probe mode and perform scan */ 1617 mode = PCI_PROBE_NORMAL; 1618 if (node && hose->controller_ops.probe_mode) 1619 mode = hose->controller_ops.probe_mode(bus); 1620 pr_debug(" probe mode: %d\n", mode); 1621 if (mode == PCI_PROBE_DEVTREE) 1622 of_scan_bus(node, bus); 1623 1624 if (mode == PCI_PROBE_NORMAL) { 1625 pci_bus_update_busn_res_end(bus, 255); 1626 hose->last_busno = pci_scan_child_bus(bus); 1627 pci_bus_update_busn_res_end(bus, hose->last_busno); 1628 } 1629 1630 /* Platform gets a chance to do some global fixups before 1631 * we proceed to resource allocation 1632 */ 1633 if (ppc_md.pcibios_fixup_phb) 1634 ppc_md.pcibios_fixup_phb(hose); 1635 1636 /* Configure PCI Express settings */ 1637 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1638 struct pci_bus *child; 1639 list_for_each_entry(child, &bus->children, node) 1640 pcie_bus_configure_settings(child); 1641 } 1642 } 1643 EXPORT_SYMBOL_GPL(pcibios_scan_phb); 1644 1645 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1646 { 1647 int i, class = dev->class >> 8; 1648 /* When configured as agent, programing interface = 1 */ 1649 int prog_if = dev->class & 0xf; 1650 1651 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1652 class == PCI_CLASS_BRIDGE_OTHER) && 1653 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1654 (prog_if == 0) && 1655 (dev->bus->parent == NULL)) { 1656 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1657 dev->resource[i].start = 0; 1658 dev->resource[i].end = 0; 1659 dev->resource[i].flags = 0; 1660 } 1661 } 1662 } 1663 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1665