1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/list.h> 29 #include <linux/syscalls.h> 30 #include <linux/irq.h> 31 #include <linux/vmalloc.h> 32 #include <linux/slab.h> 33 #include <linux/vgaarb.h> 34 35 #include <asm/processor.h> 36 #include <asm/io.h> 37 #include <asm/prom.h> 38 #include <asm/pci-bridge.h> 39 #include <asm/byteorder.h> 40 #include <asm/machdep.h> 41 #include <asm/ppc-pci.h> 42 #include <asm/eeh.h> 43 44 static DEFINE_SPINLOCK(hose_spinlock); 45 LIST_HEAD(hose_list); 46 47 /* XXX kill that some day ... */ 48 static int global_phb_number; /* Global phb counter */ 49 50 /* ISA Memory physical address */ 51 resource_size_t isa_mem_base; 52 53 54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 55 56 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 57 { 58 pci_dma_ops = dma_ops; 59 } 60 61 struct dma_map_ops *get_pci_dma_ops(void) 62 { 63 return pci_dma_ops; 64 } 65 EXPORT_SYMBOL(get_pci_dma_ops); 66 67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 68 { 69 struct pci_controller *phb; 70 71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 72 if (phb == NULL) 73 return NULL; 74 spin_lock(&hose_spinlock); 75 phb->global_number = global_phb_number++; 76 list_add_tail(&phb->list_node, &hose_list); 77 spin_unlock(&hose_spinlock); 78 phb->dn = dev; 79 phb->is_dynamic = slab_is_available(); 80 #ifdef CONFIG_PPC64 81 if (dev) { 82 int nid = of_node_to_nid(dev); 83 84 if (nid < 0 || !node_online(nid)) 85 nid = -1; 86 87 PHB_SET_NODE(phb, nid); 88 } 89 #endif 90 return phb; 91 } 92 EXPORT_SYMBOL_GPL(pcibios_alloc_controller); 93 94 void pcibios_free_controller(struct pci_controller *phb) 95 { 96 spin_lock(&hose_spinlock); 97 list_del(&phb->list_node); 98 spin_unlock(&hose_spinlock); 99 100 if (phb->is_dynamic) 101 kfree(phb); 102 } 103 104 /* 105 * The function is used to return the minimal alignment 106 * for memory or I/O windows of the associated P2P bridge. 107 * By default, 4KiB alignment for I/O windows and 1MiB for 108 * memory windows. 109 */ 110 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 111 unsigned long type) 112 { 113 struct pci_controller *phb = pci_bus_to_host(bus); 114 115 if (phb->controller_ops.window_alignment) 116 return phb->controller_ops.window_alignment(bus, type); 117 118 /* 119 * PCI core will figure out the default 120 * alignment: 4KiB for I/O and 1MiB for 121 * memory window. 122 */ 123 return 1; 124 } 125 126 void pcibios_reset_secondary_bus(struct pci_dev *dev) 127 { 128 struct pci_controller *phb = pci_bus_to_host(dev->bus); 129 130 if (phb->controller_ops.reset_secondary_bus) { 131 phb->controller_ops.reset_secondary_bus(dev); 132 return; 133 } 134 135 pci_reset_secondary_bus(dev); 136 } 137 138 #ifdef CONFIG_PCI_IOV 139 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) 140 { 141 if (ppc_md.pcibios_iov_resource_alignment) 142 return ppc_md.pcibios_iov_resource_alignment(pdev, resno); 143 144 return pci_iov_resource_size(pdev, resno); 145 } 146 #endif /* CONFIG_PCI_IOV */ 147 148 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 149 { 150 #ifdef CONFIG_PPC64 151 return hose->pci_io_size; 152 #else 153 return resource_size(&hose->io_resource); 154 #endif 155 } 156 157 int pcibios_vaddr_is_ioport(void __iomem *address) 158 { 159 int ret = 0; 160 struct pci_controller *hose; 161 resource_size_t size; 162 163 spin_lock(&hose_spinlock); 164 list_for_each_entry(hose, &hose_list, list_node) { 165 size = pcibios_io_size(hose); 166 if (address >= hose->io_base_virt && 167 address < (hose->io_base_virt + size)) { 168 ret = 1; 169 break; 170 } 171 } 172 spin_unlock(&hose_spinlock); 173 return ret; 174 } 175 176 unsigned long pci_address_to_pio(phys_addr_t address) 177 { 178 struct pci_controller *hose; 179 resource_size_t size; 180 unsigned long ret = ~0; 181 182 spin_lock(&hose_spinlock); 183 list_for_each_entry(hose, &hose_list, list_node) { 184 size = pcibios_io_size(hose); 185 if (address >= hose->io_base_phys && 186 address < (hose->io_base_phys + size)) { 187 unsigned long base = 188 (unsigned long)hose->io_base_virt - _IO_BASE; 189 ret = base + (address - hose->io_base_phys); 190 break; 191 } 192 } 193 spin_unlock(&hose_spinlock); 194 195 return ret; 196 } 197 EXPORT_SYMBOL_GPL(pci_address_to_pio); 198 199 /* 200 * Return the domain number for this bus. 201 */ 202 int pci_domain_nr(struct pci_bus *bus) 203 { 204 struct pci_controller *hose = pci_bus_to_host(bus); 205 206 return hose->global_number; 207 } 208 EXPORT_SYMBOL(pci_domain_nr); 209 210 /* This routine is meant to be used early during boot, when the 211 * PCI bus numbers have not yet been assigned, and you need to 212 * issue PCI config cycles to an OF device. 213 * It could also be used to "fix" RTAS config cycles if you want 214 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 215 * config cycles. 216 */ 217 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 218 { 219 while(node) { 220 struct pci_controller *hose, *tmp; 221 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 222 if (hose->dn == node) 223 return hose; 224 node = node->parent; 225 } 226 return NULL; 227 } 228 229 /* 230 * Reads the interrupt pin to determine if interrupt is use by card. 231 * If the interrupt is used, then gets the interrupt line from the 232 * openfirmware and sets it in the pci_dev and pci_config line. 233 */ 234 static int pci_read_irq_line(struct pci_dev *pci_dev) 235 { 236 struct of_phandle_args oirq; 237 unsigned int virq; 238 239 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 240 241 #ifdef DEBUG 242 memset(&oirq, 0xff, sizeof(oirq)); 243 #endif 244 /* Try to get a mapping from the device-tree */ 245 if (of_irq_parse_pci(pci_dev, &oirq)) { 246 u8 line, pin; 247 248 /* If that fails, lets fallback to what is in the config 249 * space and map that through the default controller. We 250 * also set the type to level low since that's what PCI 251 * interrupts are. If your platform does differently, then 252 * either provide a proper interrupt tree or don't use this 253 * function. 254 */ 255 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 256 return -1; 257 if (pin == 0) 258 return -1; 259 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 260 line == 0xff || line == 0) { 261 return -1; 262 } 263 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 264 line, pin); 265 266 virq = irq_create_mapping(NULL, line); 267 if (virq != NO_IRQ) 268 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 269 } else { 270 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 271 oirq.args_count, oirq.args[0], oirq.args[1], 272 of_node_full_name(oirq.np)); 273 274 virq = irq_create_of_mapping(&oirq); 275 } 276 if(virq == NO_IRQ) { 277 pr_debug(" Failed to map !\n"); 278 return -1; 279 } 280 281 pr_debug(" Mapped to linux irq %d\n", virq); 282 283 pci_dev->irq = virq; 284 285 return 0; 286 } 287 288 /* 289 * Platform support for /proc/bus/pci/X/Y mmap()s, 290 * modelled on the sparc64 implementation by Dave Miller. 291 * -- paulus. 292 */ 293 294 /* 295 * Adjust vm_pgoff of VMA such that it is the physical page offset 296 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 297 * 298 * Basically, the user finds the base address for his device which he wishes 299 * to mmap. They read the 32-bit value from the config space base register, 300 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 301 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 302 * 303 * Returns negative error code on failure, zero on success. 304 */ 305 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 306 resource_size_t *offset, 307 enum pci_mmap_state mmap_state) 308 { 309 struct pci_controller *hose = pci_bus_to_host(dev->bus); 310 unsigned long io_offset = 0; 311 int i, res_bit; 312 313 if (hose == NULL) 314 return NULL; /* should never happen */ 315 316 /* If memory, add on the PCI bridge address offset */ 317 if (mmap_state == pci_mmap_mem) { 318 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 319 *offset += hose->pci_mem_offset; 320 #endif 321 res_bit = IORESOURCE_MEM; 322 } else { 323 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 324 *offset += io_offset; 325 res_bit = IORESOURCE_IO; 326 } 327 328 /* 329 * Check that the offset requested corresponds to one of the 330 * resources of the device. 331 */ 332 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 333 struct resource *rp = &dev->resource[i]; 334 int flags = rp->flags; 335 336 /* treat ROM as memory (should be already) */ 337 if (i == PCI_ROM_RESOURCE) 338 flags |= IORESOURCE_MEM; 339 340 /* Active and same type? */ 341 if ((flags & res_bit) == 0) 342 continue; 343 344 /* In the range of this resource? */ 345 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 346 continue; 347 348 /* found it! construct the final physical address */ 349 if (mmap_state == pci_mmap_io) 350 *offset += hose->io_base_phys - io_offset; 351 return rp; 352 } 353 354 return NULL; 355 } 356 357 /* 358 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 359 * device mapping. 360 */ 361 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 362 pgprot_t protection, 363 enum pci_mmap_state mmap_state, 364 int write_combine) 365 { 366 367 /* Write combine is always 0 on non-memory space mappings. On 368 * memory space, if the user didn't pass 1, we check for a 369 * "prefetchable" resource. This is a bit hackish, but we use 370 * this to workaround the inability of /sysfs to provide a write 371 * combine bit 372 */ 373 if (mmap_state != pci_mmap_mem) 374 write_combine = 0; 375 else if (write_combine == 0) { 376 if (rp->flags & IORESOURCE_PREFETCH) 377 write_combine = 1; 378 } 379 380 /* XXX would be nice to have a way to ask for write-through */ 381 if (write_combine) 382 return pgprot_noncached_wc(protection); 383 else 384 return pgprot_noncached(protection); 385 } 386 387 /* 388 * This one is used by /dev/mem and fbdev who have no clue about the 389 * PCI device, it tries to find the PCI device first and calls the 390 * above routine 391 */ 392 pgprot_t pci_phys_mem_access_prot(struct file *file, 393 unsigned long pfn, 394 unsigned long size, 395 pgprot_t prot) 396 { 397 struct pci_dev *pdev = NULL; 398 struct resource *found = NULL; 399 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 400 int i; 401 402 if (page_is_ram(pfn)) 403 return prot; 404 405 prot = pgprot_noncached(prot); 406 for_each_pci_dev(pdev) { 407 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 408 struct resource *rp = &pdev->resource[i]; 409 int flags = rp->flags; 410 411 /* Active and same type? */ 412 if ((flags & IORESOURCE_MEM) == 0) 413 continue; 414 /* In the range of this resource? */ 415 if (offset < (rp->start & PAGE_MASK) || 416 offset > rp->end) 417 continue; 418 found = rp; 419 break; 420 } 421 if (found) 422 break; 423 } 424 if (found) { 425 if (found->flags & IORESOURCE_PREFETCH) 426 prot = pgprot_noncached_wc(prot); 427 pci_dev_put(pdev); 428 } 429 430 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 431 (unsigned long long)offset, pgprot_val(prot)); 432 433 return prot; 434 } 435 436 437 /* 438 * Perform the actual remap of the pages for a PCI device mapping, as 439 * appropriate for this architecture. The region in the process to map 440 * is described by vm_start and vm_end members of VMA, the base physical 441 * address is found in vm_pgoff. 442 * The pci device structure is provided so that architectures may make mapping 443 * decisions on a per-device or per-bus basis. 444 * 445 * Returns a negative error code on failure, zero on success. 446 */ 447 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 448 enum pci_mmap_state mmap_state, int write_combine) 449 { 450 resource_size_t offset = 451 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 452 struct resource *rp; 453 int ret; 454 455 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 456 if (rp == NULL) 457 return -EINVAL; 458 459 vma->vm_pgoff = offset >> PAGE_SHIFT; 460 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 461 vma->vm_page_prot, 462 mmap_state, write_combine); 463 464 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 465 vma->vm_end - vma->vm_start, vma->vm_page_prot); 466 467 return ret; 468 } 469 470 /* This provides legacy IO read access on a bus */ 471 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 472 { 473 unsigned long offset; 474 struct pci_controller *hose = pci_bus_to_host(bus); 475 struct resource *rp = &hose->io_resource; 476 void __iomem *addr; 477 478 /* Check if port can be supported by that bus. We only check 479 * the ranges of the PHB though, not the bus itself as the rules 480 * for forwarding legacy cycles down bridges are not our problem 481 * here. So if the host bridge supports it, we do it. 482 */ 483 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 484 offset += port; 485 486 if (!(rp->flags & IORESOURCE_IO)) 487 return -ENXIO; 488 if (offset < rp->start || (offset + size) > rp->end) 489 return -ENXIO; 490 addr = hose->io_base_virt + port; 491 492 switch(size) { 493 case 1: 494 *((u8 *)val) = in_8(addr); 495 return 1; 496 case 2: 497 if (port & 1) 498 return -EINVAL; 499 *((u16 *)val) = in_le16(addr); 500 return 2; 501 case 4: 502 if (port & 3) 503 return -EINVAL; 504 *((u32 *)val) = in_le32(addr); 505 return 4; 506 } 507 return -EINVAL; 508 } 509 510 /* This provides legacy IO write access on a bus */ 511 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 512 { 513 unsigned long offset; 514 struct pci_controller *hose = pci_bus_to_host(bus); 515 struct resource *rp = &hose->io_resource; 516 void __iomem *addr; 517 518 /* Check if port can be supported by that bus. We only check 519 * the ranges of the PHB though, not the bus itself as the rules 520 * for forwarding legacy cycles down bridges are not our problem 521 * here. So if the host bridge supports it, we do it. 522 */ 523 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 524 offset += port; 525 526 if (!(rp->flags & IORESOURCE_IO)) 527 return -ENXIO; 528 if (offset < rp->start || (offset + size) > rp->end) 529 return -ENXIO; 530 addr = hose->io_base_virt + port; 531 532 /* WARNING: The generic code is idiotic. It gets passed a pointer 533 * to what can be a 1, 2 or 4 byte quantity and always reads that 534 * as a u32, which means that we have to correct the location of 535 * the data read within those 32 bits for size 1 and 2 536 */ 537 switch(size) { 538 case 1: 539 out_8(addr, val >> 24); 540 return 1; 541 case 2: 542 if (port & 1) 543 return -EINVAL; 544 out_le16(addr, val >> 16); 545 return 2; 546 case 4: 547 if (port & 3) 548 return -EINVAL; 549 out_le32(addr, val); 550 return 4; 551 } 552 return -EINVAL; 553 } 554 555 /* This provides legacy IO or memory mmap access on a bus */ 556 int pci_mmap_legacy_page_range(struct pci_bus *bus, 557 struct vm_area_struct *vma, 558 enum pci_mmap_state mmap_state) 559 { 560 struct pci_controller *hose = pci_bus_to_host(bus); 561 resource_size_t offset = 562 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 563 resource_size_t size = vma->vm_end - vma->vm_start; 564 struct resource *rp; 565 566 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 567 pci_domain_nr(bus), bus->number, 568 mmap_state == pci_mmap_mem ? "MEM" : "IO", 569 (unsigned long long)offset, 570 (unsigned long long)(offset + size - 1)); 571 572 if (mmap_state == pci_mmap_mem) { 573 /* Hack alert ! 574 * 575 * Because X is lame and can fail starting if it gets an error trying 576 * to mmap legacy_mem (instead of just moving on without legacy memory 577 * access) we fake it here by giving it anonymous memory, effectively 578 * behaving just like /dev/zero 579 */ 580 if ((offset + size) > hose->isa_mem_size) { 581 printk(KERN_DEBUG 582 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 583 current->comm, current->pid, pci_domain_nr(bus), bus->number); 584 if (vma->vm_flags & VM_SHARED) 585 return shmem_zero_setup(vma); 586 return 0; 587 } 588 offset += hose->isa_mem_phys; 589 } else { 590 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 591 unsigned long roffset = offset + io_offset; 592 rp = &hose->io_resource; 593 if (!(rp->flags & IORESOURCE_IO)) 594 return -ENXIO; 595 if (roffset < rp->start || (roffset + size) > rp->end) 596 return -ENXIO; 597 offset += hose->io_base_phys; 598 } 599 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 600 601 vma->vm_pgoff = offset >> PAGE_SHIFT; 602 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 603 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 604 vma->vm_end - vma->vm_start, 605 vma->vm_page_prot); 606 } 607 608 void pci_resource_to_user(const struct pci_dev *dev, int bar, 609 const struct resource *rsrc, 610 resource_size_t *start, resource_size_t *end) 611 { 612 struct pci_controller *hose = pci_bus_to_host(dev->bus); 613 resource_size_t offset = 0; 614 615 if (hose == NULL) 616 return; 617 618 if (rsrc->flags & IORESOURCE_IO) 619 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 620 621 /* We pass a fully fixed up address to userland for MMIO instead of 622 * a BAR value because X is lame and expects to be able to use that 623 * to pass to /dev/mem ! 624 * 625 * That means that we'll have potentially 64 bits values where some 626 * userland apps only expect 32 (like X itself since it thinks only 627 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 628 * 32 bits CHRPs :-( 629 * 630 * Hopefully, the sysfs insterface is immune to that gunk. Once X 631 * has been fixed (and the fix spread enough), we can re-enable the 632 * 2 lines below and pass down a BAR value to userland. In that case 633 * we'll also have to re-enable the matching code in 634 * __pci_mmap_make_offset(). 635 * 636 * BenH. 637 */ 638 #if 0 639 else if (rsrc->flags & IORESOURCE_MEM) 640 offset = hose->pci_mem_offset; 641 #endif 642 643 *start = rsrc->start - offset; 644 *end = rsrc->end - offset; 645 } 646 647 /** 648 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 649 * @hose: newly allocated pci_controller to be setup 650 * @dev: device node of the host bridge 651 * @primary: set if primary bus (32 bits only, soon to be deprecated) 652 * 653 * This function will parse the "ranges" property of a PCI host bridge device 654 * node and setup the resource mapping of a pci controller based on its 655 * content. 656 * 657 * Life would be boring if it wasn't for a few issues that we have to deal 658 * with here: 659 * 660 * - We can only cope with one IO space range and up to 3 Memory space 661 * ranges. However, some machines (thanks Apple !) tend to split their 662 * space into lots of small contiguous ranges. So we have to coalesce. 663 * 664 * - Some busses have IO space not starting at 0, which causes trouble with 665 * the way we do our IO resource renumbering. The code somewhat deals with 666 * it for 64 bits but I would expect problems on 32 bits. 667 * 668 * - Some 32 bits platforms such as 4xx can have physical space larger than 669 * 32 bits so we need to use 64 bits values for the parsing 670 */ 671 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 672 struct device_node *dev, int primary) 673 { 674 int memno = 0; 675 struct resource *res; 676 struct of_pci_range range; 677 struct of_pci_range_parser parser; 678 679 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 680 dev->full_name, primary ? "(primary)" : ""); 681 682 /* Check for ranges property */ 683 if (of_pci_range_parser_init(&parser, dev)) 684 return; 685 686 /* Parse it */ 687 for_each_of_pci_range(&parser, &range) { 688 /* If we failed translation or got a zero-sized region 689 * (some FW try to feed us with non sensical zero sized regions 690 * such as power3 which look like some kind of attempt at exposing 691 * the VGA memory hole) 692 */ 693 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 694 continue; 695 696 /* Act based on address space type */ 697 res = NULL; 698 switch (range.flags & IORESOURCE_TYPE_BITS) { 699 case IORESOURCE_IO: 700 printk(KERN_INFO 701 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 702 range.cpu_addr, range.cpu_addr + range.size - 1, 703 range.pci_addr); 704 705 /* We support only one IO range */ 706 if (hose->pci_io_size) { 707 printk(KERN_INFO 708 " \\--> Skipped (too many) !\n"); 709 continue; 710 } 711 #ifdef CONFIG_PPC32 712 /* On 32 bits, limit I/O space to 16MB */ 713 if (range.size > 0x01000000) 714 range.size = 0x01000000; 715 716 /* 32 bits needs to map IOs here */ 717 hose->io_base_virt = ioremap(range.cpu_addr, 718 range.size); 719 720 /* Expect trouble if pci_addr is not 0 */ 721 if (primary) 722 isa_io_base = 723 (unsigned long)hose->io_base_virt; 724 #endif /* CONFIG_PPC32 */ 725 /* pci_io_size and io_base_phys always represent IO 726 * space starting at 0 so we factor in pci_addr 727 */ 728 hose->pci_io_size = range.pci_addr + range.size; 729 hose->io_base_phys = range.cpu_addr - range.pci_addr; 730 731 /* Build resource */ 732 res = &hose->io_resource; 733 range.cpu_addr = range.pci_addr; 734 break; 735 case IORESOURCE_MEM: 736 printk(KERN_INFO 737 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 738 range.cpu_addr, range.cpu_addr + range.size - 1, 739 range.pci_addr, 740 (range.pci_space & 0x40000000) ? 741 "Prefetch" : ""); 742 743 /* We support only 3 memory ranges */ 744 if (memno >= 3) { 745 printk(KERN_INFO 746 " \\--> Skipped (too many) !\n"); 747 continue; 748 } 749 /* Handles ISA memory hole space here */ 750 if (range.pci_addr == 0) { 751 if (primary || isa_mem_base == 0) 752 isa_mem_base = range.cpu_addr; 753 hose->isa_mem_phys = range.cpu_addr; 754 hose->isa_mem_size = range.size; 755 } 756 757 /* Build resource */ 758 hose->mem_offset[memno] = range.cpu_addr - 759 range.pci_addr; 760 res = &hose->mem_resources[memno++]; 761 break; 762 } 763 if (res != NULL) { 764 res->name = dev->full_name; 765 res->flags = range.flags; 766 res->start = range.cpu_addr; 767 res->end = range.cpu_addr + range.size - 1; 768 res->parent = res->child = res->sibling = NULL; 769 } 770 } 771 } 772 773 /* Decide whether to display the domain number in /proc */ 774 int pci_proc_domain(struct pci_bus *bus) 775 { 776 struct pci_controller *hose = pci_bus_to_host(bus); 777 778 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 779 return 0; 780 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 781 return hose->global_number != 0; 782 return 1; 783 } 784 785 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 786 { 787 if (ppc_md.pcibios_root_bridge_prepare) 788 return ppc_md.pcibios_root_bridge_prepare(bridge); 789 790 return 0; 791 } 792 793 /* This header fixup will do the resource fixup for all devices as they are 794 * probed, but not for bridge ranges 795 */ 796 static void pcibios_fixup_resources(struct pci_dev *dev) 797 { 798 struct pci_controller *hose = pci_bus_to_host(dev->bus); 799 int i; 800 801 if (!hose) { 802 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 803 pci_name(dev)); 804 return; 805 } 806 807 if (dev->is_virtfn) 808 return; 809 810 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 811 struct resource *res = dev->resource + i; 812 struct pci_bus_region reg; 813 if (!res->flags) 814 continue; 815 816 /* If we're going to re-assign everything, we mark all resources 817 * as unset (and 0-base them). In addition, we mark BARs starting 818 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 819 * since in that case, we don't want to re-assign anything 820 */ 821 pcibios_resource_to_bus(dev->bus, ®, res); 822 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 823 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 824 /* Only print message if not re-assigning */ 825 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 826 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 827 "is unassigned\n", 828 pci_name(dev), i, 829 (unsigned long long)res->start, 830 (unsigned long long)res->end, 831 (unsigned int)res->flags); 832 res->end -= res->start; 833 res->start = 0; 834 res->flags |= IORESOURCE_UNSET; 835 continue; 836 } 837 838 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 839 pci_name(dev), i, 840 (unsigned long long)res->start,\ 841 (unsigned long long)res->end, 842 (unsigned int)res->flags); 843 } 844 845 /* Call machine specific resource fixup */ 846 if (ppc_md.pcibios_fixup_resources) 847 ppc_md.pcibios_fixup_resources(dev); 848 } 849 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 850 851 /* This function tries to figure out if a bridge resource has been initialized 852 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 853 * things go more smoothly when it gets it right. It should covers cases such 854 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 855 */ 856 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 857 struct resource *res) 858 { 859 struct pci_controller *hose = pci_bus_to_host(bus); 860 struct pci_dev *dev = bus->self; 861 resource_size_t offset; 862 struct pci_bus_region region; 863 u16 command; 864 int i; 865 866 /* We don't do anything if PCI_PROBE_ONLY is set */ 867 if (pci_has_flag(PCI_PROBE_ONLY)) 868 return 0; 869 870 /* Job is a bit different between memory and IO */ 871 if (res->flags & IORESOURCE_MEM) { 872 pcibios_resource_to_bus(dev->bus, ®ion, res); 873 874 /* If the BAR is non-0 then it's probably been initialized */ 875 if (region.start != 0) 876 return 0; 877 878 /* The BAR is 0, let's check if memory decoding is enabled on 879 * the bridge. If not, we consider it unassigned 880 */ 881 pci_read_config_word(dev, PCI_COMMAND, &command); 882 if ((command & PCI_COMMAND_MEMORY) == 0) 883 return 1; 884 885 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 886 * resources covers that starting address (0 then it's good enough for 887 * us for memory space) 888 */ 889 for (i = 0; i < 3; i++) { 890 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 891 hose->mem_resources[i].start == hose->mem_offset[i]) 892 return 0; 893 } 894 895 /* Well, it starts at 0 and we know it will collide so we may as 896 * well consider it as unassigned. That covers the Apple case. 897 */ 898 return 1; 899 } else { 900 /* If the BAR is non-0, then we consider it assigned */ 901 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 902 if (((res->start - offset) & 0xfffffffful) != 0) 903 return 0; 904 905 /* Here, we are a bit different than memory as typically IO space 906 * starting at low addresses -is- valid. What we do instead if that 907 * we consider as unassigned anything that doesn't have IO enabled 908 * in the PCI command register, and that's it. 909 */ 910 pci_read_config_word(dev, PCI_COMMAND, &command); 911 if (command & PCI_COMMAND_IO) 912 return 0; 913 914 /* It's starting at 0 and IO is disabled in the bridge, consider 915 * it unassigned 916 */ 917 return 1; 918 } 919 } 920 921 /* Fixup resources of a PCI<->PCI bridge */ 922 static void pcibios_fixup_bridge(struct pci_bus *bus) 923 { 924 struct resource *res; 925 int i; 926 927 struct pci_dev *dev = bus->self; 928 929 pci_bus_for_each_resource(bus, res, i) { 930 if (!res || !res->flags) 931 continue; 932 if (i >= 3 && bus->self->transparent) 933 continue; 934 935 /* If we're going to reassign everything, we can 936 * shrink the P2P resource to have size as being 937 * of 0 in order to save space. 938 */ 939 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 940 res->flags |= IORESOURCE_UNSET; 941 res->start = 0; 942 res->end = -1; 943 continue; 944 } 945 946 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 947 pci_name(dev), i, 948 (unsigned long long)res->start,\ 949 (unsigned long long)res->end, 950 (unsigned int)res->flags); 951 952 /* Try to detect uninitialized P2P bridge resources, 953 * and clear them out so they get re-assigned later 954 */ 955 if (pcibios_uninitialized_bridge_resource(bus, res)) { 956 res->flags = 0; 957 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 958 } 959 } 960 } 961 962 void pcibios_setup_bus_self(struct pci_bus *bus) 963 { 964 struct pci_controller *phb; 965 966 /* Fix up the bus resources for P2P bridges */ 967 if (bus->self != NULL) 968 pcibios_fixup_bridge(bus); 969 970 /* Platform specific bus fixups. This is currently only used 971 * by fsl_pci and I'm hoping to get rid of it at some point 972 */ 973 if (ppc_md.pcibios_fixup_bus) 974 ppc_md.pcibios_fixup_bus(bus); 975 976 /* Setup bus DMA mappings */ 977 phb = pci_bus_to_host(bus); 978 if (phb->controller_ops.dma_bus_setup) 979 phb->controller_ops.dma_bus_setup(bus); 980 } 981 982 static void pcibios_setup_device(struct pci_dev *dev) 983 { 984 struct pci_controller *phb; 985 /* Fixup NUMA node as it may not be setup yet by the generic 986 * code and is needed by the DMA init 987 */ 988 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 989 990 /* Hook up default DMA ops */ 991 set_dma_ops(&dev->dev, pci_dma_ops); 992 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 993 994 /* Additional platform DMA/iommu setup */ 995 phb = pci_bus_to_host(dev->bus); 996 if (phb->controller_ops.dma_dev_setup) 997 phb->controller_ops.dma_dev_setup(dev); 998 999 /* Read default IRQs and fixup if necessary */ 1000 pci_read_irq_line(dev); 1001 if (ppc_md.pci_irq_fixup) 1002 ppc_md.pci_irq_fixup(dev); 1003 } 1004 1005 int pcibios_add_device(struct pci_dev *dev) 1006 { 1007 /* 1008 * We can only call pcibios_setup_device() after bus setup is complete, 1009 * since some of the platform specific DMA setup code depends on it. 1010 */ 1011 if (dev->bus->is_added) 1012 pcibios_setup_device(dev); 1013 1014 #ifdef CONFIG_PCI_IOV 1015 if (ppc_md.pcibios_fixup_sriov) 1016 ppc_md.pcibios_fixup_sriov(dev); 1017 #endif /* CONFIG_PCI_IOV */ 1018 1019 return 0; 1020 } 1021 1022 void pcibios_setup_bus_devices(struct pci_bus *bus) 1023 { 1024 struct pci_dev *dev; 1025 1026 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1027 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1028 1029 list_for_each_entry(dev, &bus->devices, bus_list) { 1030 /* Cardbus can call us to add new devices to a bus, so ignore 1031 * those who are already fully discovered 1032 */ 1033 if (dev->is_added) 1034 continue; 1035 1036 pcibios_setup_device(dev); 1037 } 1038 } 1039 1040 void pcibios_set_master(struct pci_dev *dev) 1041 { 1042 /* No special bus mastering setup handling */ 1043 } 1044 1045 void pcibios_fixup_bus(struct pci_bus *bus) 1046 { 1047 /* Fixup the bus */ 1048 pcibios_setup_bus_self(bus); 1049 1050 /* Now fixup devices on that bus */ 1051 pcibios_setup_bus_devices(bus); 1052 } 1053 EXPORT_SYMBOL(pcibios_fixup_bus); 1054 1055 void pci_fixup_cardbus(struct pci_bus *bus) 1056 { 1057 /* Now fixup devices on that bus */ 1058 pcibios_setup_bus_devices(bus); 1059 } 1060 1061 1062 static int skip_isa_ioresource_align(struct pci_dev *dev) 1063 { 1064 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1065 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1066 return 1; 1067 return 0; 1068 } 1069 1070 /* 1071 * We need to avoid collisions with `mirrored' VGA ports 1072 * and other strange ISA hardware, so we always want the 1073 * addresses to be allocated in the 0x000-0x0ff region 1074 * modulo 0x400. 1075 * 1076 * Why? Because some silly external IO cards only decode 1077 * the low 10 bits of the IO address. The 0x00-0xff region 1078 * is reserved for motherboard devices that decode all 16 1079 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1080 * but we want to try to avoid allocating at 0x2900-0x2bff 1081 * which might have be mirrored at 0x0100-0x03ff.. 1082 */ 1083 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1084 resource_size_t size, resource_size_t align) 1085 { 1086 struct pci_dev *dev = data; 1087 resource_size_t start = res->start; 1088 1089 if (res->flags & IORESOURCE_IO) { 1090 if (skip_isa_ioresource_align(dev)) 1091 return start; 1092 if (start & 0x300) 1093 start = (start + 0x3ff) & ~0x3ff; 1094 } 1095 1096 return start; 1097 } 1098 EXPORT_SYMBOL(pcibios_align_resource); 1099 1100 /* 1101 * Reparent resource children of pr that conflict with res 1102 * under res, and make res replace those children. 1103 */ 1104 static int reparent_resources(struct resource *parent, 1105 struct resource *res) 1106 { 1107 struct resource *p, **pp; 1108 struct resource **firstpp = NULL; 1109 1110 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1111 if (p->end < res->start) 1112 continue; 1113 if (res->end < p->start) 1114 break; 1115 if (p->start < res->start || p->end > res->end) 1116 return -1; /* not completely contained */ 1117 if (firstpp == NULL) 1118 firstpp = pp; 1119 } 1120 if (firstpp == NULL) 1121 return -1; /* didn't find any conflicting entries? */ 1122 res->parent = parent; 1123 res->child = *firstpp; 1124 res->sibling = *pp; 1125 *firstpp = res; 1126 *pp = NULL; 1127 for (p = res->child; p != NULL; p = p->sibling) { 1128 p->parent = res; 1129 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1130 p->name, 1131 (unsigned long long)p->start, 1132 (unsigned long long)p->end, res->name); 1133 } 1134 return 0; 1135 } 1136 1137 /* 1138 * Handle resources of PCI devices. If the world were perfect, we could 1139 * just allocate all the resource regions and do nothing more. It isn't. 1140 * On the other hand, we cannot just re-allocate all devices, as it would 1141 * require us to know lots of host bridge internals. So we attempt to 1142 * keep as much of the original configuration as possible, but tweak it 1143 * when it's found to be wrong. 1144 * 1145 * Known BIOS problems we have to work around: 1146 * - I/O or memory regions not configured 1147 * - regions configured, but not enabled in the command register 1148 * - bogus I/O addresses above 64K used 1149 * - expansion ROMs left enabled (this may sound harmless, but given 1150 * the fact the PCI specs explicitly allow address decoders to be 1151 * shared between expansion ROMs and other resource regions, it's 1152 * at least dangerous) 1153 * 1154 * Our solution: 1155 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1156 * This gives us fixed barriers on where we can allocate. 1157 * (2) Allocate resources for all enabled devices. If there is 1158 * a collision, just mark the resource as unallocated. Also 1159 * disable expansion ROMs during this step. 1160 * (3) Try to allocate resources for disabled devices. If the 1161 * resources were assigned correctly, everything goes well, 1162 * if they weren't, they won't disturb allocation of other 1163 * resources. 1164 * (4) Assign new addresses to resources which were either 1165 * not configured at all or misconfigured. If explicitly 1166 * requested by the user, configure expansion ROM address 1167 * as well. 1168 */ 1169 1170 static void pcibios_allocate_bus_resources(struct pci_bus *bus) 1171 { 1172 struct pci_bus *b; 1173 int i; 1174 struct resource *res, *pr; 1175 1176 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1177 pci_domain_nr(bus), bus->number); 1178 1179 pci_bus_for_each_resource(bus, res, i) { 1180 if (!res || !res->flags || res->start > res->end || res->parent) 1181 continue; 1182 1183 /* If the resource was left unset at this point, we clear it */ 1184 if (res->flags & IORESOURCE_UNSET) 1185 goto clear_resource; 1186 1187 if (bus->parent == NULL) 1188 pr = (res->flags & IORESOURCE_IO) ? 1189 &ioport_resource : &iomem_resource; 1190 else { 1191 pr = pci_find_parent_resource(bus->self, res); 1192 if (pr == res) { 1193 /* this happens when the generic PCI 1194 * code (wrongly) decides that this 1195 * bridge is transparent -- paulus 1196 */ 1197 continue; 1198 } 1199 } 1200 1201 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1202 "[0x%x], parent %p (%s)\n", 1203 bus->self ? pci_name(bus->self) : "PHB", 1204 bus->number, i, 1205 (unsigned long long)res->start, 1206 (unsigned long long)res->end, 1207 (unsigned int)res->flags, 1208 pr, (pr && pr->name) ? pr->name : "nil"); 1209 1210 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1211 struct pci_dev *dev = bus->self; 1212 1213 if (request_resource(pr, res) == 0) 1214 continue; 1215 /* 1216 * Must be a conflict with an existing entry. 1217 * Move that entry (or entries) under the 1218 * bridge resource and try again. 1219 */ 1220 if (reparent_resources(pr, res) == 0) 1221 continue; 1222 1223 if (dev && i < PCI_BRIDGE_RESOURCE_NUM && 1224 pci_claim_bridge_resource(dev, 1225 i + PCI_BRIDGE_RESOURCES) == 0) 1226 continue; 1227 } 1228 pr_warning("PCI: Cannot allocate resource region " 1229 "%d of PCI bridge %d, will remap\n", i, bus->number); 1230 clear_resource: 1231 /* The resource might be figured out when doing 1232 * reassignment based on the resources required 1233 * by the downstream PCI devices. Here we set 1234 * the size of the resource to be 0 in order to 1235 * save more space. 1236 */ 1237 res->start = 0; 1238 res->end = -1; 1239 res->flags = 0; 1240 } 1241 1242 list_for_each_entry(b, &bus->children, node) 1243 pcibios_allocate_bus_resources(b); 1244 } 1245 1246 static inline void alloc_resource(struct pci_dev *dev, int idx) 1247 { 1248 struct resource *pr, *r = &dev->resource[idx]; 1249 1250 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1251 pci_name(dev), idx, 1252 (unsigned long long)r->start, 1253 (unsigned long long)r->end, 1254 (unsigned int)r->flags); 1255 1256 pr = pci_find_parent_resource(dev, r); 1257 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1258 request_resource(pr, r) < 0) { 1259 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1260 " of device %s, will remap\n", idx, pci_name(dev)); 1261 if (pr) 1262 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1263 pr, 1264 (unsigned long long)pr->start, 1265 (unsigned long long)pr->end, 1266 (unsigned int)pr->flags); 1267 /* We'll assign a new address later */ 1268 r->flags |= IORESOURCE_UNSET; 1269 r->end -= r->start; 1270 r->start = 0; 1271 } 1272 } 1273 1274 static void __init pcibios_allocate_resources(int pass) 1275 { 1276 struct pci_dev *dev = NULL; 1277 int idx, disabled; 1278 u16 command; 1279 struct resource *r; 1280 1281 for_each_pci_dev(dev) { 1282 pci_read_config_word(dev, PCI_COMMAND, &command); 1283 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1284 r = &dev->resource[idx]; 1285 if (r->parent) /* Already allocated */ 1286 continue; 1287 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1288 continue; /* Not assigned at all */ 1289 /* We only allocate ROMs on pass 1 just in case they 1290 * have been screwed up by firmware 1291 */ 1292 if (idx == PCI_ROM_RESOURCE ) 1293 disabled = 1; 1294 if (r->flags & IORESOURCE_IO) 1295 disabled = !(command & PCI_COMMAND_IO); 1296 else 1297 disabled = !(command & PCI_COMMAND_MEMORY); 1298 if (pass == disabled) 1299 alloc_resource(dev, idx); 1300 } 1301 if (pass) 1302 continue; 1303 r = &dev->resource[PCI_ROM_RESOURCE]; 1304 if (r->flags) { 1305 /* Turn the ROM off, leave the resource region, 1306 * but keep it unregistered. 1307 */ 1308 u32 reg; 1309 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1310 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1311 pr_debug("PCI: Switching off ROM of %s\n", 1312 pci_name(dev)); 1313 r->flags &= ~IORESOURCE_ROM_ENABLE; 1314 pci_write_config_dword(dev, dev->rom_base_reg, 1315 reg & ~PCI_ROM_ADDRESS_ENABLE); 1316 } 1317 } 1318 } 1319 } 1320 1321 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1322 { 1323 struct pci_controller *hose = pci_bus_to_host(bus); 1324 resource_size_t offset; 1325 struct resource *res, *pres; 1326 int i; 1327 1328 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1329 1330 /* Check for IO */ 1331 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1332 goto no_io; 1333 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1334 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1335 BUG_ON(res == NULL); 1336 res->name = "Legacy IO"; 1337 res->flags = IORESOURCE_IO; 1338 res->start = offset; 1339 res->end = (offset + 0xfff) & 0xfffffffful; 1340 pr_debug("Candidate legacy IO: %pR\n", res); 1341 if (request_resource(&hose->io_resource, res)) { 1342 printk(KERN_DEBUG 1343 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1344 pci_domain_nr(bus), bus->number, res); 1345 kfree(res); 1346 } 1347 1348 no_io: 1349 /* Check for memory */ 1350 for (i = 0; i < 3; i++) { 1351 pres = &hose->mem_resources[i]; 1352 offset = hose->mem_offset[i]; 1353 if (!(pres->flags & IORESOURCE_MEM)) 1354 continue; 1355 pr_debug("hose mem res: %pR\n", pres); 1356 if ((pres->start - offset) <= 0xa0000 && 1357 (pres->end - offset) >= 0xbffff) 1358 break; 1359 } 1360 if (i >= 3) 1361 return; 1362 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1363 BUG_ON(res == NULL); 1364 res->name = "Legacy VGA memory"; 1365 res->flags = IORESOURCE_MEM; 1366 res->start = 0xa0000 + offset; 1367 res->end = 0xbffff + offset; 1368 pr_debug("Candidate VGA memory: %pR\n", res); 1369 if (request_resource(pres, res)) { 1370 printk(KERN_DEBUG 1371 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1372 pci_domain_nr(bus), bus->number, res); 1373 kfree(res); 1374 } 1375 } 1376 1377 void __init pcibios_resource_survey(void) 1378 { 1379 struct pci_bus *b; 1380 1381 /* Allocate and assign resources */ 1382 list_for_each_entry(b, &pci_root_buses, node) 1383 pcibios_allocate_bus_resources(b); 1384 pcibios_allocate_resources(0); 1385 pcibios_allocate_resources(1); 1386 1387 /* Before we start assigning unassigned resource, we try to reserve 1388 * the low IO area and the VGA memory area if they intersect the 1389 * bus available resources to avoid allocating things on top of them 1390 */ 1391 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1392 list_for_each_entry(b, &pci_root_buses, node) 1393 pcibios_reserve_legacy_regions(b); 1394 } 1395 1396 /* Now, if the platform didn't decide to blindly trust the firmware, 1397 * we proceed to assigning things that were left unassigned 1398 */ 1399 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1400 pr_debug("PCI: Assigning unassigned resources...\n"); 1401 pci_assign_unassigned_resources(); 1402 } 1403 1404 /* Call machine dependent fixup */ 1405 if (ppc_md.pcibios_fixup) 1406 ppc_md.pcibios_fixup(); 1407 } 1408 1409 /* This is used by the PCI hotplug driver to allocate resource 1410 * of newly plugged busses. We can try to consolidate with the 1411 * rest of the code later, for now, keep it as-is as our main 1412 * resource allocation function doesn't deal with sub-trees yet. 1413 */ 1414 void pcibios_claim_one_bus(struct pci_bus *bus) 1415 { 1416 struct pci_dev *dev; 1417 struct pci_bus *child_bus; 1418 1419 list_for_each_entry(dev, &bus->devices, bus_list) { 1420 int i; 1421 1422 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1423 struct resource *r = &dev->resource[i]; 1424 1425 if (r->parent || !r->start || !r->flags) 1426 continue; 1427 1428 pr_debug("PCI: Claiming %s: " 1429 "Resource %d: %016llx..%016llx [%x]\n", 1430 pci_name(dev), i, 1431 (unsigned long long)r->start, 1432 (unsigned long long)r->end, 1433 (unsigned int)r->flags); 1434 1435 if (pci_claim_resource(dev, i) == 0) 1436 continue; 1437 1438 pci_claim_bridge_resource(dev, i); 1439 } 1440 } 1441 1442 list_for_each_entry(child_bus, &bus->children, node) 1443 pcibios_claim_one_bus(child_bus); 1444 } 1445 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1446 1447 1448 /* pcibios_finish_adding_to_bus 1449 * 1450 * This is to be called by the hotplug code after devices have been 1451 * added to a bus, this include calling it for a PHB that is just 1452 * being added 1453 */ 1454 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1455 { 1456 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1457 pci_domain_nr(bus), bus->number); 1458 1459 /* Allocate bus and devices resources */ 1460 pcibios_allocate_bus_resources(bus); 1461 pcibios_claim_one_bus(bus); 1462 if (!pci_has_flag(PCI_PROBE_ONLY)) 1463 pci_assign_unassigned_bus_resources(bus); 1464 1465 /* Fixup EEH */ 1466 eeh_add_device_tree_late(bus); 1467 1468 /* Add new devices to global lists. Register in proc, sysfs. */ 1469 pci_bus_add_devices(bus); 1470 1471 /* sysfs files should only be added after devices are added */ 1472 eeh_add_sysfs_files(bus); 1473 } 1474 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1475 1476 int pcibios_enable_device(struct pci_dev *dev, int mask) 1477 { 1478 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1479 1480 if (phb->controller_ops.enable_device_hook) 1481 if (!phb->controller_ops.enable_device_hook(dev)) 1482 return -EINVAL; 1483 1484 return pci_enable_resources(dev, mask); 1485 } 1486 1487 void pcibios_disable_device(struct pci_dev *dev) 1488 { 1489 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1490 1491 if (phb->controller_ops.disable_device) 1492 phb->controller_ops.disable_device(dev); 1493 } 1494 1495 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1496 { 1497 return (unsigned long) hose->io_base_virt - _IO_BASE; 1498 } 1499 1500 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1501 struct list_head *resources) 1502 { 1503 struct resource *res; 1504 resource_size_t offset; 1505 int i; 1506 1507 /* Hookup PHB IO resource */ 1508 res = &hose->io_resource; 1509 1510 if (!res->flags) { 1511 pr_info("PCI: I/O resource not set for host" 1512 " bridge %s (domain %d)\n", 1513 hose->dn->full_name, hose->global_number); 1514 } else { 1515 offset = pcibios_io_space_offset(hose); 1516 1517 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n", 1518 (unsigned long long)res->start, 1519 (unsigned long long)res->end, 1520 (unsigned long)res->flags, 1521 (unsigned long long)offset); 1522 pci_add_resource_offset(resources, res, offset); 1523 } 1524 1525 /* Hookup PHB Memory resources */ 1526 for (i = 0; i < 3; ++i) { 1527 res = &hose->mem_resources[i]; 1528 if (!res->flags) { 1529 if (i == 0) 1530 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1531 "host bridge %s (domain %d)\n", 1532 hose->dn->full_name, hose->global_number); 1533 continue; 1534 } 1535 offset = hose->mem_offset[i]; 1536 1537 1538 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i, 1539 (unsigned long long)res->start, 1540 (unsigned long long)res->end, 1541 (unsigned long)res->flags, 1542 (unsigned long long)offset); 1543 1544 pci_add_resource_offset(resources, res, offset); 1545 } 1546 } 1547 1548 /* 1549 * Null PCI config access functions, for the case when we can't 1550 * find a hose. 1551 */ 1552 #define NULL_PCI_OP(rw, size, type) \ 1553 static int \ 1554 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1555 { \ 1556 return PCIBIOS_DEVICE_NOT_FOUND; \ 1557 } 1558 1559 static int 1560 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1561 int len, u32 *val) 1562 { 1563 return PCIBIOS_DEVICE_NOT_FOUND; 1564 } 1565 1566 static int 1567 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1568 int len, u32 val) 1569 { 1570 return PCIBIOS_DEVICE_NOT_FOUND; 1571 } 1572 1573 static struct pci_ops null_pci_ops = 1574 { 1575 .read = null_read_config, 1576 .write = null_write_config, 1577 }; 1578 1579 /* 1580 * These functions are used early on before PCI scanning is done 1581 * and all of the pci_dev and pci_bus structures have been created. 1582 */ 1583 static struct pci_bus * 1584 fake_pci_bus(struct pci_controller *hose, int busnr) 1585 { 1586 static struct pci_bus bus; 1587 1588 if (hose == NULL) { 1589 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1590 } 1591 bus.number = busnr; 1592 bus.sysdata = hose; 1593 bus.ops = hose? hose->ops: &null_pci_ops; 1594 return &bus; 1595 } 1596 1597 #define EARLY_PCI_OP(rw, size, type) \ 1598 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1599 int devfn, int offset, type value) \ 1600 { \ 1601 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1602 devfn, offset, value); \ 1603 } 1604 1605 EARLY_PCI_OP(read, byte, u8 *) 1606 EARLY_PCI_OP(read, word, u16 *) 1607 EARLY_PCI_OP(read, dword, u32 *) 1608 EARLY_PCI_OP(write, byte, u8) 1609 EARLY_PCI_OP(write, word, u16) 1610 EARLY_PCI_OP(write, dword, u32) 1611 1612 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1613 int cap) 1614 { 1615 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1616 } 1617 1618 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1619 { 1620 struct pci_controller *hose = bus->sysdata; 1621 1622 return of_node_get(hose->dn); 1623 } 1624 1625 /** 1626 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1627 * @hose: Pointer to the PCI host controller instance structure 1628 */ 1629 void pcibios_scan_phb(struct pci_controller *hose) 1630 { 1631 LIST_HEAD(resources); 1632 struct pci_bus *bus; 1633 struct device_node *node = hose->dn; 1634 int mode; 1635 1636 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1637 1638 /* Get some IO space for the new PHB */ 1639 pcibios_setup_phb_io_space(hose); 1640 1641 /* Wire up PHB bus resources */ 1642 pcibios_setup_phb_resources(hose, &resources); 1643 1644 hose->busn.start = hose->first_busno; 1645 hose->busn.end = hose->last_busno; 1646 hose->busn.flags = IORESOURCE_BUS; 1647 pci_add_resource(&resources, &hose->busn); 1648 1649 /* Create an empty bus for the toplevel */ 1650 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1651 hose->ops, hose, &resources); 1652 if (bus == NULL) { 1653 pr_err("Failed to create bus for PCI domain %04x\n", 1654 hose->global_number); 1655 pci_free_resource_list(&resources); 1656 return; 1657 } 1658 hose->bus = bus; 1659 1660 /* Get probe mode and perform scan */ 1661 mode = PCI_PROBE_NORMAL; 1662 if (node && hose->controller_ops.probe_mode) 1663 mode = hose->controller_ops.probe_mode(bus); 1664 pr_debug(" probe mode: %d\n", mode); 1665 if (mode == PCI_PROBE_DEVTREE) 1666 of_scan_bus(node, bus); 1667 1668 if (mode == PCI_PROBE_NORMAL) { 1669 pci_bus_update_busn_res_end(bus, 255); 1670 hose->last_busno = pci_scan_child_bus(bus); 1671 pci_bus_update_busn_res_end(bus, hose->last_busno); 1672 } 1673 1674 /* Platform gets a chance to do some global fixups before 1675 * we proceed to resource allocation 1676 */ 1677 if (ppc_md.pcibios_fixup_phb) 1678 ppc_md.pcibios_fixup_phb(hose); 1679 1680 /* Configure PCI Express settings */ 1681 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1682 struct pci_bus *child; 1683 list_for_each_entry(child, &bus->children, node) 1684 pcie_bus_configure_settings(child); 1685 } 1686 } 1687 EXPORT_SYMBOL_GPL(pcibios_scan_phb); 1688 1689 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1690 { 1691 int i, class = dev->class >> 8; 1692 /* When configured as agent, programing interface = 1 */ 1693 int prog_if = dev->class & 0xf; 1694 1695 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1696 class == PCI_CLASS_BRIDGE_OTHER) && 1697 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1698 (prog_if == 0) && 1699 (dev->bus->parent == NULL)) { 1700 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1701 dev->resource[i].start = 0; 1702 dev->resource[i].end = 0; 1703 dev->resource[i].flags = 0; 1704 } 1705 } 1706 } 1707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1709 1710 static void fixup_vga(struct pci_dev *pdev) 1711 { 1712 u16 cmd; 1713 1714 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1715 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) 1716 vga_set_default_device(pdev); 1717 1718 } 1719 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1720 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); 1721