1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #undef DEBUG 20 21 #include <linux/kernel.h> 22 #include <linux/pci.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 #include <linux/mm.h> 27 #include <linux/list.h> 28 #include <linux/syscalls.h> 29 #include <linux/irq.h> 30 #include <linux/vmalloc.h> 31 32 #include <asm/processor.h> 33 #include <asm/io.h> 34 #include <asm/prom.h> 35 #include <asm/pci-bridge.h> 36 #include <asm/byteorder.h> 37 #include <asm/machdep.h> 38 #include <asm/ppc-pci.h> 39 #include <asm/firmware.h> 40 41 #ifdef DEBUG 42 #include <asm/udbg.h> 43 #define DBG(fmt...) printk(fmt) 44 #else 45 #define DBG(fmt...) 46 #endif 47 48 static DEFINE_SPINLOCK(hose_spinlock); 49 50 /* XXX kill that some day ... */ 51 static int global_phb_number; /* Global phb counter */ 52 53 /* ISA Memory physical address */ 54 resource_size_t isa_mem_base; 55 56 /* Default PCI flags is 0 */ 57 unsigned int ppc_pci_flags; 58 59 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 60 { 61 struct pci_controller *phb; 62 63 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 64 if (phb == NULL) 65 return NULL; 66 spin_lock(&hose_spinlock); 67 phb->global_number = global_phb_number++; 68 list_add_tail(&phb->list_node, &hose_list); 69 spin_unlock(&hose_spinlock); 70 phb->dn = dev; 71 phb->is_dynamic = mem_init_done; 72 #ifdef CONFIG_PPC64 73 if (dev) { 74 int nid = of_node_to_nid(dev); 75 76 if (nid < 0 || !node_online(nid)) 77 nid = -1; 78 79 PHB_SET_NODE(phb, nid); 80 } 81 #endif 82 return phb; 83 } 84 85 void pcibios_free_controller(struct pci_controller *phb) 86 { 87 spin_lock(&hose_spinlock); 88 list_del(&phb->list_node); 89 spin_unlock(&hose_spinlock); 90 91 if (phb->is_dynamic) 92 kfree(phb); 93 } 94 95 int pcibios_vaddr_is_ioport(void __iomem *address) 96 { 97 int ret = 0; 98 struct pci_controller *hose; 99 unsigned long size; 100 101 spin_lock(&hose_spinlock); 102 list_for_each_entry(hose, &hose_list, list_node) { 103 #ifdef CONFIG_PPC64 104 size = hose->pci_io_size; 105 #else 106 size = hose->io_resource.end - hose->io_resource.start + 1; 107 #endif 108 if (address >= hose->io_base_virt && 109 address < (hose->io_base_virt + size)) { 110 ret = 1; 111 break; 112 } 113 } 114 spin_unlock(&hose_spinlock); 115 return ret; 116 } 117 118 /* 119 * Return the domain number for this bus. 120 */ 121 int pci_domain_nr(struct pci_bus *bus) 122 { 123 struct pci_controller *hose = pci_bus_to_host(bus); 124 125 return hose->global_number; 126 } 127 EXPORT_SYMBOL(pci_domain_nr); 128 129 #ifdef CONFIG_PPC_OF 130 131 /* This routine is meant to be used early during boot, when the 132 * PCI bus numbers have not yet been assigned, and you need to 133 * issue PCI config cycles to an OF device. 134 * It could also be used to "fix" RTAS config cycles if you want 135 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 136 * config cycles. 137 */ 138 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 139 { 140 if (!have_of) 141 return NULL; 142 while(node) { 143 struct pci_controller *hose, *tmp; 144 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 145 if (hose->dn == node) 146 return hose; 147 node = node->parent; 148 } 149 return NULL; 150 } 151 152 static ssize_t pci_show_devspec(struct device *dev, 153 struct device_attribute *attr, char *buf) 154 { 155 struct pci_dev *pdev; 156 struct device_node *np; 157 158 pdev = to_pci_dev (dev); 159 np = pci_device_to_OF_node(pdev); 160 if (np == NULL || np->full_name == NULL) 161 return 0; 162 return sprintf(buf, "%s", np->full_name); 163 } 164 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 165 #endif /* CONFIG_PPC_OF */ 166 167 /* Add sysfs properties */ 168 int pcibios_add_platform_entries(struct pci_dev *pdev) 169 { 170 #ifdef CONFIG_PPC_OF 171 return device_create_file(&pdev->dev, &dev_attr_devspec); 172 #else 173 return 0; 174 #endif /* CONFIG_PPC_OF */ 175 176 } 177 178 char __devinit *pcibios_setup(char *str) 179 { 180 return str; 181 } 182 183 /* 184 * Reads the interrupt pin to determine if interrupt is use by card. 185 * If the interrupt is used, then gets the interrupt line from the 186 * openfirmware and sets it in the pci_dev and pci_config line. 187 */ 188 int pci_read_irq_line(struct pci_dev *pci_dev) 189 { 190 struct of_irq oirq; 191 unsigned int virq; 192 193 /* The current device-tree that iSeries generates from the HV 194 * PCI informations doesn't contain proper interrupt routing, 195 * and all the fallback would do is print out crap, so we 196 * don't attempt to resolve the interrupts here at all, some 197 * iSeries specific fixup does it. 198 * 199 * In the long run, we will hopefully fix the generated device-tree 200 * instead. 201 */ 202 #ifdef CONFIG_PPC_ISERIES 203 if (firmware_has_feature(FW_FEATURE_ISERIES)) 204 return -1; 205 #endif 206 207 DBG("Try to map irq for %s...\n", pci_name(pci_dev)); 208 209 #ifdef DEBUG 210 memset(&oirq, 0xff, sizeof(oirq)); 211 #endif 212 /* Try to get a mapping from the device-tree */ 213 if (of_irq_map_pci(pci_dev, &oirq)) { 214 u8 line, pin; 215 216 /* If that fails, lets fallback to what is in the config 217 * space and map that through the default controller. We 218 * also set the type to level low since that's what PCI 219 * interrupts are. If your platform does differently, then 220 * either provide a proper interrupt tree or don't use this 221 * function. 222 */ 223 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 224 return -1; 225 if (pin == 0) 226 return -1; 227 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 228 line == 0xff || line == 0) { 229 return -1; 230 } 231 DBG(" -> no map ! Using line %d (pin %d) from PCI config\n", 232 line, pin); 233 234 virq = irq_create_mapping(NULL, line); 235 if (virq != NO_IRQ) 236 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 237 } else { 238 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 239 oirq.size, oirq.specifier[0], oirq.specifier[1], 240 oirq.controller->full_name); 241 242 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 243 oirq.size); 244 } 245 if(virq == NO_IRQ) { 246 DBG(" -> failed to map !\n"); 247 return -1; 248 } 249 250 DBG(" -> mapped to linux irq %d\n", virq); 251 252 pci_dev->irq = virq; 253 254 return 0; 255 } 256 EXPORT_SYMBOL(pci_read_irq_line); 257 258 /* 259 * Platform support for /proc/bus/pci/X/Y mmap()s, 260 * modelled on the sparc64 implementation by Dave Miller. 261 * -- paulus. 262 */ 263 264 /* 265 * Adjust vm_pgoff of VMA such that it is the physical page offset 266 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 267 * 268 * Basically, the user finds the base address for his device which he wishes 269 * to mmap. They read the 32-bit value from the config space base register, 270 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 271 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 272 * 273 * Returns negative error code on failure, zero on success. 274 */ 275 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 276 resource_size_t *offset, 277 enum pci_mmap_state mmap_state) 278 { 279 struct pci_controller *hose = pci_bus_to_host(dev->bus); 280 unsigned long io_offset = 0; 281 int i, res_bit; 282 283 if (hose == 0) 284 return NULL; /* should never happen */ 285 286 /* If memory, add on the PCI bridge address offset */ 287 if (mmap_state == pci_mmap_mem) { 288 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 289 *offset += hose->pci_mem_offset; 290 #endif 291 res_bit = IORESOURCE_MEM; 292 } else { 293 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 294 *offset += io_offset; 295 res_bit = IORESOURCE_IO; 296 } 297 298 /* 299 * Check that the offset requested corresponds to one of the 300 * resources of the device. 301 */ 302 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 303 struct resource *rp = &dev->resource[i]; 304 int flags = rp->flags; 305 306 /* treat ROM as memory (should be already) */ 307 if (i == PCI_ROM_RESOURCE) 308 flags |= IORESOURCE_MEM; 309 310 /* Active and same type? */ 311 if ((flags & res_bit) == 0) 312 continue; 313 314 /* In the range of this resource? */ 315 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 316 continue; 317 318 /* found it! construct the final physical address */ 319 if (mmap_state == pci_mmap_io) 320 *offset += hose->io_base_phys - io_offset; 321 return rp; 322 } 323 324 return NULL; 325 } 326 327 /* 328 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 329 * device mapping. 330 */ 331 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 332 pgprot_t protection, 333 enum pci_mmap_state mmap_state, 334 int write_combine) 335 { 336 unsigned long prot = pgprot_val(protection); 337 338 /* Write combine is always 0 on non-memory space mappings. On 339 * memory space, if the user didn't pass 1, we check for a 340 * "prefetchable" resource. This is a bit hackish, but we use 341 * this to workaround the inability of /sysfs to provide a write 342 * combine bit 343 */ 344 if (mmap_state != pci_mmap_mem) 345 write_combine = 0; 346 else if (write_combine == 0) { 347 if (rp->flags & IORESOURCE_PREFETCH) 348 write_combine = 1; 349 } 350 351 /* XXX would be nice to have a way to ask for write-through */ 352 prot |= _PAGE_NO_CACHE; 353 if (write_combine) 354 prot &= ~_PAGE_GUARDED; 355 else 356 prot |= _PAGE_GUARDED; 357 358 return __pgprot(prot); 359 } 360 361 /* 362 * This one is used by /dev/mem and fbdev who have no clue about the 363 * PCI device, it tries to find the PCI device first and calls the 364 * above routine 365 */ 366 pgprot_t pci_phys_mem_access_prot(struct file *file, 367 unsigned long pfn, 368 unsigned long size, 369 pgprot_t protection) 370 { 371 struct pci_dev *pdev = NULL; 372 struct resource *found = NULL; 373 unsigned long prot = pgprot_val(protection); 374 unsigned long offset = pfn << PAGE_SHIFT; 375 int i; 376 377 if (page_is_ram(pfn)) 378 return __pgprot(prot); 379 380 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; 381 382 for_each_pci_dev(pdev) { 383 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 384 struct resource *rp = &pdev->resource[i]; 385 int flags = rp->flags; 386 387 /* Active and same type? */ 388 if ((flags & IORESOURCE_MEM) == 0) 389 continue; 390 /* In the range of this resource? */ 391 if (offset < (rp->start & PAGE_MASK) || 392 offset > rp->end) 393 continue; 394 found = rp; 395 break; 396 } 397 if (found) 398 break; 399 } 400 if (found) { 401 if (found->flags & IORESOURCE_PREFETCH) 402 prot &= ~_PAGE_GUARDED; 403 pci_dev_put(pdev); 404 } 405 406 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); 407 408 return __pgprot(prot); 409 } 410 411 412 /* 413 * Perform the actual remap of the pages for a PCI device mapping, as 414 * appropriate for this architecture. The region in the process to map 415 * is described by vm_start and vm_end members of VMA, the base physical 416 * address is found in vm_pgoff. 417 * The pci device structure is provided so that architectures may make mapping 418 * decisions on a per-device or per-bus basis. 419 * 420 * Returns a negative error code on failure, zero on success. 421 */ 422 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 423 enum pci_mmap_state mmap_state, int write_combine) 424 { 425 resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT; 426 struct resource *rp; 427 int ret; 428 429 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 430 if (rp == NULL) 431 return -EINVAL; 432 433 vma->vm_pgoff = offset >> PAGE_SHIFT; 434 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 435 vma->vm_page_prot, 436 mmap_state, write_combine); 437 438 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 439 vma->vm_end - vma->vm_start, vma->vm_page_prot); 440 441 return ret; 442 } 443 444 void pci_resource_to_user(const struct pci_dev *dev, int bar, 445 const struct resource *rsrc, 446 resource_size_t *start, resource_size_t *end) 447 { 448 struct pci_controller *hose = pci_bus_to_host(dev->bus); 449 resource_size_t offset = 0; 450 451 if (hose == NULL) 452 return; 453 454 if (rsrc->flags & IORESOURCE_IO) 455 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 456 457 /* We pass a fully fixed up address to userland for MMIO instead of 458 * a BAR value because X is lame and expects to be able to use that 459 * to pass to /dev/mem ! 460 * 461 * That means that we'll have potentially 64 bits values where some 462 * userland apps only expect 32 (like X itself since it thinks only 463 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 464 * 32 bits CHRPs :-( 465 * 466 * Hopefully, the sysfs insterface is immune to that gunk. Once X 467 * has been fixed (and the fix spread enough), we can re-enable the 468 * 2 lines below and pass down a BAR value to userland. In that case 469 * we'll also have to re-enable the matching code in 470 * __pci_mmap_make_offset(). 471 * 472 * BenH. 473 */ 474 #if 0 475 else if (rsrc->flags & IORESOURCE_MEM) 476 offset = hose->pci_mem_offset; 477 #endif 478 479 *start = rsrc->start - offset; 480 *end = rsrc->end - offset; 481 } 482 483 /** 484 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 485 * @hose: newly allocated pci_controller to be setup 486 * @dev: device node of the host bridge 487 * @primary: set if primary bus (32 bits only, soon to be deprecated) 488 * 489 * This function will parse the "ranges" property of a PCI host bridge device 490 * node and setup the resource mapping of a pci controller based on its 491 * content. 492 * 493 * Life would be boring if it wasn't for a few issues that we have to deal 494 * with here: 495 * 496 * - We can only cope with one IO space range and up to 3 Memory space 497 * ranges. However, some machines (thanks Apple !) tend to split their 498 * space into lots of small contiguous ranges. So we have to coalesce. 499 * 500 * - We can only cope with all memory ranges having the same offset 501 * between CPU addresses and PCI addresses. Unfortunately, some bridges 502 * are setup for a large 1:1 mapping along with a small "window" which 503 * maps PCI address 0 to some arbitrary high address of the CPU space in 504 * order to give access to the ISA memory hole. 505 * The way out of here that I've chosen for now is to always set the 506 * offset based on the first resource found, then override it if we 507 * have a different offset and the previous was set by an ISA hole. 508 * 509 * - Some busses have IO space not starting at 0, which causes trouble with 510 * the way we do our IO resource renumbering. The code somewhat deals with 511 * it for 64 bits but I would expect problems on 32 bits. 512 * 513 * - Some 32 bits platforms such as 4xx can have physical space larger than 514 * 32 bits so we need to use 64 bits values for the parsing 515 */ 516 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 517 struct device_node *dev, 518 int primary) 519 { 520 const u32 *ranges; 521 int rlen; 522 int pna = of_n_addr_cells(dev); 523 int np = pna + 5; 524 int memno = 0, isa_hole = -1; 525 u32 pci_space; 526 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 527 unsigned long long isa_mb = 0; 528 struct resource *res; 529 530 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 531 dev->full_name, primary ? "(primary)" : ""); 532 533 /* Get ranges property */ 534 ranges = of_get_property(dev, "ranges", &rlen); 535 if (ranges == NULL) 536 return; 537 538 /* Parse it */ 539 while ((rlen -= np * 4) >= 0) { 540 /* Read next ranges element */ 541 pci_space = ranges[0]; 542 pci_addr = of_read_number(ranges + 1, 2); 543 cpu_addr = of_translate_address(dev, ranges + 3); 544 size = of_read_number(ranges + pna + 3, 2); 545 ranges += np; 546 if (cpu_addr == OF_BAD_ADDR || size == 0) 547 continue; 548 549 /* Now consume following elements while they are contiguous */ 550 for (; rlen >= np * sizeof(u32); 551 ranges += np, rlen -= np * 4) { 552 if (ranges[0] != pci_space) 553 break; 554 pci_next = of_read_number(ranges + 1, 2); 555 cpu_next = of_translate_address(dev, ranges + 3); 556 if (pci_next != pci_addr + size || 557 cpu_next != cpu_addr + size) 558 break; 559 size += of_read_number(ranges + pna + 3, 2); 560 } 561 562 /* Act based on address space type */ 563 res = NULL; 564 switch ((pci_space >> 24) & 0x3) { 565 case 1: /* PCI IO space */ 566 printk(KERN_INFO 567 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 568 cpu_addr, cpu_addr + size - 1, pci_addr); 569 570 /* We support only one IO range */ 571 if (hose->pci_io_size) { 572 printk(KERN_INFO 573 " \\--> Skipped (too many) !\n"); 574 continue; 575 } 576 #ifdef CONFIG_PPC32 577 /* On 32 bits, limit I/O space to 16MB */ 578 if (size > 0x01000000) 579 size = 0x01000000; 580 581 /* 32 bits needs to map IOs here */ 582 hose->io_base_virt = ioremap(cpu_addr, size); 583 584 /* Expect trouble if pci_addr is not 0 */ 585 if (primary) 586 isa_io_base = 587 (unsigned long)hose->io_base_virt; 588 #endif /* CONFIG_PPC32 */ 589 /* pci_io_size and io_base_phys always represent IO 590 * space starting at 0 so we factor in pci_addr 591 */ 592 hose->pci_io_size = pci_addr + size; 593 hose->io_base_phys = cpu_addr - pci_addr; 594 595 /* Build resource */ 596 res = &hose->io_resource; 597 res->flags = IORESOURCE_IO; 598 res->start = pci_addr; 599 break; 600 case 2: /* PCI Memory space */ 601 printk(KERN_INFO 602 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 603 cpu_addr, cpu_addr + size - 1, pci_addr, 604 (pci_space & 0x40000000) ? "Prefetch" : ""); 605 606 /* We support only 3 memory ranges */ 607 if (memno >= 3) { 608 printk(KERN_INFO 609 " \\--> Skipped (too many) !\n"); 610 continue; 611 } 612 /* Handles ISA memory hole space here */ 613 if (pci_addr == 0) { 614 isa_mb = cpu_addr; 615 isa_hole = memno; 616 if (primary || isa_mem_base == 0) 617 isa_mem_base = cpu_addr; 618 } 619 620 /* We get the PCI/Mem offset from the first range or 621 * the, current one if the offset came from an ISA 622 * hole. If they don't match, bugger. 623 */ 624 if (memno == 0 || 625 (isa_hole >= 0 && pci_addr != 0 && 626 hose->pci_mem_offset == isa_mb)) 627 hose->pci_mem_offset = cpu_addr - pci_addr; 628 else if (pci_addr != 0 && 629 hose->pci_mem_offset != cpu_addr - pci_addr) { 630 printk(KERN_INFO 631 " \\--> Skipped (offset mismatch) !\n"); 632 continue; 633 } 634 635 /* Build resource */ 636 res = &hose->mem_resources[memno++]; 637 res->flags = IORESOURCE_MEM; 638 if (pci_space & 0x40000000) 639 res->flags |= IORESOURCE_PREFETCH; 640 res->start = cpu_addr; 641 break; 642 } 643 if (res != NULL) { 644 res->name = dev->full_name; 645 res->end = res->start + size - 1; 646 res->parent = NULL; 647 res->sibling = NULL; 648 res->child = NULL; 649 } 650 } 651 652 /* Out of paranoia, let's put the ISA hole last if any */ 653 if (isa_hole >= 0 && memno > 0 && isa_hole != (memno-1)) { 654 struct resource tmp = hose->mem_resources[isa_hole]; 655 hose->mem_resources[isa_hole] = hose->mem_resources[memno-1]; 656 hose->mem_resources[memno-1] = tmp; 657 } 658 } 659 660 /* Decide whether to display the domain number in /proc */ 661 int pci_proc_domain(struct pci_bus *bus) 662 { 663 struct pci_controller *hose = pci_bus_to_host(bus); 664 #ifdef CONFIG_PPC64 665 return hose->buid != 0; 666 #else 667 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) 668 return 0; 669 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) 670 return hose->global_number != 0; 671 return 1; 672 #endif 673 } 674 675 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 676 struct resource *res) 677 { 678 resource_size_t offset = 0, mask = (resource_size_t)-1; 679 struct pci_controller *hose = pci_bus_to_host(dev->bus); 680 681 if (!hose) 682 return; 683 if (res->flags & IORESOURCE_IO) { 684 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 685 mask = 0xffffffffu; 686 } else if (res->flags & IORESOURCE_MEM) 687 offset = hose->pci_mem_offset; 688 689 region->start = (res->start - offset) & mask; 690 region->end = (res->end - offset) & mask; 691 } 692 EXPORT_SYMBOL(pcibios_resource_to_bus); 693 694 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 695 struct pci_bus_region *region) 696 { 697 resource_size_t offset = 0, mask = (resource_size_t)-1; 698 struct pci_controller *hose = pci_bus_to_host(dev->bus); 699 700 if (!hose) 701 return; 702 if (res->flags & IORESOURCE_IO) { 703 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 704 mask = 0xffffffffu; 705 } else if (res->flags & IORESOURCE_MEM) 706 offset = hose->pci_mem_offset; 707 res->start = (region->start + offset) & mask; 708 res->end = (region->end + offset) & mask; 709 } 710 EXPORT_SYMBOL(pcibios_bus_to_resource); 711 712 /* Fixup a bus resource into a linux resource */ 713 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) 714 { 715 struct pci_controller *hose = pci_bus_to_host(dev->bus); 716 resource_size_t offset = 0, mask = (resource_size_t)-1; 717 718 if (res->flags & IORESOURCE_IO) { 719 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 720 mask = 0xffffffffu; 721 } else if (res->flags & IORESOURCE_MEM) 722 offset = hose->pci_mem_offset; 723 724 res->start = (res->start + offset) & mask; 725 res->end = (res->end + offset) & mask; 726 727 pr_debug("PCI:%s %016llx-%016llx\n", 728 pci_name(dev), 729 (unsigned long long)res->start, 730 (unsigned long long)res->end); 731 } 732 733 734 /* This header fixup will do the resource fixup for all devices as they are 735 * probed, but not for bridge ranges 736 */ 737 static void __devinit pcibios_fixup_resources(struct pci_dev *dev) 738 { 739 struct pci_controller *hose = pci_bus_to_host(dev->bus); 740 int i; 741 742 if (!hose) { 743 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 744 pci_name(dev)); 745 return; 746 } 747 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 748 struct resource *res = dev->resource + i; 749 if (!res->flags) 750 continue; 751 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't 752 * consider 0 as an unassigned BAR value. It's technically 753 * a valid value, but linux doesn't like it... so when we can 754 * re-assign things, we do so, but if we can't, we keep it 755 * around and hope for the best... 756 */ 757 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 758 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 759 pci_name(dev), i, 760 (unsigned long long)res->start, 761 (unsigned long long)res->end, 762 (unsigned int)res->flags); 763 res->end -= res->start; 764 res->start = 0; 765 res->flags |= IORESOURCE_UNSET; 766 continue; 767 } 768 769 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", 770 pci_name(dev), i, 771 (unsigned long long)res->start,\ 772 (unsigned long long)res->end, 773 (unsigned int)res->flags); 774 775 fixup_resource(res, dev); 776 } 777 778 /* Call machine specific resource fixup */ 779 if (ppc_md.pcibios_fixup_resources) 780 ppc_md.pcibios_fixup_resources(dev); 781 } 782 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 783 784 static void __devinit __pcibios_fixup_bus(struct pci_bus *bus) 785 { 786 struct pci_controller *hose = pci_bus_to_host(bus); 787 struct pci_dev *dev = bus->self; 788 789 pr_debug("PCI: Fixup bus %d (%s)\n", bus->number, dev ? pci_name(dev) : "PHB"); 790 791 /* Fixup PCI<->PCI bridges. Host bridges are handled separately, for 792 * now differently between 32 and 64 bits. 793 */ 794 if (dev != NULL) { 795 struct resource *res; 796 int i; 797 798 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 799 if ((res = bus->resource[i]) == NULL) 800 continue; 801 if (!res->flags) 802 continue; 803 if (i >= 3 && bus->self->transparent) 804 continue; 805 /* On PowerMac, Apple leaves bridge windows open over 806 * an inaccessible region of memory space (0...fffff) 807 * which is somewhat bogus, but that's what they think 808 * means disabled... 809 * 810 * We clear those to force them to be reallocated later 811 * 812 * We detect such regions by the fact that the base is 813 * equal to the pci_mem_offset of the host bridge and 814 * their size is smaller than 1M. 815 */ 816 if (res->flags & IORESOURCE_MEM && 817 res->start == hose->pci_mem_offset && 818 res->end < 0x100000) { 819 printk(KERN_INFO 820 "PCI: Closing bogus Apple Firmware" 821 " region %d on bus 0x%02x\n", 822 i, bus->number); 823 res->flags = 0; 824 continue; 825 } 826 827 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", 828 pci_name(dev), i, 829 (unsigned long long)res->start,\ 830 (unsigned long long)res->end, 831 (unsigned int)res->flags); 832 833 fixup_resource(res, dev); 834 } 835 } 836 837 /* Additional setup that is different between 32 and 64 bits for now */ 838 pcibios_do_bus_setup(bus); 839 840 /* Platform specific bus fixups */ 841 if (ppc_md.pcibios_fixup_bus) 842 ppc_md.pcibios_fixup_bus(bus); 843 844 /* Read default IRQs and fixup if necessary */ 845 list_for_each_entry(dev, &bus->devices, bus_list) { 846 pci_read_irq_line(dev); 847 if (ppc_md.pci_irq_fixup) 848 ppc_md.pci_irq_fixup(dev); 849 } 850 } 851 852 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 853 { 854 /* When called from the generic PCI probe, read PCI<->PCI bridge 855 * bases before proceeding 856 */ 857 if (bus->self != NULL) 858 pci_read_bridge_bases(bus); 859 __pcibios_fixup_bus(bus); 860 } 861 EXPORT_SYMBOL(pcibios_fixup_bus); 862 863 /* When building a bus from the OF tree rather than probing, we need a 864 * slightly different version of the fixup which doesn't read the 865 * bridge bases using config space accesses 866 */ 867 void __devinit pcibios_fixup_of_probed_bus(struct pci_bus *bus) 868 { 869 __pcibios_fixup_bus(bus); 870 } 871 872 static int skip_isa_ioresource_align(struct pci_dev *dev) 873 { 874 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && 875 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 876 return 1; 877 return 0; 878 } 879 880 /* 881 * We need to avoid collisions with `mirrored' VGA ports 882 * and other strange ISA hardware, so we always want the 883 * addresses to be allocated in the 0x000-0x0ff region 884 * modulo 0x400. 885 * 886 * Why? Because some silly external IO cards only decode 887 * the low 10 bits of the IO address. The 0x00-0xff region 888 * is reserved for motherboard devices that decode all 16 889 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 890 * but we want to try to avoid allocating at 0x2900-0x2bff 891 * which might have be mirrored at 0x0100-0x03ff.. 892 */ 893 void pcibios_align_resource(void *data, struct resource *res, 894 resource_size_t size, resource_size_t align) 895 { 896 struct pci_dev *dev = data; 897 898 if (res->flags & IORESOURCE_IO) { 899 resource_size_t start = res->start; 900 901 if (skip_isa_ioresource_align(dev)) 902 return; 903 if (start & 0x300) { 904 start = (start + 0x3ff) & ~0x3ff; 905 res->start = start; 906 } 907 } 908 } 909 EXPORT_SYMBOL(pcibios_align_resource); 910 911 /* 912 * Reparent resource children of pr that conflict with res 913 * under res, and make res replace those children. 914 */ 915 static int __init reparent_resources(struct resource *parent, 916 struct resource *res) 917 { 918 struct resource *p, **pp; 919 struct resource **firstpp = NULL; 920 921 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 922 if (p->end < res->start) 923 continue; 924 if (res->end < p->start) 925 break; 926 if (p->start < res->start || p->end > res->end) 927 return -1; /* not completely contained */ 928 if (firstpp == NULL) 929 firstpp = pp; 930 } 931 if (firstpp == NULL) 932 return -1; /* didn't find any conflicting entries? */ 933 res->parent = parent; 934 res->child = *firstpp; 935 res->sibling = *pp; 936 *firstpp = res; 937 *pp = NULL; 938 for (p = res->child; p != NULL; p = p->sibling) { 939 p->parent = res; 940 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", 941 p->name, 942 (unsigned long long)p->start, 943 (unsigned long long)p->end, res->name); 944 } 945 return 0; 946 } 947 948 /* 949 * Handle resources of PCI devices. If the world were perfect, we could 950 * just allocate all the resource regions and do nothing more. It isn't. 951 * On the other hand, we cannot just re-allocate all devices, as it would 952 * require us to know lots of host bridge internals. So we attempt to 953 * keep as much of the original configuration as possible, but tweak it 954 * when it's found to be wrong. 955 * 956 * Known BIOS problems we have to work around: 957 * - I/O or memory regions not configured 958 * - regions configured, but not enabled in the command register 959 * - bogus I/O addresses above 64K used 960 * - expansion ROMs left enabled (this may sound harmless, but given 961 * the fact the PCI specs explicitly allow address decoders to be 962 * shared between expansion ROMs and other resource regions, it's 963 * at least dangerous) 964 * 965 * Our solution: 966 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 967 * This gives us fixed barriers on where we can allocate. 968 * (2) Allocate resources for all enabled devices. If there is 969 * a collision, just mark the resource as unallocated. Also 970 * disable expansion ROMs during this step. 971 * (3) Try to allocate resources for disabled devices. If the 972 * resources were assigned correctly, everything goes well, 973 * if they weren't, they won't disturb allocation of other 974 * resources. 975 * (4) Assign new addresses to resources which were either 976 * not configured at all or misconfigured. If explicitly 977 * requested by the user, configure expansion ROM address 978 * as well. 979 */ 980 981 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 982 { 983 struct pci_bus *bus; 984 int i; 985 struct resource *res, *pr; 986 987 /* Depth-First Search on bus tree */ 988 list_for_each_entry(bus, bus_list, node) { 989 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { 990 if ((res = bus->resource[i]) == NULL || !res->flags 991 || res->start > res->end) 992 continue; 993 if (bus->parent == NULL) 994 pr = (res->flags & IORESOURCE_IO) ? 995 &ioport_resource : &iomem_resource; 996 else { 997 /* Don't bother with non-root busses when 998 * re-assigning all resources. We clear the 999 * resource flags as if they were colliding 1000 * and as such ensure proper re-allocation 1001 * later. 1002 */ 1003 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) 1004 goto clear_resource; 1005 pr = pci_find_parent_resource(bus->self, res); 1006 if (pr == res) { 1007 /* this happens when the generic PCI 1008 * code (wrongly) decides that this 1009 * bridge is transparent -- paulus 1010 */ 1011 continue; 1012 } 1013 } 1014 1015 DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1016 "[0x%x], parent %p (%s)\n", 1017 bus->self ? pci_name(bus->self) : "PHB", 1018 bus->number, i, 1019 (unsigned long long)res->start, 1020 (unsigned long long)res->end, 1021 (unsigned int)res->flags, 1022 pr, (pr && pr->name) ? pr->name : "nil"); 1023 1024 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1025 if (request_resource(pr, res) == 0) 1026 continue; 1027 /* 1028 * Must be a conflict with an existing entry. 1029 * Move that entry (or entries) under the 1030 * bridge resource and try again. 1031 */ 1032 if (reparent_resources(pr, res) == 0) 1033 continue; 1034 } 1035 printk(KERN_WARNING 1036 "PCI: Cannot allocate resource region " 1037 "%d of PCI bridge %d, will remap\n", 1038 i, bus->number); 1039 clear_resource: 1040 res->flags = 0; 1041 } 1042 pcibios_allocate_bus_resources(&bus->children); 1043 } 1044 } 1045 1046 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) 1047 { 1048 struct resource *pr, *r = &dev->resource[idx]; 1049 1050 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1051 pci_name(dev), idx, 1052 (unsigned long long)r->start, 1053 (unsigned long long)r->end, 1054 (unsigned int)r->flags); 1055 1056 pr = pci_find_parent_resource(dev, r); 1057 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1058 request_resource(pr, r) < 0) { 1059 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1060 " of device %s, will remap\n", idx, pci_name(dev)); 1061 if (pr) 1062 DBG("PCI: parent is %p: %016llx-%016llx [%x]\n", pr, 1063 (unsigned long long)pr->start, 1064 (unsigned long long)pr->end, 1065 (unsigned int)pr->flags); 1066 /* We'll assign a new address later */ 1067 r->flags |= IORESOURCE_UNSET; 1068 r->end -= r->start; 1069 r->start = 0; 1070 } 1071 } 1072 1073 static void __init pcibios_allocate_resources(int pass) 1074 { 1075 struct pci_dev *dev = NULL; 1076 int idx, disabled; 1077 u16 command; 1078 struct resource *r; 1079 1080 for_each_pci_dev(dev) { 1081 pci_read_config_word(dev, PCI_COMMAND, &command); 1082 for (idx = 0; idx < 6; idx++) { 1083 r = &dev->resource[idx]; 1084 if (r->parent) /* Already allocated */ 1085 continue; 1086 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1087 continue; /* Not assigned at all */ 1088 if (r->flags & IORESOURCE_IO) 1089 disabled = !(command & PCI_COMMAND_IO); 1090 else 1091 disabled = !(command & PCI_COMMAND_MEMORY); 1092 if (pass == disabled) 1093 alloc_resource(dev, idx); 1094 } 1095 if (pass) 1096 continue; 1097 r = &dev->resource[PCI_ROM_RESOURCE]; 1098 if (r->flags & IORESOURCE_ROM_ENABLE) { 1099 /* Turn the ROM off, leave the resource region, 1100 * but keep it unregistered. 1101 */ 1102 u32 reg; 1103 DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); 1104 r->flags &= ~IORESOURCE_ROM_ENABLE; 1105 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1106 pci_write_config_dword(dev, dev->rom_base_reg, 1107 reg & ~PCI_ROM_ADDRESS_ENABLE); 1108 } 1109 } 1110 } 1111 1112 void __init pcibios_resource_survey(void) 1113 { 1114 /* Allocate and assign resources. If we re-assign everything, then 1115 * we skip the allocate phase 1116 */ 1117 pcibios_allocate_bus_resources(&pci_root_buses); 1118 1119 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { 1120 pcibios_allocate_resources(0); 1121 pcibios_allocate_resources(1); 1122 } 1123 1124 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1125 DBG("PCI: Assigning unassigned resouces...\n"); 1126 pci_assign_unassigned_resources(); 1127 } 1128 1129 /* Call machine dependent fixup */ 1130 if (ppc_md.pcibios_fixup) 1131 ppc_md.pcibios_fixup(); 1132 } 1133 1134 #ifdef CONFIG_HOTPLUG 1135 /* This is used by the pSeries hotplug driver to allocate resource 1136 * of newly plugged busses. We can try to consolidate with the 1137 * rest of the code later, for now, keep it as-is 1138 */ 1139 void __devinit pcibios_claim_one_bus(struct pci_bus *bus) 1140 { 1141 struct pci_dev *dev; 1142 struct pci_bus *child_bus; 1143 1144 list_for_each_entry(dev, &bus->devices, bus_list) { 1145 int i; 1146 1147 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1148 struct resource *r = &dev->resource[i]; 1149 1150 if (r->parent || !r->start || !r->flags) 1151 continue; 1152 pci_claim_resource(dev, i); 1153 } 1154 } 1155 1156 list_for_each_entry(child_bus, &bus->children, node) 1157 pcibios_claim_one_bus(child_bus); 1158 } 1159 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1160 #endif /* CONFIG_HOTPLUG */ 1161 1162 int pcibios_enable_device(struct pci_dev *dev, int mask) 1163 { 1164 if (ppc_md.pcibios_enable_device_hook) 1165 if (ppc_md.pcibios_enable_device_hook(dev)) 1166 return -EINVAL; 1167 1168 return pci_enable_resources(dev, mask); 1169 } 1170