1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/delay.h> 25 #include <linux/export.h> 26 #include <linux/of_address.h> 27 #include <linux/of_pci.h> 28 #include <linux/mm.h> 29 #include <linux/list.h> 30 #include <linux/syscalls.h> 31 #include <linux/irq.h> 32 #include <linux/vmalloc.h> 33 #include <linux/slab.h> 34 #include <linux/vgaarb.h> 35 36 #include <asm/processor.h> 37 #include <asm/io.h> 38 #include <asm/prom.h> 39 #include <asm/pci-bridge.h> 40 #include <asm/byteorder.h> 41 #include <asm/machdep.h> 42 #include <asm/ppc-pci.h> 43 #include <asm/eeh.h> 44 45 static DEFINE_SPINLOCK(hose_spinlock); 46 LIST_HEAD(hose_list); 47 48 /* XXX kill that some day ... */ 49 static int global_phb_number; /* Global phb counter */ 50 51 /* ISA Memory physical address */ 52 resource_size_t isa_mem_base; 53 54 55 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 56 57 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 58 { 59 pci_dma_ops = dma_ops; 60 } 61 62 struct dma_map_ops *get_pci_dma_ops(void) 63 { 64 return pci_dma_ops; 65 } 66 EXPORT_SYMBOL(get_pci_dma_ops); 67 68 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 69 { 70 struct pci_controller *phb; 71 72 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 73 if (phb == NULL) 74 return NULL; 75 spin_lock(&hose_spinlock); 76 phb->global_number = global_phb_number++; 77 list_add_tail(&phb->list_node, &hose_list); 78 spin_unlock(&hose_spinlock); 79 phb->dn = dev; 80 phb->is_dynamic = mem_init_done; 81 #ifdef CONFIG_PPC64 82 if (dev) { 83 int nid = of_node_to_nid(dev); 84 85 if (nid < 0 || !node_online(nid)) 86 nid = -1; 87 88 PHB_SET_NODE(phb, nid); 89 } 90 #endif 91 return phb; 92 } 93 94 void pcibios_free_controller(struct pci_controller *phb) 95 { 96 spin_lock(&hose_spinlock); 97 list_del(&phb->list_node); 98 spin_unlock(&hose_spinlock); 99 100 if (phb->is_dynamic) 101 kfree(phb); 102 } 103 104 /* 105 * The function is used to return the minimal alignment 106 * for memory or I/O windows of the associated P2P bridge. 107 * By default, 4KiB alignment for I/O windows and 1MiB for 108 * memory windows. 109 */ 110 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 111 unsigned long type) 112 { 113 if (ppc_md.pcibios_window_alignment) 114 return ppc_md.pcibios_window_alignment(bus, type); 115 116 /* 117 * PCI core will figure out the default 118 * alignment: 4KiB for I/O and 1MiB for 119 * memory window. 120 */ 121 return 1; 122 } 123 124 void pcibios_reset_secondary_bus(struct pci_dev *dev) 125 { 126 u16 ctrl; 127 128 if (ppc_md.pcibios_reset_secondary_bus) { 129 ppc_md.pcibios_reset_secondary_bus(dev); 130 return; 131 } 132 133 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 134 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 135 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 136 msleep(2); 137 138 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 140 ssleep(1); 141 } 142 143 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 144 { 145 #ifdef CONFIG_PPC64 146 return hose->pci_io_size; 147 #else 148 return resource_size(&hose->io_resource); 149 #endif 150 } 151 152 int pcibios_vaddr_is_ioport(void __iomem *address) 153 { 154 int ret = 0; 155 struct pci_controller *hose; 156 resource_size_t size; 157 158 spin_lock(&hose_spinlock); 159 list_for_each_entry(hose, &hose_list, list_node) { 160 size = pcibios_io_size(hose); 161 if (address >= hose->io_base_virt && 162 address < (hose->io_base_virt + size)) { 163 ret = 1; 164 break; 165 } 166 } 167 spin_unlock(&hose_spinlock); 168 return ret; 169 } 170 171 unsigned long pci_address_to_pio(phys_addr_t address) 172 { 173 struct pci_controller *hose; 174 resource_size_t size; 175 unsigned long ret = ~0; 176 177 spin_lock(&hose_spinlock); 178 list_for_each_entry(hose, &hose_list, list_node) { 179 size = pcibios_io_size(hose); 180 if (address >= hose->io_base_phys && 181 address < (hose->io_base_phys + size)) { 182 unsigned long base = 183 (unsigned long)hose->io_base_virt - _IO_BASE; 184 ret = base + (address - hose->io_base_phys); 185 break; 186 } 187 } 188 spin_unlock(&hose_spinlock); 189 190 return ret; 191 } 192 EXPORT_SYMBOL_GPL(pci_address_to_pio); 193 194 /* 195 * Return the domain number for this bus. 196 */ 197 int pci_domain_nr(struct pci_bus *bus) 198 { 199 struct pci_controller *hose = pci_bus_to_host(bus); 200 201 return hose->global_number; 202 } 203 EXPORT_SYMBOL(pci_domain_nr); 204 205 /* This routine is meant to be used early during boot, when the 206 * PCI bus numbers have not yet been assigned, and you need to 207 * issue PCI config cycles to an OF device. 208 * It could also be used to "fix" RTAS config cycles if you want 209 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 210 * config cycles. 211 */ 212 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 213 { 214 while(node) { 215 struct pci_controller *hose, *tmp; 216 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 217 if (hose->dn == node) 218 return hose; 219 node = node->parent; 220 } 221 return NULL; 222 } 223 224 /* 225 * Reads the interrupt pin to determine if interrupt is use by card. 226 * If the interrupt is used, then gets the interrupt line from the 227 * openfirmware and sets it in the pci_dev and pci_config line. 228 */ 229 static int pci_read_irq_line(struct pci_dev *pci_dev) 230 { 231 struct of_phandle_args oirq; 232 unsigned int virq; 233 234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 235 236 #ifdef DEBUG 237 memset(&oirq, 0xff, sizeof(oirq)); 238 #endif 239 /* Try to get a mapping from the device-tree */ 240 if (of_irq_parse_pci(pci_dev, &oirq)) { 241 u8 line, pin; 242 243 /* If that fails, lets fallback to what is in the config 244 * space and map that through the default controller. We 245 * also set the type to level low since that's what PCI 246 * interrupts are. If your platform does differently, then 247 * either provide a proper interrupt tree or don't use this 248 * function. 249 */ 250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 251 return -1; 252 if (pin == 0) 253 return -1; 254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 255 line == 0xff || line == 0) { 256 return -1; 257 } 258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 259 line, pin); 260 261 virq = irq_create_mapping(NULL, line); 262 if (virq != NO_IRQ) 263 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 264 } else { 265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 266 oirq.args_count, oirq.args[0], oirq.args[1], 267 of_node_full_name(oirq.np)); 268 269 virq = irq_create_of_mapping(&oirq); 270 } 271 if(virq == NO_IRQ) { 272 pr_debug(" Failed to map !\n"); 273 return -1; 274 } 275 276 pr_debug(" Mapped to linux irq %d\n", virq); 277 278 pci_dev->irq = virq; 279 280 return 0; 281 } 282 283 /* 284 * Platform support for /proc/bus/pci/X/Y mmap()s, 285 * modelled on the sparc64 implementation by Dave Miller. 286 * -- paulus. 287 */ 288 289 /* 290 * Adjust vm_pgoff of VMA such that it is the physical page offset 291 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 292 * 293 * Basically, the user finds the base address for his device which he wishes 294 * to mmap. They read the 32-bit value from the config space base register, 295 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 296 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 297 * 298 * Returns negative error code on failure, zero on success. 299 */ 300 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 301 resource_size_t *offset, 302 enum pci_mmap_state mmap_state) 303 { 304 struct pci_controller *hose = pci_bus_to_host(dev->bus); 305 unsigned long io_offset = 0; 306 int i, res_bit; 307 308 if (hose == NULL) 309 return NULL; /* should never happen */ 310 311 /* If memory, add on the PCI bridge address offset */ 312 if (mmap_state == pci_mmap_mem) { 313 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 314 *offset += hose->pci_mem_offset; 315 #endif 316 res_bit = IORESOURCE_MEM; 317 } else { 318 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 319 *offset += io_offset; 320 res_bit = IORESOURCE_IO; 321 } 322 323 /* 324 * Check that the offset requested corresponds to one of the 325 * resources of the device. 326 */ 327 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 328 struct resource *rp = &dev->resource[i]; 329 int flags = rp->flags; 330 331 /* treat ROM as memory (should be already) */ 332 if (i == PCI_ROM_RESOURCE) 333 flags |= IORESOURCE_MEM; 334 335 /* Active and same type? */ 336 if ((flags & res_bit) == 0) 337 continue; 338 339 /* In the range of this resource? */ 340 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 341 continue; 342 343 /* found it! construct the final physical address */ 344 if (mmap_state == pci_mmap_io) 345 *offset += hose->io_base_phys - io_offset; 346 return rp; 347 } 348 349 return NULL; 350 } 351 352 /* 353 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 354 * device mapping. 355 */ 356 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 357 pgprot_t protection, 358 enum pci_mmap_state mmap_state, 359 int write_combine) 360 { 361 362 /* Write combine is always 0 on non-memory space mappings. On 363 * memory space, if the user didn't pass 1, we check for a 364 * "prefetchable" resource. This is a bit hackish, but we use 365 * this to workaround the inability of /sysfs to provide a write 366 * combine bit 367 */ 368 if (mmap_state != pci_mmap_mem) 369 write_combine = 0; 370 else if (write_combine == 0) { 371 if (rp->flags & IORESOURCE_PREFETCH) 372 write_combine = 1; 373 } 374 375 /* XXX would be nice to have a way to ask for write-through */ 376 if (write_combine) 377 return pgprot_noncached_wc(protection); 378 else 379 return pgprot_noncached(protection); 380 } 381 382 /* 383 * This one is used by /dev/mem and fbdev who have no clue about the 384 * PCI device, it tries to find the PCI device first and calls the 385 * above routine 386 */ 387 pgprot_t pci_phys_mem_access_prot(struct file *file, 388 unsigned long pfn, 389 unsigned long size, 390 pgprot_t prot) 391 { 392 struct pci_dev *pdev = NULL; 393 struct resource *found = NULL; 394 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 395 int i; 396 397 if (page_is_ram(pfn)) 398 return prot; 399 400 prot = pgprot_noncached(prot); 401 for_each_pci_dev(pdev) { 402 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 403 struct resource *rp = &pdev->resource[i]; 404 int flags = rp->flags; 405 406 /* Active and same type? */ 407 if ((flags & IORESOURCE_MEM) == 0) 408 continue; 409 /* In the range of this resource? */ 410 if (offset < (rp->start & PAGE_MASK) || 411 offset > rp->end) 412 continue; 413 found = rp; 414 break; 415 } 416 if (found) 417 break; 418 } 419 if (found) { 420 if (found->flags & IORESOURCE_PREFETCH) 421 prot = pgprot_noncached_wc(prot); 422 pci_dev_put(pdev); 423 } 424 425 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 426 (unsigned long long)offset, pgprot_val(prot)); 427 428 return prot; 429 } 430 431 432 /* 433 * Perform the actual remap of the pages for a PCI device mapping, as 434 * appropriate for this architecture. The region in the process to map 435 * is described by vm_start and vm_end members of VMA, the base physical 436 * address is found in vm_pgoff. 437 * The pci device structure is provided so that architectures may make mapping 438 * decisions on a per-device or per-bus basis. 439 * 440 * Returns a negative error code on failure, zero on success. 441 */ 442 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 443 enum pci_mmap_state mmap_state, int write_combine) 444 { 445 resource_size_t offset = 446 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 447 struct resource *rp; 448 int ret; 449 450 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 451 if (rp == NULL) 452 return -EINVAL; 453 454 vma->vm_pgoff = offset >> PAGE_SHIFT; 455 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 456 vma->vm_page_prot, 457 mmap_state, write_combine); 458 459 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 460 vma->vm_end - vma->vm_start, vma->vm_page_prot); 461 462 return ret; 463 } 464 465 /* This provides legacy IO read access on a bus */ 466 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 467 { 468 unsigned long offset; 469 struct pci_controller *hose = pci_bus_to_host(bus); 470 struct resource *rp = &hose->io_resource; 471 void __iomem *addr; 472 473 /* Check if port can be supported by that bus. We only check 474 * the ranges of the PHB though, not the bus itself as the rules 475 * for forwarding legacy cycles down bridges are not our problem 476 * here. So if the host bridge supports it, we do it. 477 */ 478 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 479 offset += port; 480 481 if (!(rp->flags & IORESOURCE_IO)) 482 return -ENXIO; 483 if (offset < rp->start || (offset + size) > rp->end) 484 return -ENXIO; 485 addr = hose->io_base_virt + port; 486 487 switch(size) { 488 case 1: 489 *((u8 *)val) = in_8(addr); 490 return 1; 491 case 2: 492 if (port & 1) 493 return -EINVAL; 494 *((u16 *)val) = in_le16(addr); 495 return 2; 496 case 4: 497 if (port & 3) 498 return -EINVAL; 499 *((u32 *)val) = in_le32(addr); 500 return 4; 501 } 502 return -EINVAL; 503 } 504 505 /* This provides legacy IO write access on a bus */ 506 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 507 { 508 unsigned long offset; 509 struct pci_controller *hose = pci_bus_to_host(bus); 510 struct resource *rp = &hose->io_resource; 511 void __iomem *addr; 512 513 /* Check if port can be supported by that bus. We only check 514 * the ranges of the PHB though, not the bus itself as the rules 515 * for forwarding legacy cycles down bridges are not our problem 516 * here. So if the host bridge supports it, we do it. 517 */ 518 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 519 offset += port; 520 521 if (!(rp->flags & IORESOURCE_IO)) 522 return -ENXIO; 523 if (offset < rp->start || (offset + size) > rp->end) 524 return -ENXIO; 525 addr = hose->io_base_virt + port; 526 527 /* WARNING: The generic code is idiotic. It gets passed a pointer 528 * to what can be a 1, 2 or 4 byte quantity and always reads that 529 * as a u32, which means that we have to correct the location of 530 * the data read within those 32 bits for size 1 and 2 531 */ 532 switch(size) { 533 case 1: 534 out_8(addr, val >> 24); 535 return 1; 536 case 2: 537 if (port & 1) 538 return -EINVAL; 539 out_le16(addr, val >> 16); 540 return 2; 541 case 4: 542 if (port & 3) 543 return -EINVAL; 544 out_le32(addr, val); 545 return 4; 546 } 547 return -EINVAL; 548 } 549 550 /* This provides legacy IO or memory mmap access on a bus */ 551 int pci_mmap_legacy_page_range(struct pci_bus *bus, 552 struct vm_area_struct *vma, 553 enum pci_mmap_state mmap_state) 554 { 555 struct pci_controller *hose = pci_bus_to_host(bus); 556 resource_size_t offset = 557 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 558 resource_size_t size = vma->vm_end - vma->vm_start; 559 struct resource *rp; 560 561 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 562 pci_domain_nr(bus), bus->number, 563 mmap_state == pci_mmap_mem ? "MEM" : "IO", 564 (unsigned long long)offset, 565 (unsigned long long)(offset + size - 1)); 566 567 if (mmap_state == pci_mmap_mem) { 568 /* Hack alert ! 569 * 570 * Because X is lame and can fail starting if it gets an error trying 571 * to mmap legacy_mem (instead of just moving on without legacy memory 572 * access) we fake it here by giving it anonymous memory, effectively 573 * behaving just like /dev/zero 574 */ 575 if ((offset + size) > hose->isa_mem_size) { 576 printk(KERN_DEBUG 577 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 578 current->comm, current->pid, pci_domain_nr(bus), bus->number); 579 if (vma->vm_flags & VM_SHARED) 580 return shmem_zero_setup(vma); 581 return 0; 582 } 583 offset += hose->isa_mem_phys; 584 } else { 585 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 586 unsigned long roffset = offset + io_offset; 587 rp = &hose->io_resource; 588 if (!(rp->flags & IORESOURCE_IO)) 589 return -ENXIO; 590 if (roffset < rp->start || (roffset + size) > rp->end) 591 return -ENXIO; 592 offset += hose->io_base_phys; 593 } 594 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 595 596 vma->vm_pgoff = offset >> PAGE_SHIFT; 597 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 598 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 599 vma->vm_end - vma->vm_start, 600 vma->vm_page_prot); 601 } 602 603 void pci_resource_to_user(const struct pci_dev *dev, int bar, 604 const struct resource *rsrc, 605 resource_size_t *start, resource_size_t *end) 606 { 607 struct pci_controller *hose = pci_bus_to_host(dev->bus); 608 resource_size_t offset = 0; 609 610 if (hose == NULL) 611 return; 612 613 if (rsrc->flags & IORESOURCE_IO) 614 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 615 616 /* We pass a fully fixed up address to userland for MMIO instead of 617 * a BAR value because X is lame and expects to be able to use that 618 * to pass to /dev/mem ! 619 * 620 * That means that we'll have potentially 64 bits values where some 621 * userland apps only expect 32 (like X itself since it thinks only 622 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 623 * 32 bits CHRPs :-( 624 * 625 * Hopefully, the sysfs insterface is immune to that gunk. Once X 626 * has been fixed (and the fix spread enough), we can re-enable the 627 * 2 lines below and pass down a BAR value to userland. In that case 628 * we'll also have to re-enable the matching code in 629 * __pci_mmap_make_offset(). 630 * 631 * BenH. 632 */ 633 #if 0 634 else if (rsrc->flags & IORESOURCE_MEM) 635 offset = hose->pci_mem_offset; 636 #endif 637 638 *start = rsrc->start - offset; 639 *end = rsrc->end - offset; 640 } 641 642 /** 643 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 644 * @hose: newly allocated pci_controller to be setup 645 * @dev: device node of the host bridge 646 * @primary: set if primary bus (32 bits only, soon to be deprecated) 647 * 648 * This function will parse the "ranges" property of a PCI host bridge device 649 * node and setup the resource mapping of a pci controller based on its 650 * content. 651 * 652 * Life would be boring if it wasn't for a few issues that we have to deal 653 * with here: 654 * 655 * - We can only cope with one IO space range and up to 3 Memory space 656 * ranges. However, some machines (thanks Apple !) tend to split their 657 * space into lots of small contiguous ranges. So we have to coalesce. 658 * 659 * - Some busses have IO space not starting at 0, which causes trouble with 660 * the way we do our IO resource renumbering. The code somewhat deals with 661 * it for 64 bits but I would expect problems on 32 bits. 662 * 663 * - Some 32 bits platforms such as 4xx can have physical space larger than 664 * 32 bits so we need to use 64 bits values for the parsing 665 */ 666 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 667 struct device_node *dev, int primary) 668 { 669 int memno = 0; 670 struct resource *res; 671 struct of_pci_range range; 672 struct of_pci_range_parser parser; 673 674 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 675 dev->full_name, primary ? "(primary)" : ""); 676 677 /* Check for ranges property */ 678 if (of_pci_range_parser_init(&parser, dev)) 679 return; 680 681 /* Parse it */ 682 for_each_of_pci_range(&parser, &range) { 683 /* If we failed translation or got a zero-sized region 684 * (some FW try to feed us with non sensical zero sized regions 685 * such as power3 which look like some kind of attempt at exposing 686 * the VGA memory hole) 687 */ 688 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 689 continue; 690 691 /* Act based on address space type */ 692 res = NULL; 693 switch (range.flags & IORESOURCE_TYPE_BITS) { 694 case IORESOURCE_IO: 695 printk(KERN_INFO 696 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 697 range.cpu_addr, range.cpu_addr + range.size - 1, 698 range.pci_addr); 699 700 /* We support only one IO range */ 701 if (hose->pci_io_size) { 702 printk(KERN_INFO 703 " \\--> Skipped (too many) !\n"); 704 continue; 705 } 706 #ifdef CONFIG_PPC32 707 /* On 32 bits, limit I/O space to 16MB */ 708 if (range.size > 0x01000000) 709 range.size = 0x01000000; 710 711 /* 32 bits needs to map IOs here */ 712 hose->io_base_virt = ioremap(range.cpu_addr, 713 range.size); 714 715 /* Expect trouble if pci_addr is not 0 */ 716 if (primary) 717 isa_io_base = 718 (unsigned long)hose->io_base_virt; 719 #endif /* CONFIG_PPC32 */ 720 /* pci_io_size and io_base_phys always represent IO 721 * space starting at 0 so we factor in pci_addr 722 */ 723 hose->pci_io_size = range.pci_addr + range.size; 724 hose->io_base_phys = range.cpu_addr - range.pci_addr; 725 726 /* Build resource */ 727 res = &hose->io_resource; 728 range.cpu_addr = range.pci_addr; 729 break; 730 case IORESOURCE_MEM: 731 printk(KERN_INFO 732 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 733 range.cpu_addr, range.cpu_addr + range.size - 1, 734 range.pci_addr, 735 (range.pci_space & 0x40000000) ? 736 "Prefetch" : ""); 737 738 /* We support only 3 memory ranges */ 739 if (memno >= 3) { 740 printk(KERN_INFO 741 " \\--> Skipped (too many) !\n"); 742 continue; 743 } 744 /* Handles ISA memory hole space here */ 745 if (range.pci_addr == 0) { 746 if (primary || isa_mem_base == 0) 747 isa_mem_base = range.cpu_addr; 748 hose->isa_mem_phys = range.cpu_addr; 749 hose->isa_mem_size = range.size; 750 } 751 752 /* Build resource */ 753 hose->mem_offset[memno] = range.cpu_addr - 754 range.pci_addr; 755 res = &hose->mem_resources[memno++]; 756 break; 757 } 758 if (res != NULL) { 759 of_pci_range_to_resource(&range, dev, res); 760 } 761 } 762 } 763 764 /* Decide whether to display the domain number in /proc */ 765 int pci_proc_domain(struct pci_bus *bus) 766 { 767 struct pci_controller *hose = pci_bus_to_host(bus); 768 769 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 770 return 0; 771 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 772 return hose->global_number != 0; 773 return 1; 774 } 775 776 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 777 { 778 if (ppc_md.pcibios_root_bridge_prepare) 779 return ppc_md.pcibios_root_bridge_prepare(bridge); 780 781 return 0; 782 } 783 784 /* This header fixup will do the resource fixup for all devices as they are 785 * probed, but not for bridge ranges 786 */ 787 static void pcibios_fixup_resources(struct pci_dev *dev) 788 { 789 struct pci_controller *hose = pci_bus_to_host(dev->bus); 790 int i; 791 792 if (!hose) { 793 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 794 pci_name(dev)); 795 return; 796 } 797 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 798 struct resource *res = dev->resource + i; 799 struct pci_bus_region reg; 800 if (!res->flags) 801 continue; 802 803 /* If we're going to re-assign everything, we mark all resources 804 * as unset (and 0-base them). In addition, we mark BARs starting 805 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 806 * since in that case, we don't want to re-assign anything 807 */ 808 pcibios_resource_to_bus(dev->bus, ®, res); 809 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 810 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 811 /* Only print message if not re-assigning */ 812 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 813 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 814 "is unassigned\n", 815 pci_name(dev), i, 816 (unsigned long long)res->start, 817 (unsigned long long)res->end, 818 (unsigned int)res->flags); 819 res->end -= res->start; 820 res->start = 0; 821 res->flags |= IORESOURCE_UNSET; 822 continue; 823 } 824 825 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 826 pci_name(dev), i, 827 (unsigned long long)res->start,\ 828 (unsigned long long)res->end, 829 (unsigned int)res->flags); 830 } 831 832 /* Call machine specific resource fixup */ 833 if (ppc_md.pcibios_fixup_resources) 834 ppc_md.pcibios_fixup_resources(dev); 835 } 836 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 837 838 /* This function tries to figure out if a bridge resource has been initialized 839 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 840 * things go more smoothly when it gets it right. It should covers cases such 841 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 842 */ 843 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 844 struct resource *res) 845 { 846 struct pci_controller *hose = pci_bus_to_host(bus); 847 struct pci_dev *dev = bus->self; 848 resource_size_t offset; 849 struct pci_bus_region region; 850 u16 command; 851 int i; 852 853 /* We don't do anything if PCI_PROBE_ONLY is set */ 854 if (pci_has_flag(PCI_PROBE_ONLY)) 855 return 0; 856 857 /* Job is a bit different between memory and IO */ 858 if (res->flags & IORESOURCE_MEM) { 859 pcibios_resource_to_bus(dev->bus, ®ion, res); 860 861 /* If the BAR is non-0 then it's probably been initialized */ 862 if (region.start != 0) 863 return 0; 864 865 /* The BAR is 0, let's check if memory decoding is enabled on 866 * the bridge. If not, we consider it unassigned 867 */ 868 pci_read_config_word(dev, PCI_COMMAND, &command); 869 if ((command & PCI_COMMAND_MEMORY) == 0) 870 return 1; 871 872 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 873 * resources covers that starting address (0 then it's good enough for 874 * us for memory space) 875 */ 876 for (i = 0; i < 3; i++) { 877 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 878 hose->mem_resources[i].start == hose->mem_offset[i]) 879 return 0; 880 } 881 882 /* Well, it starts at 0 and we know it will collide so we may as 883 * well consider it as unassigned. That covers the Apple case. 884 */ 885 return 1; 886 } else { 887 /* If the BAR is non-0, then we consider it assigned */ 888 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 889 if (((res->start - offset) & 0xfffffffful) != 0) 890 return 0; 891 892 /* Here, we are a bit different than memory as typically IO space 893 * starting at low addresses -is- valid. What we do instead if that 894 * we consider as unassigned anything that doesn't have IO enabled 895 * in the PCI command register, and that's it. 896 */ 897 pci_read_config_word(dev, PCI_COMMAND, &command); 898 if (command & PCI_COMMAND_IO) 899 return 0; 900 901 /* It's starting at 0 and IO is disabled in the bridge, consider 902 * it unassigned 903 */ 904 return 1; 905 } 906 } 907 908 /* Fixup resources of a PCI<->PCI bridge */ 909 static void pcibios_fixup_bridge(struct pci_bus *bus) 910 { 911 struct resource *res; 912 int i; 913 914 struct pci_dev *dev = bus->self; 915 916 pci_bus_for_each_resource(bus, res, i) { 917 if (!res || !res->flags) 918 continue; 919 if (i >= 3 && bus->self->transparent) 920 continue; 921 922 /* If we're going to reassign everything, we can 923 * shrink the P2P resource to have size as being 924 * of 0 in order to save space. 925 */ 926 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 927 res->flags |= IORESOURCE_UNSET; 928 res->start = 0; 929 res->end = -1; 930 continue; 931 } 932 933 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 934 pci_name(dev), i, 935 (unsigned long long)res->start,\ 936 (unsigned long long)res->end, 937 (unsigned int)res->flags); 938 939 /* Try to detect uninitialized P2P bridge resources, 940 * and clear them out so they get re-assigned later 941 */ 942 if (pcibios_uninitialized_bridge_resource(bus, res)) { 943 res->flags = 0; 944 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 945 } 946 } 947 } 948 949 void pcibios_setup_bus_self(struct pci_bus *bus) 950 { 951 /* Fix up the bus resources for P2P bridges */ 952 if (bus->self != NULL) 953 pcibios_fixup_bridge(bus); 954 955 /* Platform specific bus fixups. This is currently only used 956 * by fsl_pci and I'm hoping to get rid of it at some point 957 */ 958 if (ppc_md.pcibios_fixup_bus) 959 ppc_md.pcibios_fixup_bus(bus); 960 961 /* Setup bus DMA mappings */ 962 if (ppc_md.pci_dma_bus_setup) 963 ppc_md.pci_dma_bus_setup(bus); 964 } 965 966 static void pcibios_setup_device(struct pci_dev *dev) 967 { 968 /* Fixup NUMA node as it may not be setup yet by the generic 969 * code and is needed by the DMA init 970 */ 971 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 972 973 /* Hook up default DMA ops */ 974 set_dma_ops(&dev->dev, pci_dma_ops); 975 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 976 977 /* Additional platform DMA/iommu setup */ 978 if (ppc_md.pci_dma_dev_setup) 979 ppc_md.pci_dma_dev_setup(dev); 980 981 /* Read default IRQs and fixup if necessary */ 982 pci_read_irq_line(dev); 983 if (ppc_md.pci_irq_fixup) 984 ppc_md.pci_irq_fixup(dev); 985 } 986 987 int pcibios_add_device(struct pci_dev *dev) 988 { 989 /* 990 * We can only call pcibios_setup_device() after bus setup is complete, 991 * since some of the platform specific DMA setup code depends on it. 992 */ 993 if (dev->bus->is_added) 994 pcibios_setup_device(dev); 995 return 0; 996 } 997 998 void pcibios_setup_bus_devices(struct pci_bus *bus) 999 { 1000 struct pci_dev *dev; 1001 1002 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1003 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1004 1005 list_for_each_entry(dev, &bus->devices, bus_list) { 1006 /* Cardbus can call us to add new devices to a bus, so ignore 1007 * those who are already fully discovered 1008 */ 1009 if (dev->is_added) 1010 continue; 1011 1012 pcibios_setup_device(dev); 1013 } 1014 } 1015 1016 void pcibios_set_master(struct pci_dev *dev) 1017 { 1018 /* No special bus mastering setup handling */ 1019 } 1020 1021 void pcibios_fixup_bus(struct pci_bus *bus) 1022 { 1023 /* When called from the generic PCI probe, read PCI<->PCI bridge 1024 * bases. This is -not- called when generating the PCI tree from 1025 * the OF device-tree. 1026 */ 1027 pci_read_bridge_bases(bus); 1028 1029 /* Now fixup the bus bus */ 1030 pcibios_setup_bus_self(bus); 1031 1032 /* Now fixup devices on that bus */ 1033 pcibios_setup_bus_devices(bus); 1034 } 1035 EXPORT_SYMBOL(pcibios_fixup_bus); 1036 1037 void pci_fixup_cardbus(struct pci_bus *bus) 1038 { 1039 /* Now fixup devices on that bus */ 1040 pcibios_setup_bus_devices(bus); 1041 } 1042 1043 1044 static int skip_isa_ioresource_align(struct pci_dev *dev) 1045 { 1046 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1047 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1048 return 1; 1049 return 0; 1050 } 1051 1052 /* 1053 * We need to avoid collisions with `mirrored' VGA ports 1054 * and other strange ISA hardware, so we always want the 1055 * addresses to be allocated in the 0x000-0x0ff region 1056 * modulo 0x400. 1057 * 1058 * Why? Because some silly external IO cards only decode 1059 * the low 10 bits of the IO address. The 0x00-0xff region 1060 * is reserved for motherboard devices that decode all 16 1061 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1062 * but we want to try to avoid allocating at 0x2900-0x2bff 1063 * which might have be mirrored at 0x0100-0x03ff.. 1064 */ 1065 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1066 resource_size_t size, resource_size_t align) 1067 { 1068 struct pci_dev *dev = data; 1069 resource_size_t start = res->start; 1070 1071 if (res->flags & IORESOURCE_IO) { 1072 if (skip_isa_ioresource_align(dev)) 1073 return start; 1074 if (start & 0x300) 1075 start = (start + 0x3ff) & ~0x3ff; 1076 } 1077 1078 return start; 1079 } 1080 EXPORT_SYMBOL(pcibios_align_resource); 1081 1082 /* 1083 * Reparent resource children of pr that conflict with res 1084 * under res, and make res replace those children. 1085 */ 1086 static int reparent_resources(struct resource *parent, 1087 struct resource *res) 1088 { 1089 struct resource *p, **pp; 1090 struct resource **firstpp = NULL; 1091 1092 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1093 if (p->end < res->start) 1094 continue; 1095 if (res->end < p->start) 1096 break; 1097 if (p->start < res->start || p->end > res->end) 1098 return -1; /* not completely contained */ 1099 if (firstpp == NULL) 1100 firstpp = pp; 1101 } 1102 if (firstpp == NULL) 1103 return -1; /* didn't find any conflicting entries? */ 1104 res->parent = parent; 1105 res->child = *firstpp; 1106 res->sibling = *pp; 1107 *firstpp = res; 1108 *pp = NULL; 1109 for (p = res->child; p != NULL; p = p->sibling) { 1110 p->parent = res; 1111 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1112 p->name, 1113 (unsigned long long)p->start, 1114 (unsigned long long)p->end, res->name); 1115 } 1116 return 0; 1117 } 1118 1119 /* 1120 * Handle resources of PCI devices. If the world were perfect, we could 1121 * just allocate all the resource regions and do nothing more. It isn't. 1122 * On the other hand, we cannot just re-allocate all devices, as it would 1123 * require us to know lots of host bridge internals. So we attempt to 1124 * keep as much of the original configuration as possible, but tweak it 1125 * when it's found to be wrong. 1126 * 1127 * Known BIOS problems we have to work around: 1128 * - I/O or memory regions not configured 1129 * - regions configured, but not enabled in the command register 1130 * - bogus I/O addresses above 64K used 1131 * - expansion ROMs left enabled (this may sound harmless, but given 1132 * the fact the PCI specs explicitly allow address decoders to be 1133 * shared between expansion ROMs and other resource regions, it's 1134 * at least dangerous) 1135 * 1136 * Our solution: 1137 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1138 * This gives us fixed barriers on where we can allocate. 1139 * (2) Allocate resources for all enabled devices. If there is 1140 * a collision, just mark the resource as unallocated. Also 1141 * disable expansion ROMs during this step. 1142 * (3) Try to allocate resources for disabled devices. If the 1143 * resources were assigned correctly, everything goes well, 1144 * if they weren't, they won't disturb allocation of other 1145 * resources. 1146 * (4) Assign new addresses to resources which were either 1147 * not configured at all or misconfigured. If explicitly 1148 * requested by the user, configure expansion ROM address 1149 * as well. 1150 */ 1151 1152 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1153 { 1154 struct pci_bus *b; 1155 int i; 1156 struct resource *res, *pr; 1157 1158 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1159 pci_domain_nr(bus), bus->number); 1160 1161 pci_bus_for_each_resource(bus, res, i) { 1162 if (!res || !res->flags || res->start > res->end || res->parent) 1163 continue; 1164 1165 /* If the resource was left unset at this point, we clear it */ 1166 if (res->flags & IORESOURCE_UNSET) 1167 goto clear_resource; 1168 1169 if (bus->parent == NULL) 1170 pr = (res->flags & IORESOURCE_IO) ? 1171 &ioport_resource : &iomem_resource; 1172 else { 1173 pr = pci_find_parent_resource(bus->self, res); 1174 if (pr == res) { 1175 /* this happens when the generic PCI 1176 * code (wrongly) decides that this 1177 * bridge is transparent -- paulus 1178 */ 1179 continue; 1180 } 1181 } 1182 1183 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1184 "[0x%x], parent %p (%s)\n", 1185 bus->self ? pci_name(bus->self) : "PHB", 1186 bus->number, i, 1187 (unsigned long long)res->start, 1188 (unsigned long long)res->end, 1189 (unsigned int)res->flags, 1190 pr, (pr && pr->name) ? pr->name : "nil"); 1191 1192 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1193 if (request_resource(pr, res) == 0) 1194 continue; 1195 /* 1196 * Must be a conflict with an existing entry. 1197 * Move that entry (or entries) under the 1198 * bridge resource and try again. 1199 */ 1200 if (reparent_resources(pr, res) == 0) 1201 continue; 1202 } 1203 pr_warning("PCI: Cannot allocate resource region " 1204 "%d of PCI bridge %d, will remap\n", i, bus->number); 1205 clear_resource: 1206 /* The resource might be figured out when doing 1207 * reassignment based on the resources required 1208 * by the downstream PCI devices. Here we set 1209 * the size of the resource to be 0 in order to 1210 * save more space. 1211 */ 1212 res->start = 0; 1213 res->end = -1; 1214 res->flags = 0; 1215 } 1216 1217 list_for_each_entry(b, &bus->children, node) 1218 pcibios_allocate_bus_resources(b); 1219 } 1220 1221 static inline void alloc_resource(struct pci_dev *dev, int idx) 1222 { 1223 struct resource *pr, *r = &dev->resource[idx]; 1224 1225 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1226 pci_name(dev), idx, 1227 (unsigned long long)r->start, 1228 (unsigned long long)r->end, 1229 (unsigned int)r->flags); 1230 1231 pr = pci_find_parent_resource(dev, r); 1232 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1233 request_resource(pr, r) < 0) { 1234 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1235 " of device %s, will remap\n", idx, pci_name(dev)); 1236 if (pr) 1237 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1238 pr, 1239 (unsigned long long)pr->start, 1240 (unsigned long long)pr->end, 1241 (unsigned int)pr->flags); 1242 /* We'll assign a new address later */ 1243 r->flags |= IORESOURCE_UNSET; 1244 r->end -= r->start; 1245 r->start = 0; 1246 } 1247 } 1248 1249 static void __init pcibios_allocate_resources(int pass) 1250 { 1251 struct pci_dev *dev = NULL; 1252 int idx, disabled; 1253 u16 command; 1254 struct resource *r; 1255 1256 for_each_pci_dev(dev) { 1257 pci_read_config_word(dev, PCI_COMMAND, &command); 1258 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1259 r = &dev->resource[idx]; 1260 if (r->parent) /* Already allocated */ 1261 continue; 1262 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1263 continue; /* Not assigned at all */ 1264 /* We only allocate ROMs on pass 1 just in case they 1265 * have been screwed up by firmware 1266 */ 1267 if (idx == PCI_ROM_RESOURCE ) 1268 disabled = 1; 1269 if (r->flags & IORESOURCE_IO) 1270 disabled = !(command & PCI_COMMAND_IO); 1271 else 1272 disabled = !(command & PCI_COMMAND_MEMORY); 1273 if (pass == disabled) 1274 alloc_resource(dev, idx); 1275 } 1276 if (pass) 1277 continue; 1278 r = &dev->resource[PCI_ROM_RESOURCE]; 1279 if (r->flags) { 1280 /* Turn the ROM off, leave the resource region, 1281 * but keep it unregistered. 1282 */ 1283 u32 reg; 1284 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1285 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1286 pr_debug("PCI: Switching off ROM of %s\n", 1287 pci_name(dev)); 1288 r->flags &= ~IORESOURCE_ROM_ENABLE; 1289 pci_write_config_dword(dev, dev->rom_base_reg, 1290 reg & ~PCI_ROM_ADDRESS_ENABLE); 1291 } 1292 } 1293 } 1294 } 1295 1296 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1297 { 1298 struct pci_controller *hose = pci_bus_to_host(bus); 1299 resource_size_t offset; 1300 struct resource *res, *pres; 1301 int i; 1302 1303 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1304 1305 /* Check for IO */ 1306 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1307 goto no_io; 1308 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1309 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1310 BUG_ON(res == NULL); 1311 res->name = "Legacy IO"; 1312 res->flags = IORESOURCE_IO; 1313 res->start = offset; 1314 res->end = (offset + 0xfff) & 0xfffffffful; 1315 pr_debug("Candidate legacy IO: %pR\n", res); 1316 if (request_resource(&hose->io_resource, res)) { 1317 printk(KERN_DEBUG 1318 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1319 pci_domain_nr(bus), bus->number, res); 1320 kfree(res); 1321 } 1322 1323 no_io: 1324 /* Check for memory */ 1325 for (i = 0; i < 3; i++) { 1326 pres = &hose->mem_resources[i]; 1327 offset = hose->mem_offset[i]; 1328 if (!(pres->flags & IORESOURCE_MEM)) 1329 continue; 1330 pr_debug("hose mem res: %pR\n", pres); 1331 if ((pres->start - offset) <= 0xa0000 && 1332 (pres->end - offset) >= 0xbffff) 1333 break; 1334 } 1335 if (i >= 3) 1336 return; 1337 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1338 BUG_ON(res == NULL); 1339 res->name = "Legacy VGA memory"; 1340 res->flags = IORESOURCE_MEM; 1341 res->start = 0xa0000 + offset; 1342 res->end = 0xbffff + offset; 1343 pr_debug("Candidate VGA memory: %pR\n", res); 1344 if (request_resource(pres, res)) { 1345 printk(KERN_DEBUG 1346 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1347 pci_domain_nr(bus), bus->number, res); 1348 kfree(res); 1349 } 1350 } 1351 1352 void __init pcibios_resource_survey(void) 1353 { 1354 struct pci_bus *b; 1355 1356 /* Allocate and assign resources */ 1357 list_for_each_entry(b, &pci_root_buses, node) 1358 pcibios_allocate_bus_resources(b); 1359 pcibios_allocate_resources(0); 1360 pcibios_allocate_resources(1); 1361 1362 /* Before we start assigning unassigned resource, we try to reserve 1363 * the low IO area and the VGA memory area if they intersect the 1364 * bus available resources to avoid allocating things on top of them 1365 */ 1366 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1367 list_for_each_entry(b, &pci_root_buses, node) 1368 pcibios_reserve_legacy_regions(b); 1369 } 1370 1371 /* Now, if the platform didn't decide to blindly trust the firmware, 1372 * we proceed to assigning things that were left unassigned 1373 */ 1374 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1375 pr_debug("PCI: Assigning unassigned resources...\n"); 1376 pci_assign_unassigned_resources(); 1377 } 1378 1379 /* Call machine dependent fixup */ 1380 if (ppc_md.pcibios_fixup) 1381 ppc_md.pcibios_fixup(); 1382 } 1383 1384 /* This is used by the PCI hotplug driver to allocate resource 1385 * of newly plugged busses. We can try to consolidate with the 1386 * rest of the code later, for now, keep it as-is as our main 1387 * resource allocation function doesn't deal with sub-trees yet. 1388 */ 1389 void pcibios_claim_one_bus(struct pci_bus *bus) 1390 { 1391 struct pci_dev *dev; 1392 struct pci_bus *child_bus; 1393 1394 list_for_each_entry(dev, &bus->devices, bus_list) { 1395 int i; 1396 1397 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1398 struct resource *r = &dev->resource[i]; 1399 1400 if (r->parent || !r->start || !r->flags) 1401 continue; 1402 1403 pr_debug("PCI: Claiming %s: " 1404 "Resource %d: %016llx..%016llx [%x]\n", 1405 pci_name(dev), i, 1406 (unsigned long long)r->start, 1407 (unsigned long long)r->end, 1408 (unsigned int)r->flags); 1409 1410 pci_claim_resource(dev, i); 1411 } 1412 } 1413 1414 list_for_each_entry(child_bus, &bus->children, node) 1415 pcibios_claim_one_bus(child_bus); 1416 } 1417 1418 1419 /* pcibios_finish_adding_to_bus 1420 * 1421 * This is to be called by the hotplug code after devices have been 1422 * added to a bus, this include calling it for a PHB that is just 1423 * being added 1424 */ 1425 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1426 { 1427 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1428 pci_domain_nr(bus), bus->number); 1429 1430 /* Allocate bus and devices resources */ 1431 pcibios_allocate_bus_resources(bus); 1432 pcibios_claim_one_bus(bus); 1433 if (!pci_has_flag(PCI_PROBE_ONLY)) 1434 pci_assign_unassigned_bus_resources(bus); 1435 1436 /* Fixup EEH */ 1437 eeh_add_device_tree_late(bus); 1438 1439 /* Add new devices to global lists. Register in proc, sysfs. */ 1440 pci_bus_add_devices(bus); 1441 1442 /* sysfs files should only be added after devices are added */ 1443 eeh_add_sysfs_files(bus); 1444 } 1445 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1446 1447 int pcibios_enable_device(struct pci_dev *dev, int mask) 1448 { 1449 if (ppc_md.pcibios_enable_device_hook) 1450 if (ppc_md.pcibios_enable_device_hook(dev)) 1451 return -EINVAL; 1452 1453 return pci_enable_resources(dev, mask); 1454 } 1455 1456 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1457 { 1458 return (unsigned long) hose->io_base_virt - _IO_BASE; 1459 } 1460 1461 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1462 struct list_head *resources) 1463 { 1464 struct resource *res; 1465 resource_size_t offset; 1466 int i; 1467 1468 /* Hookup PHB IO resource */ 1469 res = &hose->io_resource; 1470 1471 if (!res->flags) { 1472 printk(KERN_WARNING "PCI: I/O resource not set for host" 1473 " bridge %s (domain %d)\n", 1474 hose->dn->full_name, hose->global_number); 1475 } else { 1476 offset = pcibios_io_space_offset(hose); 1477 1478 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n", 1479 (unsigned long long)res->start, 1480 (unsigned long long)res->end, 1481 (unsigned long)res->flags, 1482 (unsigned long long)offset); 1483 pci_add_resource_offset(resources, res, offset); 1484 } 1485 1486 /* Hookup PHB Memory resources */ 1487 for (i = 0; i < 3; ++i) { 1488 res = &hose->mem_resources[i]; 1489 if (!res->flags) { 1490 if (i == 0) 1491 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1492 "host bridge %s (domain %d)\n", 1493 hose->dn->full_name, hose->global_number); 1494 continue; 1495 } 1496 offset = hose->mem_offset[i]; 1497 1498 1499 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i, 1500 (unsigned long long)res->start, 1501 (unsigned long long)res->end, 1502 (unsigned long)res->flags, 1503 (unsigned long long)offset); 1504 1505 pci_add_resource_offset(resources, res, offset); 1506 } 1507 } 1508 1509 /* 1510 * Null PCI config access functions, for the case when we can't 1511 * find a hose. 1512 */ 1513 #define NULL_PCI_OP(rw, size, type) \ 1514 static int \ 1515 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1516 { \ 1517 return PCIBIOS_DEVICE_NOT_FOUND; \ 1518 } 1519 1520 static int 1521 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1522 int len, u32 *val) 1523 { 1524 return PCIBIOS_DEVICE_NOT_FOUND; 1525 } 1526 1527 static int 1528 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1529 int len, u32 val) 1530 { 1531 return PCIBIOS_DEVICE_NOT_FOUND; 1532 } 1533 1534 static struct pci_ops null_pci_ops = 1535 { 1536 .read = null_read_config, 1537 .write = null_write_config, 1538 }; 1539 1540 /* 1541 * These functions are used early on before PCI scanning is done 1542 * and all of the pci_dev and pci_bus structures have been created. 1543 */ 1544 static struct pci_bus * 1545 fake_pci_bus(struct pci_controller *hose, int busnr) 1546 { 1547 static struct pci_bus bus; 1548 1549 if (hose == NULL) { 1550 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1551 } 1552 bus.number = busnr; 1553 bus.sysdata = hose; 1554 bus.ops = hose? hose->ops: &null_pci_ops; 1555 return &bus; 1556 } 1557 1558 #define EARLY_PCI_OP(rw, size, type) \ 1559 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1560 int devfn, int offset, type value) \ 1561 { \ 1562 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1563 devfn, offset, value); \ 1564 } 1565 1566 EARLY_PCI_OP(read, byte, u8 *) 1567 EARLY_PCI_OP(read, word, u16 *) 1568 EARLY_PCI_OP(read, dword, u32 *) 1569 EARLY_PCI_OP(write, byte, u8) 1570 EARLY_PCI_OP(write, word, u16) 1571 EARLY_PCI_OP(write, dword, u32) 1572 1573 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1574 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1575 int cap) 1576 { 1577 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1578 } 1579 1580 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1581 { 1582 struct pci_controller *hose = bus->sysdata; 1583 1584 return of_node_get(hose->dn); 1585 } 1586 1587 /** 1588 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1589 * @hose: Pointer to the PCI host controller instance structure 1590 */ 1591 void pcibios_scan_phb(struct pci_controller *hose) 1592 { 1593 LIST_HEAD(resources); 1594 struct pci_bus *bus; 1595 struct device_node *node = hose->dn; 1596 int mode; 1597 1598 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1599 1600 /* Get some IO space for the new PHB */ 1601 pcibios_setup_phb_io_space(hose); 1602 1603 /* Wire up PHB bus resources */ 1604 pcibios_setup_phb_resources(hose, &resources); 1605 1606 hose->busn.start = hose->first_busno; 1607 hose->busn.end = hose->last_busno; 1608 hose->busn.flags = IORESOURCE_BUS; 1609 pci_add_resource(&resources, &hose->busn); 1610 1611 /* Create an empty bus for the toplevel */ 1612 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1613 hose->ops, hose, &resources); 1614 if (bus == NULL) { 1615 pr_err("Failed to create bus for PCI domain %04x\n", 1616 hose->global_number); 1617 pci_free_resource_list(&resources); 1618 return; 1619 } 1620 hose->bus = bus; 1621 1622 /* Get probe mode and perform scan */ 1623 mode = PCI_PROBE_NORMAL; 1624 if (node && ppc_md.pci_probe_mode) 1625 mode = ppc_md.pci_probe_mode(bus); 1626 pr_debug(" probe mode: %d\n", mode); 1627 if (mode == PCI_PROBE_DEVTREE) 1628 of_scan_bus(node, bus); 1629 1630 if (mode == PCI_PROBE_NORMAL) { 1631 pci_bus_update_busn_res_end(bus, 255); 1632 hose->last_busno = pci_scan_child_bus(bus); 1633 pci_bus_update_busn_res_end(bus, hose->last_busno); 1634 } 1635 1636 /* Platform gets a chance to do some global fixups before 1637 * we proceed to resource allocation 1638 */ 1639 if (ppc_md.pcibios_fixup_phb) 1640 ppc_md.pcibios_fixup_phb(hose); 1641 1642 /* Configure PCI Express settings */ 1643 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1644 struct pci_bus *child; 1645 list_for_each_entry(child, &bus->children, node) 1646 pcie_bus_configure_settings(child); 1647 } 1648 } 1649 1650 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1651 { 1652 int i, class = dev->class >> 8; 1653 /* When configured as agent, programing interface = 1 */ 1654 int prog_if = dev->class & 0xf; 1655 1656 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1657 class == PCI_CLASS_BRIDGE_OTHER) && 1658 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1659 (prog_if == 0) && 1660 (dev->bus->parent == NULL)) { 1661 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1662 dev->resource[i].start = 0; 1663 dev->resource[i].end = 0; 1664 dev->resource[i].flags = 0; 1665 } 1666 } 1667 } 1668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1670 1671 static void fixup_vga(struct pci_dev *pdev) 1672 { 1673 u16 cmd; 1674 1675 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1676 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) 1677 vga_set_default_device(pdev); 1678 1679 } 1680 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1681 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); 1682