1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/export.h> 25 #include <linux/of_address.h> 26 #include <linux/of_pci.h> 27 #include <linux/mm.h> 28 #include <linux/list.h> 29 #include <linux/syscalls.h> 30 #include <linux/irq.h> 31 #include <linux/vmalloc.h> 32 #include <linux/slab.h> 33 #include <linux/vgaarb.h> 34 35 #include <asm/processor.h> 36 #include <asm/io.h> 37 #include <asm/prom.h> 38 #include <asm/pci-bridge.h> 39 #include <asm/byteorder.h> 40 #include <asm/machdep.h> 41 #include <asm/ppc-pci.h> 42 #include <asm/eeh.h> 43 44 static DEFINE_SPINLOCK(hose_spinlock); 45 LIST_HEAD(hose_list); 46 47 /* XXX kill that some day ... */ 48 static int global_phb_number; /* Global phb counter */ 49 50 /* ISA Memory physical address */ 51 resource_size_t isa_mem_base; 52 53 54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 55 56 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 57 { 58 pci_dma_ops = dma_ops; 59 } 60 61 struct dma_map_ops *get_pci_dma_ops(void) 62 { 63 return pci_dma_ops; 64 } 65 EXPORT_SYMBOL(get_pci_dma_ops); 66 67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 68 { 69 struct pci_controller *phb; 70 71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 72 if (phb == NULL) 73 return NULL; 74 spin_lock(&hose_spinlock); 75 phb->global_number = global_phb_number++; 76 list_add_tail(&phb->list_node, &hose_list); 77 spin_unlock(&hose_spinlock); 78 phb->dn = dev; 79 phb->is_dynamic = mem_init_done; 80 #ifdef CONFIG_PPC64 81 if (dev) { 82 int nid = of_node_to_nid(dev); 83 84 if (nid < 0 || !node_online(nid)) 85 nid = -1; 86 87 PHB_SET_NODE(phb, nid); 88 } 89 #endif 90 return phb; 91 } 92 93 void pcibios_free_controller(struct pci_controller *phb) 94 { 95 spin_lock(&hose_spinlock); 96 list_del(&phb->list_node); 97 spin_unlock(&hose_spinlock); 98 99 if (phb->is_dynamic) 100 kfree(phb); 101 } 102 103 /* 104 * The function is used to return the minimal alignment 105 * for memory or I/O windows of the associated P2P bridge. 106 * By default, 4KiB alignment for I/O windows and 1MiB for 107 * memory windows. 108 */ 109 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 110 unsigned long type) 111 { 112 if (ppc_md.pcibios_window_alignment) 113 return ppc_md.pcibios_window_alignment(bus, type); 114 115 /* 116 * PCI core will figure out the default 117 * alignment: 4KiB for I/O and 1MiB for 118 * memory window. 119 */ 120 return 1; 121 } 122 123 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 124 { 125 #ifdef CONFIG_PPC64 126 return hose->pci_io_size; 127 #else 128 return resource_size(&hose->io_resource); 129 #endif 130 } 131 132 int pcibios_vaddr_is_ioport(void __iomem *address) 133 { 134 int ret = 0; 135 struct pci_controller *hose; 136 resource_size_t size; 137 138 spin_lock(&hose_spinlock); 139 list_for_each_entry(hose, &hose_list, list_node) { 140 size = pcibios_io_size(hose); 141 if (address >= hose->io_base_virt && 142 address < (hose->io_base_virt + size)) { 143 ret = 1; 144 break; 145 } 146 } 147 spin_unlock(&hose_spinlock); 148 return ret; 149 } 150 151 unsigned long pci_address_to_pio(phys_addr_t address) 152 { 153 struct pci_controller *hose; 154 resource_size_t size; 155 unsigned long ret = ~0; 156 157 spin_lock(&hose_spinlock); 158 list_for_each_entry(hose, &hose_list, list_node) { 159 size = pcibios_io_size(hose); 160 if (address >= hose->io_base_phys && 161 address < (hose->io_base_phys + size)) { 162 unsigned long base = 163 (unsigned long)hose->io_base_virt - _IO_BASE; 164 ret = base + (address - hose->io_base_phys); 165 break; 166 } 167 } 168 spin_unlock(&hose_spinlock); 169 170 return ret; 171 } 172 EXPORT_SYMBOL_GPL(pci_address_to_pio); 173 174 /* 175 * Return the domain number for this bus. 176 */ 177 int pci_domain_nr(struct pci_bus *bus) 178 { 179 struct pci_controller *hose = pci_bus_to_host(bus); 180 181 return hose->global_number; 182 } 183 EXPORT_SYMBOL(pci_domain_nr); 184 185 /* This routine is meant to be used early during boot, when the 186 * PCI bus numbers have not yet been assigned, and you need to 187 * issue PCI config cycles to an OF device. 188 * It could also be used to "fix" RTAS config cycles if you want 189 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 190 * config cycles. 191 */ 192 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 193 { 194 while(node) { 195 struct pci_controller *hose, *tmp; 196 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 197 if (hose->dn == node) 198 return hose; 199 node = node->parent; 200 } 201 return NULL; 202 } 203 204 static ssize_t pci_show_devspec(struct device *dev, 205 struct device_attribute *attr, char *buf) 206 { 207 struct pci_dev *pdev; 208 struct device_node *np; 209 210 pdev = to_pci_dev (dev); 211 np = pci_device_to_OF_node(pdev); 212 if (np == NULL || np->full_name == NULL) 213 return 0; 214 return sprintf(buf, "%s", np->full_name); 215 } 216 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 217 218 /* Add sysfs properties */ 219 int pcibios_add_platform_entries(struct pci_dev *pdev) 220 { 221 return device_create_file(&pdev->dev, &dev_attr_devspec); 222 } 223 224 /* 225 * Reads the interrupt pin to determine if interrupt is use by card. 226 * If the interrupt is used, then gets the interrupt line from the 227 * openfirmware and sets it in the pci_dev and pci_config line. 228 */ 229 static int pci_read_irq_line(struct pci_dev *pci_dev) 230 { 231 struct of_phandle_args oirq; 232 unsigned int virq; 233 234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 235 236 #ifdef DEBUG 237 memset(&oirq, 0xff, sizeof(oirq)); 238 #endif 239 /* Try to get a mapping from the device-tree */ 240 if (of_irq_parse_pci(pci_dev, &oirq)) { 241 u8 line, pin; 242 243 /* If that fails, lets fallback to what is in the config 244 * space and map that through the default controller. We 245 * also set the type to level low since that's what PCI 246 * interrupts are. If your platform does differently, then 247 * either provide a proper interrupt tree or don't use this 248 * function. 249 */ 250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 251 return -1; 252 if (pin == 0) 253 return -1; 254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 255 line == 0xff || line == 0) { 256 return -1; 257 } 258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 259 line, pin); 260 261 virq = irq_create_mapping(NULL, line); 262 if (virq != NO_IRQ) 263 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 264 } else { 265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 266 oirq.args_count, oirq.args[0], oirq.args[1], 267 of_node_full_name(oirq.np)); 268 269 virq = irq_create_of_mapping(&oirq); 270 } 271 if(virq == NO_IRQ) { 272 pr_debug(" Failed to map !\n"); 273 return -1; 274 } 275 276 pr_debug(" Mapped to linux irq %d\n", virq); 277 278 pci_dev->irq = virq; 279 280 return 0; 281 } 282 283 /* 284 * Platform support for /proc/bus/pci/X/Y mmap()s, 285 * modelled on the sparc64 implementation by Dave Miller. 286 * -- paulus. 287 */ 288 289 /* 290 * Adjust vm_pgoff of VMA such that it is the physical page offset 291 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 292 * 293 * Basically, the user finds the base address for his device which he wishes 294 * to mmap. They read the 32-bit value from the config space base register, 295 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 296 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 297 * 298 * Returns negative error code on failure, zero on success. 299 */ 300 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 301 resource_size_t *offset, 302 enum pci_mmap_state mmap_state) 303 { 304 struct pci_controller *hose = pci_bus_to_host(dev->bus); 305 unsigned long io_offset = 0; 306 int i, res_bit; 307 308 if (hose == NULL) 309 return NULL; /* should never happen */ 310 311 /* If memory, add on the PCI bridge address offset */ 312 if (mmap_state == pci_mmap_mem) { 313 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 314 *offset += hose->pci_mem_offset; 315 #endif 316 res_bit = IORESOURCE_MEM; 317 } else { 318 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 319 *offset += io_offset; 320 res_bit = IORESOURCE_IO; 321 } 322 323 /* 324 * Check that the offset requested corresponds to one of the 325 * resources of the device. 326 */ 327 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 328 struct resource *rp = &dev->resource[i]; 329 int flags = rp->flags; 330 331 /* treat ROM as memory (should be already) */ 332 if (i == PCI_ROM_RESOURCE) 333 flags |= IORESOURCE_MEM; 334 335 /* Active and same type? */ 336 if ((flags & res_bit) == 0) 337 continue; 338 339 /* In the range of this resource? */ 340 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 341 continue; 342 343 /* found it! construct the final physical address */ 344 if (mmap_state == pci_mmap_io) 345 *offset += hose->io_base_phys - io_offset; 346 return rp; 347 } 348 349 return NULL; 350 } 351 352 /* 353 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 354 * device mapping. 355 */ 356 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 357 pgprot_t protection, 358 enum pci_mmap_state mmap_state, 359 int write_combine) 360 { 361 362 /* Write combine is always 0 on non-memory space mappings. On 363 * memory space, if the user didn't pass 1, we check for a 364 * "prefetchable" resource. This is a bit hackish, but we use 365 * this to workaround the inability of /sysfs to provide a write 366 * combine bit 367 */ 368 if (mmap_state != pci_mmap_mem) 369 write_combine = 0; 370 else if (write_combine == 0) { 371 if (rp->flags & IORESOURCE_PREFETCH) 372 write_combine = 1; 373 } 374 375 /* XXX would be nice to have a way to ask for write-through */ 376 if (write_combine) 377 return pgprot_noncached_wc(protection); 378 else 379 return pgprot_noncached(protection); 380 } 381 382 /* 383 * This one is used by /dev/mem and fbdev who have no clue about the 384 * PCI device, it tries to find the PCI device first and calls the 385 * above routine 386 */ 387 pgprot_t pci_phys_mem_access_prot(struct file *file, 388 unsigned long pfn, 389 unsigned long size, 390 pgprot_t prot) 391 { 392 struct pci_dev *pdev = NULL; 393 struct resource *found = NULL; 394 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 395 int i; 396 397 if (page_is_ram(pfn)) 398 return prot; 399 400 prot = pgprot_noncached(prot); 401 for_each_pci_dev(pdev) { 402 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 403 struct resource *rp = &pdev->resource[i]; 404 int flags = rp->flags; 405 406 /* Active and same type? */ 407 if ((flags & IORESOURCE_MEM) == 0) 408 continue; 409 /* In the range of this resource? */ 410 if (offset < (rp->start & PAGE_MASK) || 411 offset > rp->end) 412 continue; 413 found = rp; 414 break; 415 } 416 if (found) 417 break; 418 } 419 if (found) { 420 if (found->flags & IORESOURCE_PREFETCH) 421 prot = pgprot_noncached_wc(prot); 422 pci_dev_put(pdev); 423 } 424 425 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 426 (unsigned long long)offset, pgprot_val(prot)); 427 428 return prot; 429 } 430 431 432 /* 433 * Perform the actual remap of the pages for a PCI device mapping, as 434 * appropriate for this architecture. The region in the process to map 435 * is described by vm_start and vm_end members of VMA, the base physical 436 * address is found in vm_pgoff. 437 * The pci device structure is provided so that architectures may make mapping 438 * decisions on a per-device or per-bus basis. 439 * 440 * Returns a negative error code on failure, zero on success. 441 */ 442 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 443 enum pci_mmap_state mmap_state, int write_combine) 444 { 445 resource_size_t offset = 446 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 447 struct resource *rp; 448 int ret; 449 450 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 451 if (rp == NULL) 452 return -EINVAL; 453 454 vma->vm_pgoff = offset >> PAGE_SHIFT; 455 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 456 vma->vm_page_prot, 457 mmap_state, write_combine); 458 459 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 460 vma->vm_end - vma->vm_start, vma->vm_page_prot); 461 462 return ret; 463 } 464 465 /* This provides legacy IO read access on a bus */ 466 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 467 { 468 unsigned long offset; 469 struct pci_controller *hose = pci_bus_to_host(bus); 470 struct resource *rp = &hose->io_resource; 471 void __iomem *addr; 472 473 /* Check if port can be supported by that bus. We only check 474 * the ranges of the PHB though, not the bus itself as the rules 475 * for forwarding legacy cycles down bridges are not our problem 476 * here. So if the host bridge supports it, we do it. 477 */ 478 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 479 offset += port; 480 481 if (!(rp->flags & IORESOURCE_IO)) 482 return -ENXIO; 483 if (offset < rp->start || (offset + size) > rp->end) 484 return -ENXIO; 485 addr = hose->io_base_virt + port; 486 487 switch(size) { 488 case 1: 489 *((u8 *)val) = in_8(addr); 490 return 1; 491 case 2: 492 if (port & 1) 493 return -EINVAL; 494 *((u16 *)val) = in_le16(addr); 495 return 2; 496 case 4: 497 if (port & 3) 498 return -EINVAL; 499 *((u32 *)val) = in_le32(addr); 500 return 4; 501 } 502 return -EINVAL; 503 } 504 505 /* This provides legacy IO write access on a bus */ 506 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 507 { 508 unsigned long offset; 509 struct pci_controller *hose = pci_bus_to_host(bus); 510 struct resource *rp = &hose->io_resource; 511 void __iomem *addr; 512 513 /* Check if port can be supported by that bus. We only check 514 * the ranges of the PHB though, not the bus itself as the rules 515 * for forwarding legacy cycles down bridges are not our problem 516 * here. So if the host bridge supports it, we do it. 517 */ 518 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 519 offset += port; 520 521 if (!(rp->flags & IORESOURCE_IO)) 522 return -ENXIO; 523 if (offset < rp->start || (offset + size) > rp->end) 524 return -ENXIO; 525 addr = hose->io_base_virt + port; 526 527 /* WARNING: The generic code is idiotic. It gets passed a pointer 528 * to what can be a 1, 2 or 4 byte quantity and always reads that 529 * as a u32, which means that we have to correct the location of 530 * the data read within those 32 bits for size 1 and 2 531 */ 532 switch(size) { 533 case 1: 534 out_8(addr, val >> 24); 535 return 1; 536 case 2: 537 if (port & 1) 538 return -EINVAL; 539 out_le16(addr, val >> 16); 540 return 2; 541 case 4: 542 if (port & 3) 543 return -EINVAL; 544 out_le32(addr, val); 545 return 4; 546 } 547 return -EINVAL; 548 } 549 550 /* This provides legacy IO or memory mmap access on a bus */ 551 int pci_mmap_legacy_page_range(struct pci_bus *bus, 552 struct vm_area_struct *vma, 553 enum pci_mmap_state mmap_state) 554 { 555 struct pci_controller *hose = pci_bus_to_host(bus); 556 resource_size_t offset = 557 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 558 resource_size_t size = vma->vm_end - vma->vm_start; 559 struct resource *rp; 560 561 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 562 pci_domain_nr(bus), bus->number, 563 mmap_state == pci_mmap_mem ? "MEM" : "IO", 564 (unsigned long long)offset, 565 (unsigned long long)(offset + size - 1)); 566 567 if (mmap_state == pci_mmap_mem) { 568 /* Hack alert ! 569 * 570 * Because X is lame and can fail starting if it gets an error trying 571 * to mmap legacy_mem (instead of just moving on without legacy memory 572 * access) we fake it here by giving it anonymous memory, effectively 573 * behaving just like /dev/zero 574 */ 575 if ((offset + size) > hose->isa_mem_size) { 576 printk(KERN_DEBUG 577 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 578 current->comm, current->pid, pci_domain_nr(bus), bus->number); 579 if (vma->vm_flags & VM_SHARED) 580 return shmem_zero_setup(vma); 581 return 0; 582 } 583 offset += hose->isa_mem_phys; 584 } else { 585 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 586 unsigned long roffset = offset + io_offset; 587 rp = &hose->io_resource; 588 if (!(rp->flags & IORESOURCE_IO)) 589 return -ENXIO; 590 if (roffset < rp->start || (roffset + size) > rp->end) 591 return -ENXIO; 592 offset += hose->io_base_phys; 593 } 594 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 595 596 vma->vm_pgoff = offset >> PAGE_SHIFT; 597 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 598 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 599 vma->vm_end - vma->vm_start, 600 vma->vm_page_prot); 601 } 602 603 void pci_resource_to_user(const struct pci_dev *dev, int bar, 604 const struct resource *rsrc, 605 resource_size_t *start, resource_size_t *end) 606 { 607 struct pci_controller *hose = pci_bus_to_host(dev->bus); 608 resource_size_t offset = 0; 609 610 if (hose == NULL) 611 return; 612 613 if (rsrc->flags & IORESOURCE_IO) 614 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 615 616 /* We pass a fully fixed up address to userland for MMIO instead of 617 * a BAR value because X is lame and expects to be able to use that 618 * to pass to /dev/mem ! 619 * 620 * That means that we'll have potentially 64 bits values where some 621 * userland apps only expect 32 (like X itself since it thinks only 622 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 623 * 32 bits CHRPs :-( 624 * 625 * Hopefully, the sysfs insterface is immune to that gunk. Once X 626 * has been fixed (and the fix spread enough), we can re-enable the 627 * 2 lines below and pass down a BAR value to userland. In that case 628 * we'll also have to re-enable the matching code in 629 * __pci_mmap_make_offset(). 630 * 631 * BenH. 632 */ 633 #if 0 634 else if (rsrc->flags & IORESOURCE_MEM) 635 offset = hose->pci_mem_offset; 636 #endif 637 638 *start = rsrc->start - offset; 639 *end = rsrc->end - offset; 640 } 641 642 /** 643 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 644 * @hose: newly allocated pci_controller to be setup 645 * @dev: device node of the host bridge 646 * @primary: set if primary bus (32 bits only, soon to be deprecated) 647 * 648 * This function will parse the "ranges" property of a PCI host bridge device 649 * node and setup the resource mapping of a pci controller based on its 650 * content. 651 * 652 * Life would be boring if it wasn't for a few issues that we have to deal 653 * with here: 654 * 655 * - We can only cope with one IO space range and up to 3 Memory space 656 * ranges. However, some machines (thanks Apple !) tend to split their 657 * space into lots of small contiguous ranges. So we have to coalesce. 658 * 659 * - Some busses have IO space not starting at 0, which causes trouble with 660 * the way we do our IO resource renumbering. The code somewhat deals with 661 * it for 64 bits but I would expect problems on 32 bits. 662 * 663 * - Some 32 bits platforms such as 4xx can have physical space larger than 664 * 32 bits so we need to use 64 bits values for the parsing 665 */ 666 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 667 struct device_node *dev, int primary) 668 { 669 const __be32 *ranges; 670 int rlen; 671 int pna = of_n_addr_cells(dev); 672 int np = pna + 5; 673 int memno = 0; 674 u32 pci_space; 675 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 676 struct resource *res; 677 678 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 679 dev->full_name, primary ? "(primary)" : ""); 680 681 /* Get ranges property */ 682 ranges = of_get_property(dev, "ranges", &rlen); 683 if (ranges == NULL) 684 return; 685 686 /* Parse it */ 687 while ((rlen -= np * 4) >= 0) { 688 /* Read next ranges element */ 689 pci_space = of_read_number(ranges, 1); 690 pci_addr = of_read_number(ranges + 1, 2); 691 cpu_addr = of_translate_address(dev, ranges + 3); 692 size = of_read_number(ranges + pna + 3, 2); 693 ranges += np; 694 695 /* If we failed translation or got a zero-sized region 696 * (some FW try to feed us with non sensical zero sized regions 697 * such as power3 which look like some kind of attempt at exposing 698 * the VGA memory hole) 699 */ 700 if (cpu_addr == OF_BAD_ADDR || size == 0) 701 continue; 702 703 /* Now consume following elements while they are contiguous */ 704 for (; rlen >= np * sizeof(u32); 705 ranges += np, rlen -= np * 4) { 706 if (of_read_number(ranges, 1) != pci_space) 707 break; 708 pci_next = of_read_number(ranges + 1, 2); 709 cpu_next = of_translate_address(dev, ranges + 3); 710 if (pci_next != pci_addr + size || 711 cpu_next != cpu_addr + size) 712 break; 713 size += of_read_number(ranges + pna + 3, 2); 714 } 715 716 /* Act based on address space type */ 717 res = NULL; 718 switch ((pci_space >> 24) & 0x3) { 719 case 1: /* PCI IO space */ 720 printk(KERN_INFO 721 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 722 cpu_addr, cpu_addr + size - 1, pci_addr); 723 724 /* We support only one IO range */ 725 if (hose->pci_io_size) { 726 printk(KERN_INFO 727 " \\--> Skipped (too many) !\n"); 728 continue; 729 } 730 #ifdef CONFIG_PPC32 731 /* On 32 bits, limit I/O space to 16MB */ 732 if (size > 0x01000000) 733 size = 0x01000000; 734 735 /* 32 bits needs to map IOs here */ 736 hose->io_base_virt = ioremap(cpu_addr, size); 737 738 /* Expect trouble if pci_addr is not 0 */ 739 if (primary) 740 isa_io_base = 741 (unsigned long)hose->io_base_virt; 742 #endif /* CONFIG_PPC32 */ 743 /* pci_io_size and io_base_phys always represent IO 744 * space starting at 0 so we factor in pci_addr 745 */ 746 hose->pci_io_size = pci_addr + size; 747 hose->io_base_phys = cpu_addr - pci_addr; 748 749 /* Build resource */ 750 res = &hose->io_resource; 751 res->flags = IORESOURCE_IO; 752 res->start = pci_addr; 753 break; 754 case 2: /* PCI Memory space */ 755 case 3: /* PCI 64 bits Memory space */ 756 printk(KERN_INFO 757 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 758 cpu_addr, cpu_addr + size - 1, pci_addr, 759 (pci_space & 0x40000000) ? "Prefetch" : ""); 760 761 /* We support only 3 memory ranges */ 762 if (memno >= 3) { 763 printk(KERN_INFO 764 " \\--> Skipped (too many) !\n"); 765 continue; 766 } 767 /* Handles ISA memory hole space here */ 768 if (pci_addr == 0) { 769 if (primary || isa_mem_base == 0) 770 isa_mem_base = cpu_addr; 771 hose->isa_mem_phys = cpu_addr; 772 hose->isa_mem_size = size; 773 } 774 775 /* Build resource */ 776 hose->mem_offset[memno] = cpu_addr - pci_addr; 777 res = &hose->mem_resources[memno++]; 778 res->flags = IORESOURCE_MEM; 779 if (pci_space & 0x40000000) 780 res->flags |= IORESOURCE_PREFETCH; 781 res->start = cpu_addr; 782 break; 783 } 784 if (res != NULL) { 785 res->name = dev->full_name; 786 res->end = res->start + size - 1; 787 res->parent = NULL; 788 res->sibling = NULL; 789 res->child = NULL; 790 } 791 } 792 } 793 794 /* Decide whether to display the domain number in /proc */ 795 int pci_proc_domain(struct pci_bus *bus) 796 { 797 struct pci_controller *hose = pci_bus_to_host(bus); 798 799 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 800 return 0; 801 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 802 return hose->global_number != 0; 803 return 1; 804 } 805 806 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 807 { 808 if (ppc_md.pcibios_root_bridge_prepare) 809 return ppc_md.pcibios_root_bridge_prepare(bridge); 810 811 return 0; 812 } 813 814 /* This header fixup will do the resource fixup for all devices as they are 815 * probed, but not for bridge ranges 816 */ 817 static void pcibios_fixup_resources(struct pci_dev *dev) 818 { 819 struct pci_controller *hose = pci_bus_to_host(dev->bus); 820 int i; 821 822 if (!hose) { 823 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 824 pci_name(dev)); 825 return; 826 } 827 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 828 struct resource *res = dev->resource + i; 829 struct pci_bus_region reg; 830 if (!res->flags) 831 continue; 832 833 /* If we're going to re-assign everything, we mark all resources 834 * as unset (and 0-base them). In addition, we mark BARs starting 835 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 836 * since in that case, we don't want to re-assign anything 837 */ 838 pcibios_resource_to_bus(dev, ®, res); 839 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 840 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 841 /* Only print message if not re-assigning */ 842 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 843 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 844 "is unassigned\n", 845 pci_name(dev), i, 846 (unsigned long long)res->start, 847 (unsigned long long)res->end, 848 (unsigned int)res->flags); 849 res->end -= res->start; 850 res->start = 0; 851 res->flags |= IORESOURCE_UNSET; 852 continue; 853 } 854 855 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 856 pci_name(dev), i, 857 (unsigned long long)res->start,\ 858 (unsigned long long)res->end, 859 (unsigned int)res->flags); 860 } 861 862 /* Call machine specific resource fixup */ 863 if (ppc_md.pcibios_fixup_resources) 864 ppc_md.pcibios_fixup_resources(dev); 865 } 866 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 867 868 /* This function tries to figure out if a bridge resource has been initialized 869 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 870 * things go more smoothly when it gets it right. It should covers cases such 871 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 872 */ 873 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 874 struct resource *res) 875 { 876 struct pci_controller *hose = pci_bus_to_host(bus); 877 struct pci_dev *dev = bus->self; 878 resource_size_t offset; 879 struct pci_bus_region region; 880 u16 command; 881 int i; 882 883 /* We don't do anything if PCI_PROBE_ONLY is set */ 884 if (pci_has_flag(PCI_PROBE_ONLY)) 885 return 0; 886 887 /* Job is a bit different between memory and IO */ 888 if (res->flags & IORESOURCE_MEM) { 889 pcibios_resource_to_bus(dev, ®ion, res); 890 891 /* If the BAR is non-0 then it's probably been initialized */ 892 if (region.start != 0) 893 return 0; 894 895 /* The BAR is 0, let's check if memory decoding is enabled on 896 * the bridge. If not, we consider it unassigned 897 */ 898 pci_read_config_word(dev, PCI_COMMAND, &command); 899 if ((command & PCI_COMMAND_MEMORY) == 0) 900 return 1; 901 902 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 903 * resources covers that starting address (0 then it's good enough for 904 * us for memory space) 905 */ 906 for (i = 0; i < 3; i++) { 907 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 908 hose->mem_resources[i].start == hose->mem_offset[i]) 909 return 0; 910 } 911 912 /* Well, it starts at 0 and we know it will collide so we may as 913 * well consider it as unassigned. That covers the Apple case. 914 */ 915 return 1; 916 } else { 917 /* If the BAR is non-0, then we consider it assigned */ 918 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 919 if (((res->start - offset) & 0xfffffffful) != 0) 920 return 0; 921 922 /* Here, we are a bit different than memory as typically IO space 923 * starting at low addresses -is- valid. What we do instead if that 924 * we consider as unassigned anything that doesn't have IO enabled 925 * in the PCI command register, and that's it. 926 */ 927 pci_read_config_word(dev, PCI_COMMAND, &command); 928 if (command & PCI_COMMAND_IO) 929 return 0; 930 931 /* It's starting at 0 and IO is disabled in the bridge, consider 932 * it unassigned 933 */ 934 return 1; 935 } 936 } 937 938 /* Fixup resources of a PCI<->PCI bridge */ 939 static void pcibios_fixup_bridge(struct pci_bus *bus) 940 { 941 struct resource *res; 942 int i; 943 944 struct pci_dev *dev = bus->self; 945 946 pci_bus_for_each_resource(bus, res, i) { 947 if (!res || !res->flags) 948 continue; 949 if (i >= 3 && bus->self->transparent) 950 continue; 951 952 /* If we're going to reassign everything, we can 953 * shrink the P2P resource to have size as being 954 * of 0 in order to save space. 955 */ 956 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 957 res->flags |= IORESOURCE_UNSET; 958 res->start = 0; 959 res->end = -1; 960 continue; 961 } 962 963 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 964 pci_name(dev), i, 965 (unsigned long long)res->start,\ 966 (unsigned long long)res->end, 967 (unsigned int)res->flags); 968 969 /* Try to detect uninitialized P2P bridge resources, 970 * and clear them out so they get re-assigned later 971 */ 972 if (pcibios_uninitialized_bridge_resource(bus, res)) { 973 res->flags = 0; 974 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 975 } 976 } 977 } 978 979 void pcibios_setup_bus_self(struct pci_bus *bus) 980 { 981 /* Fix up the bus resources for P2P bridges */ 982 if (bus->self != NULL) 983 pcibios_fixup_bridge(bus); 984 985 /* Platform specific bus fixups. This is currently only used 986 * by fsl_pci and I'm hoping to get rid of it at some point 987 */ 988 if (ppc_md.pcibios_fixup_bus) 989 ppc_md.pcibios_fixup_bus(bus); 990 991 /* Setup bus DMA mappings */ 992 if (ppc_md.pci_dma_bus_setup) 993 ppc_md.pci_dma_bus_setup(bus); 994 } 995 996 static void pcibios_setup_device(struct pci_dev *dev) 997 { 998 /* Fixup NUMA node as it may not be setup yet by the generic 999 * code and is needed by the DMA init 1000 */ 1001 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1002 1003 /* Hook up default DMA ops */ 1004 set_dma_ops(&dev->dev, pci_dma_ops); 1005 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1006 1007 /* Additional platform DMA/iommu setup */ 1008 if (ppc_md.pci_dma_dev_setup) 1009 ppc_md.pci_dma_dev_setup(dev); 1010 1011 /* Read default IRQs and fixup if necessary */ 1012 pci_read_irq_line(dev); 1013 if (ppc_md.pci_irq_fixup) 1014 ppc_md.pci_irq_fixup(dev); 1015 } 1016 1017 int pcibios_add_device(struct pci_dev *dev) 1018 { 1019 /* 1020 * We can only call pcibios_setup_device() after bus setup is complete, 1021 * since some of the platform specific DMA setup code depends on it. 1022 */ 1023 if (dev->bus->is_added) 1024 pcibios_setup_device(dev); 1025 return 0; 1026 } 1027 1028 void pcibios_setup_bus_devices(struct pci_bus *bus) 1029 { 1030 struct pci_dev *dev; 1031 1032 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1033 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1034 1035 list_for_each_entry(dev, &bus->devices, bus_list) { 1036 /* Cardbus can call us to add new devices to a bus, so ignore 1037 * those who are already fully discovered 1038 */ 1039 if (dev->is_added) 1040 continue; 1041 1042 pcibios_setup_device(dev); 1043 } 1044 } 1045 1046 void pcibios_set_master(struct pci_dev *dev) 1047 { 1048 /* No special bus mastering setup handling */ 1049 } 1050 1051 void pcibios_fixup_bus(struct pci_bus *bus) 1052 { 1053 /* When called from the generic PCI probe, read PCI<->PCI bridge 1054 * bases. This is -not- called when generating the PCI tree from 1055 * the OF device-tree. 1056 */ 1057 pci_read_bridge_bases(bus); 1058 1059 /* Now fixup the bus bus */ 1060 pcibios_setup_bus_self(bus); 1061 1062 /* Now fixup devices on that bus */ 1063 pcibios_setup_bus_devices(bus); 1064 } 1065 EXPORT_SYMBOL(pcibios_fixup_bus); 1066 1067 void pci_fixup_cardbus(struct pci_bus *bus) 1068 { 1069 /* Now fixup devices on that bus */ 1070 pcibios_setup_bus_devices(bus); 1071 } 1072 1073 1074 static int skip_isa_ioresource_align(struct pci_dev *dev) 1075 { 1076 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1077 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1078 return 1; 1079 return 0; 1080 } 1081 1082 /* 1083 * We need to avoid collisions with `mirrored' VGA ports 1084 * and other strange ISA hardware, so we always want the 1085 * addresses to be allocated in the 0x000-0x0ff region 1086 * modulo 0x400. 1087 * 1088 * Why? Because some silly external IO cards only decode 1089 * the low 10 bits of the IO address. The 0x00-0xff region 1090 * is reserved for motherboard devices that decode all 16 1091 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1092 * but we want to try to avoid allocating at 0x2900-0x2bff 1093 * which might have be mirrored at 0x0100-0x03ff.. 1094 */ 1095 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1096 resource_size_t size, resource_size_t align) 1097 { 1098 struct pci_dev *dev = data; 1099 resource_size_t start = res->start; 1100 1101 if (res->flags & IORESOURCE_IO) { 1102 if (skip_isa_ioresource_align(dev)) 1103 return start; 1104 if (start & 0x300) 1105 start = (start + 0x3ff) & ~0x3ff; 1106 } 1107 1108 return start; 1109 } 1110 EXPORT_SYMBOL(pcibios_align_resource); 1111 1112 /* 1113 * Reparent resource children of pr that conflict with res 1114 * under res, and make res replace those children. 1115 */ 1116 static int reparent_resources(struct resource *parent, 1117 struct resource *res) 1118 { 1119 struct resource *p, **pp; 1120 struct resource **firstpp = NULL; 1121 1122 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1123 if (p->end < res->start) 1124 continue; 1125 if (res->end < p->start) 1126 break; 1127 if (p->start < res->start || p->end > res->end) 1128 return -1; /* not completely contained */ 1129 if (firstpp == NULL) 1130 firstpp = pp; 1131 } 1132 if (firstpp == NULL) 1133 return -1; /* didn't find any conflicting entries? */ 1134 res->parent = parent; 1135 res->child = *firstpp; 1136 res->sibling = *pp; 1137 *firstpp = res; 1138 *pp = NULL; 1139 for (p = res->child; p != NULL; p = p->sibling) { 1140 p->parent = res; 1141 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1142 p->name, 1143 (unsigned long long)p->start, 1144 (unsigned long long)p->end, res->name); 1145 } 1146 return 0; 1147 } 1148 1149 /* 1150 * Handle resources of PCI devices. If the world were perfect, we could 1151 * just allocate all the resource regions and do nothing more. It isn't. 1152 * On the other hand, we cannot just re-allocate all devices, as it would 1153 * require us to know lots of host bridge internals. So we attempt to 1154 * keep as much of the original configuration as possible, but tweak it 1155 * when it's found to be wrong. 1156 * 1157 * Known BIOS problems we have to work around: 1158 * - I/O or memory regions not configured 1159 * - regions configured, but not enabled in the command register 1160 * - bogus I/O addresses above 64K used 1161 * - expansion ROMs left enabled (this may sound harmless, but given 1162 * the fact the PCI specs explicitly allow address decoders to be 1163 * shared between expansion ROMs and other resource regions, it's 1164 * at least dangerous) 1165 * 1166 * Our solution: 1167 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1168 * This gives us fixed barriers on where we can allocate. 1169 * (2) Allocate resources for all enabled devices. If there is 1170 * a collision, just mark the resource as unallocated. Also 1171 * disable expansion ROMs during this step. 1172 * (3) Try to allocate resources for disabled devices. If the 1173 * resources were assigned correctly, everything goes well, 1174 * if they weren't, they won't disturb allocation of other 1175 * resources. 1176 * (4) Assign new addresses to resources which were either 1177 * not configured at all or misconfigured. If explicitly 1178 * requested by the user, configure expansion ROM address 1179 * as well. 1180 */ 1181 1182 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1183 { 1184 struct pci_bus *b; 1185 int i; 1186 struct resource *res, *pr; 1187 1188 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1189 pci_domain_nr(bus), bus->number); 1190 1191 pci_bus_for_each_resource(bus, res, i) { 1192 if (!res || !res->flags || res->start > res->end || res->parent) 1193 continue; 1194 1195 /* If the resource was left unset at this point, we clear it */ 1196 if (res->flags & IORESOURCE_UNSET) 1197 goto clear_resource; 1198 1199 if (bus->parent == NULL) 1200 pr = (res->flags & IORESOURCE_IO) ? 1201 &ioport_resource : &iomem_resource; 1202 else { 1203 pr = pci_find_parent_resource(bus->self, res); 1204 if (pr == res) { 1205 /* this happens when the generic PCI 1206 * code (wrongly) decides that this 1207 * bridge is transparent -- paulus 1208 */ 1209 continue; 1210 } 1211 } 1212 1213 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1214 "[0x%x], parent %p (%s)\n", 1215 bus->self ? pci_name(bus->self) : "PHB", 1216 bus->number, i, 1217 (unsigned long long)res->start, 1218 (unsigned long long)res->end, 1219 (unsigned int)res->flags, 1220 pr, (pr && pr->name) ? pr->name : "nil"); 1221 1222 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1223 if (request_resource(pr, res) == 0) 1224 continue; 1225 /* 1226 * Must be a conflict with an existing entry. 1227 * Move that entry (or entries) under the 1228 * bridge resource and try again. 1229 */ 1230 if (reparent_resources(pr, res) == 0) 1231 continue; 1232 } 1233 pr_warning("PCI: Cannot allocate resource region " 1234 "%d of PCI bridge %d, will remap\n", i, bus->number); 1235 clear_resource: 1236 /* The resource might be figured out when doing 1237 * reassignment based on the resources required 1238 * by the downstream PCI devices. Here we set 1239 * the size of the resource to be 0 in order to 1240 * save more space. 1241 */ 1242 res->start = 0; 1243 res->end = -1; 1244 res->flags = 0; 1245 } 1246 1247 list_for_each_entry(b, &bus->children, node) 1248 pcibios_allocate_bus_resources(b); 1249 } 1250 1251 static inline void alloc_resource(struct pci_dev *dev, int idx) 1252 { 1253 struct resource *pr, *r = &dev->resource[idx]; 1254 1255 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1256 pci_name(dev), idx, 1257 (unsigned long long)r->start, 1258 (unsigned long long)r->end, 1259 (unsigned int)r->flags); 1260 1261 pr = pci_find_parent_resource(dev, r); 1262 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1263 request_resource(pr, r) < 0) { 1264 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1265 " of device %s, will remap\n", idx, pci_name(dev)); 1266 if (pr) 1267 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1268 pr, 1269 (unsigned long long)pr->start, 1270 (unsigned long long)pr->end, 1271 (unsigned int)pr->flags); 1272 /* We'll assign a new address later */ 1273 r->flags |= IORESOURCE_UNSET; 1274 r->end -= r->start; 1275 r->start = 0; 1276 } 1277 } 1278 1279 static void __init pcibios_allocate_resources(int pass) 1280 { 1281 struct pci_dev *dev = NULL; 1282 int idx, disabled; 1283 u16 command; 1284 struct resource *r; 1285 1286 for_each_pci_dev(dev) { 1287 pci_read_config_word(dev, PCI_COMMAND, &command); 1288 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1289 r = &dev->resource[idx]; 1290 if (r->parent) /* Already allocated */ 1291 continue; 1292 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1293 continue; /* Not assigned at all */ 1294 /* We only allocate ROMs on pass 1 just in case they 1295 * have been screwed up by firmware 1296 */ 1297 if (idx == PCI_ROM_RESOURCE ) 1298 disabled = 1; 1299 if (r->flags & IORESOURCE_IO) 1300 disabled = !(command & PCI_COMMAND_IO); 1301 else 1302 disabled = !(command & PCI_COMMAND_MEMORY); 1303 if (pass == disabled) 1304 alloc_resource(dev, idx); 1305 } 1306 if (pass) 1307 continue; 1308 r = &dev->resource[PCI_ROM_RESOURCE]; 1309 if (r->flags) { 1310 /* Turn the ROM off, leave the resource region, 1311 * but keep it unregistered. 1312 */ 1313 u32 reg; 1314 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1315 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1316 pr_debug("PCI: Switching off ROM of %s\n", 1317 pci_name(dev)); 1318 r->flags &= ~IORESOURCE_ROM_ENABLE; 1319 pci_write_config_dword(dev, dev->rom_base_reg, 1320 reg & ~PCI_ROM_ADDRESS_ENABLE); 1321 } 1322 } 1323 } 1324 } 1325 1326 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1327 { 1328 struct pci_controller *hose = pci_bus_to_host(bus); 1329 resource_size_t offset; 1330 struct resource *res, *pres; 1331 int i; 1332 1333 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1334 1335 /* Check for IO */ 1336 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1337 goto no_io; 1338 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1339 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1340 BUG_ON(res == NULL); 1341 res->name = "Legacy IO"; 1342 res->flags = IORESOURCE_IO; 1343 res->start = offset; 1344 res->end = (offset + 0xfff) & 0xfffffffful; 1345 pr_debug("Candidate legacy IO: %pR\n", res); 1346 if (request_resource(&hose->io_resource, res)) { 1347 printk(KERN_DEBUG 1348 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1349 pci_domain_nr(bus), bus->number, res); 1350 kfree(res); 1351 } 1352 1353 no_io: 1354 /* Check for memory */ 1355 for (i = 0; i < 3; i++) { 1356 pres = &hose->mem_resources[i]; 1357 offset = hose->mem_offset[i]; 1358 if (!(pres->flags & IORESOURCE_MEM)) 1359 continue; 1360 pr_debug("hose mem res: %pR\n", pres); 1361 if ((pres->start - offset) <= 0xa0000 && 1362 (pres->end - offset) >= 0xbffff) 1363 break; 1364 } 1365 if (i >= 3) 1366 return; 1367 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1368 BUG_ON(res == NULL); 1369 res->name = "Legacy VGA memory"; 1370 res->flags = IORESOURCE_MEM; 1371 res->start = 0xa0000 + offset; 1372 res->end = 0xbffff + offset; 1373 pr_debug("Candidate VGA memory: %pR\n", res); 1374 if (request_resource(pres, res)) { 1375 printk(KERN_DEBUG 1376 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1377 pci_domain_nr(bus), bus->number, res); 1378 kfree(res); 1379 } 1380 } 1381 1382 void __init pcibios_resource_survey(void) 1383 { 1384 struct pci_bus *b; 1385 1386 /* Allocate and assign resources */ 1387 list_for_each_entry(b, &pci_root_buses, node) 1388 pcibios_allocate_bus_resources(b); 1389 pcibios_allocate_resources(0); 1390 pcibios_allocate_resources(1); 1391 1392 /* Before we start assigning unassigned resource, we try to reserve 1393 * the low IO area and the VGA memory area if they intersect the 1394 * bus available resources to avoid allocating things on top of them 1395 */ 1396 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1397 list_for_each_entry(b, &pci_root_buses, node) 1398 pcibios_reserve_legacy_regions(b); 1399 } 1400 1401 /* Now, if the platform didn't decide to blindly trust the firmware, 1402 * we proceed to assigning things that were left unassigned 1403 */ 1404 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1405 pr_debug("PCI: Assigning unassigned resources...\n"); 1406 pci_assign_unassigned_resources(); 1407 } 1408 1409 /* Call machine dependent fixup */ 1410 if (ppc_md.pcibios_fixup) 1411 ppc_md.pcibios_fixup(); 1412 } 1413 1414 /* This is used by the PCI hotplug driver to allocate resource 1415 * of newly plugged busses. We can try to consolidate with the 1416 * rest of the code later, for now, keep it as-is as our main 1417 * resource allocation function doesn't deal with sub-trees yet. 1418 */ 1419 void pcibios_claim_one_bus(struct pci_bus *bus) 1420 { 1421 struct pci_dev *dev; 1422 struct pci_bus *child_bus; 1423 1424 list_for_each_entry(dev, &bus->devices, bus_list) { 1425 int i; 1426 1427 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1428 struct resource *r = &dev->resource[i]; 1429 1430 if (r->parent || !r->start || !r->flags) 1431 continue; 1432 1433 pr_debug("PCI: Claiming %s: " 1434 "Resource %d: %016llx..%016llx [%x]\n", 1435 pci_name(dev), i, 1436 (unsigned long long)r->start, 1437 (unsigned long long)r->end, 1438 (unsigned int)r->flags); 1439 1440 pci_claim_resource(dev, i); 1441 } 1442 } 1443 1444 list_for_each_entry(child_bus, &bus->children, node) 1445 pcibios_claim_one_bus(child_bus); 1446 } 1447 1448 1449 /* pcibios_finish_adding_to_bus 1450 * 1451 * This is to be called by the hotplug code after devices have been 1452 * added to a bus, this include calling it for a PHB that is just 1453 * being added 1454 */ 1455 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1456 { 1457 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1458 pci_domain_nr(bus), bus->number); 1459 1460 /* Allocate bus and devices resources */ 1461 pcibios_allocate_bus_resources(bus); 1462 pcibios_claim_one_bus(bus); 1463 if (!pci_has_flag(PCI_PROBE_ONLY)) 1464 pci_assign_unassigned_bus_resources(bus); 1465 1466 /* Fixup EEH */ 1467 eeh_add_device_tree_late(bus); 1468 1469 /* Add new devices to global lists. Register in proc, sysfs. */ 1470 pci_bus_add_devices(bus); 1471 1472 /* sysfs files should only be added after devices are added */ 1473 eeh_add_sysfs_files(bus); 1474 } 1475 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1476 1477 int pcibios_enable_device(struct pci_dev *dev, int mask) 1478 { 1479 if (ppc_md.pcibios_enable_device_hook) 1480 if (ppc_md.pcibios_enable_device_hook(dev)) 1481 return -EINVAL; 1482 1483 return pci_enable_resources(dev, mask); 1484 } 1485 1486 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1487 { 1488 return (unsigned long) hose->io_base_virt - _IO_BASE; 1489 } 1490 1491 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1492 struct list_head *resources) 1493 { 1494 struct resource *res; 1495 resource_size_t offset; 1496 int i; 1497 1498 /* Hookup PHB IO resource */ 1499 res = &hose->io_resource; 1500 1501 if (!res->flags) { 1502 printk(KERN_WARNING "PCI: I/O resource not set for host" 1503 " bridge %s (domain %d)\n", 1504 hose->dn->full_name, hose->global_number); 1505 } else { 1506 offset = pcibios_io_space_offset(hose); 1507 1508 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n", 1509 (unsigned long long)res->start, 1510 (unsigned long long)res->end, 1511 (unsigned long)res->flags, 1512 (unsigned long long)offset); 1513 pci_add_resource_offset(resources, res, offset); 1514 } 1515 1516 /* Hookup PHB Memory resources */ 1517 for (i = 0; i < 3; ++i) { 1518 res = &hose->mem_resources[i]; 1519 if (!res->flags) { 1520 if (i == 0) 1521 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1522 "host bridge %s (domain %d)\n", 1523 hose->dn->full_name, hose->global_number); 1524 continue; 1525 } 1526 offset = hose->mem_offset[i]; 1527 1528 1529 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i, 1530 (unsigned long long)res->start, 1531 (unsigned long long)res->end, 1532 (unsigned long)res->flags, 1533 (unsigned long long)offset); 1534 1535 pci_add_resource_offset(resources, res, offset); 1536 } 1537 } 1538 1539 /* 1540 * Null PCI config access functions, for the case when we can't 1541 * find a hose. 1542 */ 1543 #define NULL_PCI_OP(rw, size, type) \ 1544 static int \ 1545 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1546 { \ 1547 return PCIBIOS_DEVICE_NOT_FOUND; \ 1548 } 1549 1550 static int 1551 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1552 int len, u32 *val) 1553 { 1554 return PCIBIOS_DEVICE_NOT_FOUND; 1555 } 1556 1557 static int 1558 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1559 int len, u32 val) 1560 { 1561 return PCIBIOS_DEVICE_NOT_FOUND; 1562 } 1563 1564 static struct pci_ops null_pci_ops = 1565 { 1566 .read = null_read_config, 1567 .write = null_write_config, 1568 }; 1569 1570 /* 1571 * These functions are used early on before PCI scanning is done 1572 * and all of the pci_dev and pci_bus structures have been created. 1573 */ 1574 static struct pci_bus * 1575 fake_pci_bus(struct pci_controller *hose, int busnr) 1576 { 1577 static struct pci_bus bus; 1578 1579 if (hose == NULL) { 1580 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1581 } 1582 bus.number = busnr; 1583 bus.sysdata = hose; 1584 bus.ops = hose? hose->ops: &null_pci_ops; 1585 return &bus; 1586 } 1587 1588 #define EARLY_PCI_OP(rw, size, type) \ 1589 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1590 int devfn, int offset, type value) \ 1591 { \ 1592 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1593 devfn, offset, value); \ 1594 } 1595 1596 EARLY_PCI_OP(read, byte, u8 *) 1597 EARLY_PCI_OP(read, word, u16 *) 1598 EARLY_PCI_OP(read, dword, u32 *) 1599 EARLY_PCI_OP(write, byte, u8) 1600 EARLY_PCI_OP(write, word, u16) 1601 EARLY_PCI_OP(write, dword, u32) 1602 1603 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1604 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1605 int cap) 1606 { 1607 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1608 } 1609 1610 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1611 { 1612 struct pci_controller *hose = bus->sysdata; 1613 1614 return of_node_get(hose->dn); 1615 } 1616 1617 /** 1618 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1619 * @hose: Pointer to the PCI host controller instance structure 1620 */ 1621 void pcibios_scan_phb(struct pci_controller *hose) 1622 { 1623 LIST_HEAD(resources); 1624 struct pci_bus *bus; 1625 struct device_node *node = hose->dn; 1626 int mode; 1627 1628 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1629 1630 /* Get some IO space for the new PHB */ 1631 pcibios_setup_phb_io_space(hose); 1632 1633 /* Wire up PHB bus resources */ 1634 pcibios_setup_phb_resources(hose, &resources); 1635 1636 hose->busn.start = hose->first_busno; 1637 hose->busn.end = hose->last_busno; 1638 hose->busn.flags = IORESOURCE_BUS; 1639 pci_add_resource(&resources, &hose->busn); 1640 1641 /* Create an empty bus for the toplevel */ 1642 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1643 hose->ops, hose, &resources); 1644 if (bus == NULL) { 1645 pr_err("Failed to create bus for PCI domain %04x\n", 1646 hose->global_number); 1647 pci_free_resource_list(&resources); 1648 return; 1649 } 1650 hose->bus = bus; 1651 1652 /* Get probe mode and perform scan */ 1653 mode = PCI_PROBE_NORMAL; 1654 if (node && ppc_md.pci_probe_mode) 1655 mode = ppc_md.pci_probe_mode(bus); 1656 pr_debug(" probe mode: %d\n", mode); 1657 if (mode == PCI_PROBE_DEVTREE) 1658 of_scan_bus(node, bus); 1659 1660 if (mode == PCI_PROBE_NORMAL) { 1661 pci_bus_update_busn_res_end(bus, 255); 1662 hose->last_busno = pci_scan_child_bus(bus); 1663 pci_bus_update_busn_res_end(bus, hose->last_busno); 1664 } 1665 1666 /* Platform gets a chance to do some global fixups before 1667 * we proceed to resource allocation 1668 */ 1669 if (ppc_md.pcibios_fixup_phb) 1670 ppc_md.pcibios_fixup_phb(hose); 1671 1672 /* Configure PCI Express settings */ 1673 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1674 struct pci_bus *child; 1675 list_for_each_entry(child, &bus->children, node) 1676 pcie_bus_configure_settings(child); 1677 } 1678 } 1679 1680 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1681 { 1682 int i, class = dev->class >> 8; 1683 /* When configured as agent, programing interface = 1 */ 1684 int prog_if = dev->class & 0xf; 1685 1686 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1687 class == PCI_CLASS_BRIDGE_OTHER) && 1688 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1689 (prog_if == 0) && 1690 (dev->bus->parent == NULL)) { 1691 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1692 dev->resource[i].start = 0; 1693 dev->resource[i].end = 0; 1694 dev->resource[i].flags = 0; 1695 } 1696 } 1697 } 1698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1700 1701 static void fixup_vga(struct pci_dev *pdev) 1702 { 1703 u16 cmd; 1704 1705 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1706 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) 1707 vga_set_default_device(pdev); 1708 1709 } 1710 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1711 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); 1712