1/* 2 * This file contains miscellaneous low-level functions. 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) 6 * and Paul Mackerras. 7 * 8 * kexec bits: 9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> 10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz 11 * PPC44x port. Copyright (C) 2011, IBM Corporation 12 * Author: Suzuki Poulose <suzuki@in.ibm.com> 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License 16 * as published by the Free Software Foundation; either version 17 * 2 of the License, or (at your option) any later version. 18 * 19 */ 20 21#include <linux/sys.h> 22#include <asm/unistd.h> 23#include <asm/errno.h> 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/cache.h> 27#include <asm/cputable.h> 28#include <asm/mmu.h> 29#include <asm/ppc_asm.h> 30#include <asm/thread_info.h> 31#include <asm/asm-offsets.h> 32#include <asm/processor.h> 33#include <asm/kexec.h> 34#include <asm/bug.h> 35#include <asm/ptrace.h> 36 37 .text 38 39/* 40 * We store the saved ksp_limit in the unused part 41 * of the STACK_FRAME_OVERHEAD 42 */ 43_GLOBAL(call_do_softirq) 44 mflr r0 45 stw r0,4(r1) 46 lwz r10,THREAD+KSP_LIMIT(r2) 47 addi r11,r3,THREAD_INFO_GAP 48 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3) 49 mr r1,r3 50 stw r10,8(r1) 51 stw r11,THREAD+KSP_LIMIT(r2) 52 bl __do_softirq 53 lwz r10,8(r1) 54 lwz r1,0(r1) 55 lwz r0,4(r1) 56 stw r10,THREAD+KSP_LIMIT(r2) 57 mtlr r0 58 blr 59 60/* 61 * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp); 62 */ 63_GLOBAL(call_do_irq) 64 mflr r0 65 stw r0,4(r1) 66 lwz r10,THREAD+KSP_LIMIT(r2) 67 addi r11,r4,THREAD_INFO_GAP 68 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4) 69 mr r1,r4 70 stw r10,8(r1) 71 stw r11,THREAD+KSP_LIMIT(r2) 72 bl __do_irq 73 lwz r10,8(r1) 74 lwz r1,0(r1) 75 lwz r0,4(r1) 76 stw r10,THREAD+KSP_LIMIT(r2) 77 mtlr r0 78 blr 79 80/* 81 * This returns the high 64 bits of the product of two 64-bit numbers. 82 */ 83_GLOBAL(mulhdu) 84 cmpwi r6,0 85 cmpwi cr1,r3,0 86 mr r10,r4 87 mulhwu r4,r4,r5 88 beq 1f 89 mulhwu r0,r10,r6 90 mullw r7,r10,r5 91 addc r7,r0,r7 92 addze r4,r4 931: beqlr cr1 /* all done if high part of A is 0 */ 94 mr r10,r3 95 mullw r9,r3,r5 96 mulhwu r3,r3,r5 97 beq 2f 98 mullw r0,r10,r6 99 mulhwu r8,r10,r6 100 addc r7,r0,r7 101 adde r4,r4,r8 102 addze r3,r3 1032: addc r4,r4,r9 104 addze r3,r3 105 blr 106 107/* 108 * sub_reloc_offset(x) returns x - reloc_offset(). 109 */ 110_GLOBAL(sub_reloc_offset) 111 mflr r0 112 bl 1f 1131: mflr r5 114 lis r4,1b@ha 115 addi r4,r4,1b@l 116 subf r5,r4,r5 117 subf r3,r5,r3 118 mtlr r0 119 blr 120 121/* 122 * reloc_got2 runs through the .got2 section adding an offset 123 * to each entry. 124 */ 125_GLOBAL(reloc_got2) 126 mflr r11 127 lis r7,__got2_start@ha 128 addi r7,r7,__got2_start@l 129 lis r8,__got2_end@ha 130 addi r8,r8,__got2_end@l 131 subf r8,r7,r8 132 srwi. r8,r8,2 133 beqlr 134 mtctr r8 135 bl 1f 1361: mflr r0 137 lis r4,1b@ha 138 addi r4,r4,1b@l 139 subf r0,r4,r0 140 add r7,r0,r7 1412: lwz r0,0(r7) 142 add r0,r0,r3 143 stw r0,0(r7) 144 addi r7,r7,4 145 bdnz 2b 146 mtlr r11 147 blr 148 149/* 150 * call_setup_cpu - call the setup_cpu function for this cpu 151 * r3 = data offset, r24 = cpu number 152 * 153 * Setup function is called with: 154 * r3 = data offset 155 * r4 = ptr to CPU spec (relocated) 156 */ 157_GLOBAL(call_setup_cpu) 158 addis r4,r3,cur_cpu_spec@ha 159 addi r4,r4,cur_cpu_spec@l 160 lwz r4,0(r4) 161 add r4,r4,r3 162 lwz r5,CPU_SPEC_SETUP(r4) 163 cmpwi 0,r5,0 164 add r5,r5,r3 165 beqlr 166 mtctr r5 167 bctr 168 169#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) 170 171/* This gets called by via-pmu.c to switch the PLL selection 172 * on 750fx CPU. This function should really be moved to some 173 * other place (as most of the cpufreq code in via-pmu 174 */ 175_GLOBAL(low_choose_750fx_pll) 176 /* Clear MSR:EE */ 177 mfmsr r7 178 rlwinm r0,r7,0,17,15 179 mtmsr r0 180 181 /* If switching to PLL1, disable HID0:BTIC */ 182 cmplwi cr0,r3,0 183 beq 1f 184 mfspr r5,SPRN_HID0 185 rlwinm r5,r5,0,27,25 186 sync 187 mtspr SPRN_HID0,r5 188 isync 189 sync 190 1911: 192 /* Calc new HID1 value */ 193 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ 194 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ 195 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ 196 or r4,r4,r5 197 mtspr SPRN_HID1,r4 198 199 /* Store new HID1 image */ 200 CURRENT_THREAD_INFO(r6, r1) 201 lwz r6,TI_CPU(r6) 202 slwi r6,r6,2 203 addis r6,r6,nap_save_hid1@ha 204 stw r4,nap_save_hid1@l(r6) 205 206 /* If switching to PLL0, enable HID0:BTIC */ 207 cmplwi cr0,r3,0 208 bne 1f 209 mfspr r5,SPRN_HID0 210 ori r5,r5,HID0_BTIC 211 sync 212 mtspr SPRN_HID0,r5 213 isync 214 sync 215 2161: 217 /* Return */ 218 mtmsr r7 219 blr 220 221_GLOBAL(low_choose_7447a_dfs) 222 /* Clear MSR:EE */ 223 mfmsr r7 224 rlwinm r0,r7,0,17,15 225 mtmsr r0 226 227 /* Calc new HID1 value */ 228 mfspr r4,SPRN_HID1 229 insrwi r4,r3,1,9 /* insert parameter into bit 9 */ 230 sync 231 mtspr SPRN_HID1,r4 232 sync 233 isync 234 235 /* Return */ 236 mtmsr r7 237 blr 238 239#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ 240 241/* 242 * complement mask on the msr then "or" some values on. 243 * _nmask_and_or_msr(nmask, value_to_or) 244 */ 245_GLOBAL(_nmask_and_or_msr) 246 mfmsr r0 /* Get current msr */ 247 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ 248 or r0,r0,r4 /* Or on the bits in r4 (second parm) */ 249 SYNC /* Some chip revs have problems here... */ 250 mtmsr r0 /* Update machine state */ 251 isync 252 blr /* Done */ 253 254#ifdef CONFIG_40x 255 256/* 257 * Do an IO access in real mode 258 */ 259_GLOBAL(real_readb) 260 mfmsr r7 261 ori r0,r7,MSR_DR 262 xori r0,r0,MSR_DR 263 sync 264 mtmsr r0 265 sync 266 isync 267 lbz r3,0(r3) 268 sync 269 mtmsr r7 270 sync 271 isync 272 blr 273 274 /* 275 * Do an IO access in real mode 276 */ 277_GLOBAL(real_writeb) 278 mfmsr r7 279 ori r0,r7,MSR_DR 280 xori r0,r0,MSR_DR 281 sync 282 mtmsr r0 283 sync 284 isync 285 stb r3,0(r4) 286 sync 287 mtmsr r7 288 sync 289 isync 290 blr 291 292#endif /* CONFIG_40x */ 293 294 295/* 296 * Flush instruction cache. 297 * This is a no-op on the 601. 298 */ 299_GLOBAL(flush_instruction_cache) 300#if defined(CONFIG_8xx) 301 isync 302 lis r5, IDC_INVALL@h 303 mtspr SPRN_IC_CST, r5 304#elif defined(CONFIG_4xx) 305#ifdef CONFIG_403GCX 306 li r3, 512 307 mtctr r3 308 lis r4, KERNELBASE@h 3091: iccci 0, r4 310 addi r4, r4, 16 311 bdnz 1b 312#else 313 lis r3, KERNELBASE@h 314 iccci 0,r3 315#endif 316#elif CONFIG_FSL_BOOKE 317BEGIN_FTR_SECTION 318 mfspr r3,SPRN_L1CSR0 319 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC 320 /* msync; isync recommended here */ 321 mtspr SPRN_L1CSR0,r3 322 isync 323 blr 324END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) 325 mfspr r3,SPRN_L1CSR1 326 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR 327 mtspr SPRN_L1CSR1,r3 328#else 329 mfspr r3,SPRN_PVR 330 rlwinm r3,r3,16,16,31 331 cmpwi 0,r3,1 332 beqlr /* for 601, do nothing */ 333 /* 603/604 processor - use invalidate-all bit in HID0 */ 334 mfspr r3,SPRN_HID0 335 ori r3,r3,HID0_ICFI 336 mtspr SPRN_HID0,r3 337#endif /* CONFIG_8xx/4xx */ 338 isync 339 blr 340 341/* 342 * Write any modified data cache blocks out to memory 343 * and invalidate the corresponding instruction cache blocks. 344 * This is a no-op on the 601. 345 * 346 * flush_icache_range(unsigned long start, unsigned long stop) 347 */ 348_KPROBE(flush_icache_range) 349BEGIN_FTR_SECTION 350 PURGE_PREFETCHED_INS 351 blr /* for 601, do nothing */ 352END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 353 li r5,L1_CACHE_BYTES-1 354 andc r3,r3,r5 355 subf r4,r3,r4 356 add r4,r4,r5 357 srwi. r4,r4,L1_CACHE_SHIFT 358 beqlr 359 mtctr r4 360 mr r6,r3 3611: dcbst 0,r3 362 addi r3,r3,L1_CACHE_BYTES 363 bdnz 1b 364 sync /* wait for dcbst's to get to ram */ 365#ifndef CONFIG_44x 366 mtctr r4 3672: icbi 0,r6 368 addi r6,r6,L1_CACHE_BYTES 369 bdnz 2b 370#else 371 /* Flash invalidate on 44x because we are passed kmapped addresses and 372 this doesn't work for userspace pages due to the virtually tagged 373 icache. Sigh. */ 374 iccci 0, r0 375#endif 376 sync /* additional sync needed on g4 */ 377 isync 378 blr 379/* 380 * Write any modified data cache blocks out to memory. 381 * Does not invalidate the corresponding cache lines (especially for 382 * any corresponding instruction cache). 383 * 384 * clean_dcache_range(unsigned long start, unsigned long stop) 385 */ 386_GLOBAL(clean_dcache_range) 387 li r5,L1_CACHE_BYTES-1 388 andc r3,r3,r5 389 subf r4,r3,r4 390 add r4,r4,r5 391 srwi. r4,r4,L1_CACHE_SHIFT 392 beqlr 393 mtctr r4 394 3951: dcbst 0,r3 396 addi r3,r3,L1_CACHE_BYTES 397 bdnz 1b 398 sync /* wait for dcbst's to get to ram */ 399 blr 400 401/* 402 * Write any modified data cache blocks out to memory and invalidate them. 403 * Does not invalidate the corresponding instruction cache blocks. 404 * 405 * flush_dcache_range(unsigned long start, unsigned long stop) 406 */ 407_GLOBAL(flush_dcache_range) 408 li r5,L1_CACHE_BYTES-1 409 andc r3,r3,r5 410 subf r4,r3,r4 411 add r4,r4,r5 412 srwi. r4,r4,L1_CACHE_SHIFT 413 beqlr 414 mtctr r4 415 4161: dcbf 0,r3 417 addi r3,r3,L1_CACHE_BYTES 418 bdnz 1b 419 sync /* wait for dcbst's to get to ram */ 420 blr 421 422/* 423 * Like above, but invalidate the D-cache. This is used by the 8xx 424 * to invalidate the cache so the PPC core doesn't get stale data 425 * from the CPM (no cache snooping here :-). 426 * 427 * invalidate_dcache_range(unsigned long start, unsigned long stop) 428 */ 429_GLOBAL(invalidate_dcache_range) 430 li r5,L1_CACHE_BYTES-1 431 andc r3,r3,r5 432 subf r4,r3,r4 433 add r4,r4,r5 434 srwi. r4,r4,L1_CACHE_SHIFT 435 beqlr 436 mtctr r4 437 4381: dcbi 0,r3 439 addi r3,r3,L1_CACHE_BYTES 440 bdnz 1b 441 sync /* wait for dcbi's to get to ram */ 442 blr 443 444/* 445 * Flush a particular page from the data cache to RAM. 446 * Note: this is necessary because the instruction cache does *not* 447 * snoop from the data cache. 448 * This is a no-op on the 601 which has a unified cache. 449 * 450 * void __flush_dcache_icache(void *page) 451 */ 452_GLOBAL(__flush_dcache_icache) 453BEGIN_FTR_SECTION 454 PURGE_PREFETCHED_INS 455 blr 456END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 457 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 458 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 459 mtctr r4 460 mr r6,r3 4610: dcbst 0,r3 /* Write line to ram */ 462 addi r3,r3,L1_CACHE_BYTES 463 bdnz 0b 464 sync 465#ifdef CONFIG_44x 466 /* We don't flush the icache on 44x. Those have a virtual icache 467 * and we don't have access to the virtual address here (it's 468 * not the page vaddr but where it's mapped in user space). The 469 * flushing of the icache on these is handled elsewhere, when 470 * a change in the address space occurs, before returning to 471 * user space 472 */ 473BEGIN_MMU_FTR_SECTION 474 blr 475END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x) 476#endif /* CONFIG_44x */ 477 mtctr r4 4781: icbi 0,r6 479 addi r6,r6,L1_CACHE_BYTES 480 bdnz 1b 481 sync 482 isync 483 blr 484 485#ifndef CONFIG_BOOKE 486/* 487 * Flush a particular page from the data cache to RAM, identified 488 * by its physical address. We turn off the MMU so we can just use 489 * the physical address (this may be a highmem page without a kernel 490 * mapping). 491 * 492 * void __flush_dcache_icache_phys(unsigned long physaddr) 493 */ 494_GLOBAL(__flush_dcache_icache_phys) 495BEGIN_FTR_SECTION 496 PURGE_PREFETCHED_INS 497 blr /* for 601, do nothing */ 498END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 499 mfmsr r10 500 rlwinm r0,r10,0,28,26 /* clear DR */ 501 mtmsr r0 502 isync 503 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 504 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 505 mtctr r4 506 mr r6,r3 5070: dcbst 0,r3 /* Write line to ram */ 508 addi r3,r3,L1_CACHE_BYTES 509 bdnz 0b 510 sync 511 mtctr r4 5121: icbi 0,r6 513 addi r6,r6,L1_CACHE_BYTES 514 bdnz 1b 515 sync 516 mtmsr r10 /* restore DR */ 517 isync 518 blr 519#endif /* CONFIG_BOOKE */ 520 521/* 522 * Clear pages using the dcbz instruction, which doesn't cause any 523 * memory traffic (except to write out any cache lines which get 524 * displaced). This only works on cacheable memory. 525 * 526 * void clear_pages(void *page, int order) ; 527 */ 528_GLOBAL(clear_pages) 529 li r0,PAGE_SIZE/L1_CACHE_BYTES 530 slw r0,r0,r4 531 mtctr r0 5321: dcbz 0,r3 533 addi r3,r3,L1_CACHE_BYTES 534 bdnz 1b 535 blr 536 537/* 538 * Copy a whole page. We use the dcbz instruction on the destination 539 * to reduce memory traffic (it eliminates the unnecessary reads of 540 * the destination into cache). This requires that the destination 541 * is cacheable. 542 */ 543#define COPY_16_BYTES \ 544 lwz r6,4(r4); \ 545 lwz r7,8(r4); \ 546 lwz r8,12(r4); \ 547 lwzu r9,16(r4); \ 548 stw r6,4(r3); \ 549 stw r7,8(r3); \ 550 stw r8,12(r3); \ 551 stwu r9,16(r3) 552 553_GLOBAL(copy_page) 554 addi r3,r3,-4 555 addi r4,r4,-4 556 557 li r5,4 558 559#if MAX_COPY_PREFETCH > 1 560 li r0,MAX_COPY_PREFETCH 561 li r11,4 562 mtctr r0 56311: dcbt r11,r4 564 addi r11,r11,L1_CACHE_BYTES 565 bdnz 11b 566#else /* MAX_COPY_PREFETCH == 1 */ 567 dcbt r5,r4 568 li r11,L1_CACHE_BYTES+4 569#endif /* MAX_COPY_PREFETCH */ 570 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH 571 crclr 4*cr0+eq 5722: 573 mtctr r0 5741: 575 dcbt r11,r4 576 dcbz r5,r3 577 COPY_16_BYTES 578#if L1_CACHE_BYTES >= 32 579 COPY_16_BYTES 580#if L1_CACHE_BYTES >= 64 581 COPY_16_BYTES 582 COPY_16_BYTES 583#if L1_CACHE_BYTES >= 128 584 COPY_16_BYTES 585 COPY_16_BYTES 586 COPY_16_BYTES 587 COPY_16_BYTES 588#endif 589#endif 590#endif 591 bdnz 1b 592 beqlr 593 crnot 4*cr0+eq,4*cr0+eq 594 li r0,MAX_COPY_PREFETCH 595 li r11,4 596 b 2b 597 598/* 599 * Extended precision shifts. 600 * 601 * Updated to be valid for shift counts from 0 to 63 inclusive. 602 * -- Gabriel 603 * 604 * R3/R4 has 64 bit value 605 * R5 has shift count 606 * result in R3/R4 607 * 608 * ashrdi3: arithmetic right shift (sign propagation) 609 * lshrdi3: logical right shift 610 * ashldi3: left shift 611 */ 612_GLOBAL(__ashrdi3) 613 subfic r6,r5,32 614 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 615 addi r7,r5,32 # could be xori, or addi with -32 616 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 617 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 618 sraw r7,r3,r7 # t2 = MSW >> (count-32) 619 or r4,r4,r6 # LSW |= t1 620 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 621 sraw r3,r3,r5 # MSW = MSW >> count 622 or r4,r4,r7 # LSW |= t2 623 blr 624 625_GLOBAL(__ashldi3) 626 subfic r6,r5,32 627 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count 628 addi r7,r5,32 # could be xori, or addi with -32 629 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) 630 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) 631 or r3,r3,r6 # MSW |= t1 632 slw r4,r4,r5 # LSW = LSW << count 633 or r3,r3,r7 # MSW |= t2 634 blr 635 636_GLOBAL(__lshrdi3) 637 subfic r6,r5,32 638 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 639 addi r7,r5,32 # could be xori, or addi with -32 640 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 641 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) 642 or r4,r4,r6 # LSW |= t1 643 srw r3,r3,r5 # MSW = MSW >> count 644 or r4,r4,r7 # LSW |= t2 645 blr 646 647/* 648 * 64-bit comparison: __cmpdi2(s64 a, s64 b) 649 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 650 */ 651_GLOBAL(__cmpdi2) 652 cmpw r3,r5 653 li r3,1 654 bne 1f 655 cmplw r4,r6 656 beqlr 6571: li r3,0 658 bltlr 659 li r3,2 660 blr 661/* 662 * 64-bit comparison: __ucmpdi2(u64 a, u64 b) 663 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 664 */ 665_GLOBAL(__ucmpdi2) 666 cmplw r3,r5 667 li r3,1 668 bne 1f 669 cmplw r4,r6 670 beqlr 6711: li r3,0 672 bltlr 673 li r3,2 674 blr 675 676_GLOBAL(__bswapdi2) 677 rotlwi r9,r4,8 678 rotlwi r10,r3,8 679 rlwimi r9,r4,24,0,7 680 rlwimi r10,r3,24,0,7 681 rlwimi r9,r4,24,16,23 682 rlwimi r10,r3,24,16,23 683 mr r3,r9 684 mr r4,r10 685 blr 686 687_GLOBAL(abs) 688 srawi r4,r3,31 689 xor r3,r3,r4 690 sub r3,r3,r4 691 blr 692 693#ifdef CONFIG_SMP 694_GLOBAL(start_secondary_resume) 695 /* Reset stack */ 696 CURRENT_THREAD_INFO(r1, r1) 697 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 698 li r3,0 699 stw r3,0(r1) /* Zero the stack frame pointer */ 700 bl start_secondary 701 b . 702#endif /* CONFIG_SMP */ 703 704/* 705 * This routine is just here to keep GCC happy - sigh... 706 */ 707_GLOBAL(__main) 708 blr 709 710#ifdef CONFIG_KEXEC 711 /* 712 * Must be relocatable PIC code callable as a C function. 713 */ 714 .globl relocate_new_kernel 715relocate_new_kernel: 716 /* r3 = page_list */ 717 /* r4 = reboot_code_buffer */ 718 /* r5 = start_address */ 719 720#ifdef CONFIG_FSL_BOOKE 721 722 mr r29, r3 723 mr r30, r4 724 mr r31, r5 725 726#define ENTRY_MAPPING_KEXEC_SETUP 727#include "fsl_booke_entry_mapping.S" 728#undef ENTRY_MAPPING_KEXEC_SETUP 729 730 mr r3, r29 731 mr r4, r30 732 mr r5, r31 733 734 li r0, 0 735#elif defined(CONFIG_44x) 736 737 /* Save our parameters */ 738 mr r29, r3 739 mr r30, r4 740 mr r31, r5 741 742#ifdef CONFIG_PPC_47x 743 /* Check for 47x cores */ 744 mfspr r3,SPRN_PVR 745 srwi r3,r3,16 746 cmplwi cr0,r3,PVR_476FPE@h 747 beq setup_map_47x 748 cmplwi cr0,r3,PVR_476@h 749 beq setup_map_47x 750 cmplwi cr0,r3,PVR_476_ISS@h 751 beq setup_map_47x 752#endif /* CONFIG_PPC_47x */ 753 754/* 755 * Code for setting up 1:1 mapping for PPC440x for KEXEC 756 * 757 * We cannot switch off the MMU on PPC44x. 758 * So we: 759 * 1) Invalidate all the mappings except the one we are running from. 760 * 2) Create a tmp mapping for our code in the other address space(TS) and 761 * jump to it. Invalidate the entry we started in. 762 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS. 763 * 4) Jump to the 1:1 mapping in original TS. 764 * 5) Invalidate the tmp mapping. 765 * 766 * - Based on the kexec support code for FSL BookE 767 * 768 */ 769 770 /* 771 * Load the PID with kernel PID (0). 772 * Also load our MSR_IS and TID to MMUCR for TLB search. 773 */ 774 li r3, 0 775 mtspr SPRN_PID, r3 776 mfmsr r4 777 andi. r4,r4,MSR_IS@l 778 beq wmmucr 779 oris r3,r3,PPC44x_MMUCR_STS@h 780wmmucr: 781 mtspr SPRN_MMUCR,r3 782 sync 783 784 /* 785 * Invalidate all the TLB entries except the current entry 786 * where we are running from 787 */ 788 bl 0f /* Find our address */ 7890: mflr r5 /* Make it accessible */ 790 tlbsx r23,0,r5 /* Find entry we are in */ 791 li r4,0 /* Start at TLB entry 0 */ 792 li r3,0 /* Set PAGEID inval value */ 7931: cmpw r23,r4 /* Is this our entry? */ 794 beq skip /* If so, skip the inval */ 795 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ 796skip: 797 addi r4,r4,1 /* Increment */ 798 cmpwi r4,64 /* Are we done? */ 799 bne 1b /* If not, repeat */ 800 isync 801 802 /* Create a temp mapping and jump to it */ 803 andi. r6, r23, 1 /* Find the index to use */ 804 addi r24, r6, 1 /* r24 will contain 1 or 2 */ 805 806 mfmsr r9 /* get the MSR */ 807 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */ 808 xori r7, r5, 1 /* Use the other address space */ 809 810 /* Read the current mapping entries */ 811 tlbre r3, r23, PPC44x_TLB_PAGEID 812 tlbre r4, r23, PPC44x_TLB_XLAT 813 tlbre r5, r23, PPC44x_TLB_ATTRIB 814 815 /* Save our current XLAT entry */ 816 mr r25, r4 817 818 /* Extract the TLB PageSize */ 819 li r10, 1 /* r10 will hold PageSize */ 820 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */ 821 822 /* XXX: As of now we use 256M, 4K pages */ 823 cmpwi r11, PPC44x_TLB_256M 824 bne tlb_4k 825 rotlwi r10, r10, 28 /* r10 = 256M */ 826 b write_out 827tlb_4k: 828 cmpwi r11, PPC44x_TLB_4K 829 bne default 830 rotlwi r10, r10, 12 /* r10 = 4K */ 831 b write_out 832default: 833 rotlwi r10, r10, 10 /* r10 = 1K */ 834 835write_out: 836 /* 837 * Write out the tmp 1:1 mapping for this code in other address space 838 * Fixup EPN = RPN , TS=other address space 839 */ 840 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */ 841 842 /* Write out the tmp mapping entries */ 843 tlbwe r3, r24, PPC44x_TLB_PAGEID 844 tlbwe r4, r24, PPC44x_TLB_XLAT 845 tlbwe r5, r24, PPC44x_TLB_ATTRIB 846 847 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */ 848 not r10, r11 /* Mask for PageNum */ 849 850 /* Switch to other address space in MSR */ 851 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 852 853 bl 1f 8541: mflr r8 855 addi r8, r8, (2f-1b) /* Find the target offset */ 856 857 /* Jump to the tmp mapping */ 858 mtspr SPRN_SRR0, r8 859 mtspr SPRN_SRR1, r9 860 rfi 861 8622: 863 /* Invalidate the entry we were executing from */ 864 li r3, 0 865 tlbwe r3, r23, PPC44x_TLB_PAGEID 866 867 /* attribute fields. rwx for SUPERVISOR mode */ 868 li r5, 0 869 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) 870 871 /* Create 1:1 mapping in 256M pages */ 872 xori r7, r7, 1 /* Revert back to Original TS */ 873 874 li r8, 0 /* PageNumber */ 875 li r6, 3 /* TLB Index, start at 3 */ 876 877next_tlb: 878 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */ 879 mr r4, r3 /* RPN = EPN */ 880 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */ 881 insrwi r3, r7, 1, 23 /* Set TS from r7 */ 882 883 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */ 884 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */ 885 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */ 886 887 addi r8, r8, 1 /* Increment PN */ 888 addi r6, r6, 1 /* Increment TLB Index */ 889 cmpwi r8, 8 /* Are we done ? */ 890 bne next_tlb 891 isync 892 893 /* Jump to the new mapping 1:1 */ 894 li r9,0 895 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 896 897 bl 1f 8981: mflr r8 899 and r8, r8, r11 /* Get our offset within page */ 900 addi r8, r8, (2f-1b) 901 902 and r5, r25, r10 /* Get our target PageNum */ 903 or r8, r8, r5 /* Target jump address */ 904 905 mtspr SPRN_SRR0, r8 906 mtspr SPRN_SRR1, r9 907 rfi 9082: 909 /* Invalidate the tmp entry we used */ 910 li r3, 0 911 tlbwe r3, r24, PPC44x_TLB_PAGEID 912 sync 913 b ppc44x_map_done 914 915#ifdef CONFIG_PPC_47x 916 917 /* 1:1 mapping for 47x */ 918 919setup_map_47x: 920 921 /* 922 * Load the kernel pid (0) to PID and also to MMUCR[TID]. 923 * Also set the MSR IS->MMUCR STS 924 */ 925 li r3, 0 926 mtspr SPRN_PID, r3 /* Set PID */ 927 mfmsr r4 /* Get MSR */ 928 andi. r4, r4, MSR_IS@l /* TS=1? */ 929 beq 1f /* If not, leave STS=0 */ 930 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */ 9311: mtspr SPRN_MMUCR, r3 /* Put MMUCR */ 932 sync 933 934 /* Find the entry we are running from */ 935 bl 2f 9362: mflr r23 937 tlbsx r23, 0, r23 938 tlbre r24, r23, 0 /* TLB Word 0 */ 939 tlbre r25, r23, 1 /* TLB Word 1 */ 940 tlbre r26, r23, 2 /* TLB Word 2 */ 941 942 943 /* 944 * Invalidates all the tlb entries by writing to 256 RPNs(r4) 945 * of 4k page size in all 4 ways (0-3 in r3). 946 * This would invalidate the entire UTLB including the one we are 947 * running from. However the shadow TLB entries would help us 948 * to continue the execution, until we flush them (rfi/isync). 949 */ 950 addis r3, 0, 0x8000 /* specify the way */ 951 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */ 952 addi r5, 0, 0 953 b clear_utlb_entry 954 955 /* Align the loop to speed things up. from head_44x.S */ 956 .align 6 957 958clear_utlb_entry: 959 960 tlbwe r4, r3, 0 961 tlbwe r5, r3, 1 962 tlbwe r5, r3, 2 963 addis r3, r3, 0x2000 /* Increment the way */ 964 cmpwi r3, 0 965 bne clear_utlb_entry 966 addis r3, 0, 0x8000 967 addis r4, r4, 0x100 /* Increment the EPN */ 968 cmpwi r4, 0 969 bne clear_utlb_entry 970 971 /* Create the entries in the other address space */ 972 mfmsr r5 973 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */ 974 xori r7, r7, 1 /* r7 = !TS */ 975 976 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */ 977 978 /* 979 * write out the TLB entries for the tmp mapping 980 * Use way '0' so that we could easily invalidate it later. 981 */ 982 lis r3, 0x8000 /* Way '0' */ 983 984 tlbwe r24, r3, 0 985 tlbwe r25, r3, 1 986 tlbwe r26, r3, 2 987 988 /* Update the msr to the new TS */ 989 insrwi r5, r7, 1, 26 990 991 bl 1f 9921: mflr r6 993 addi r6, r6, (2f-1b) 994 995 mtspr SPRN_SRR0, r6 996 mtspr SPRN_SRR1, r5 997 rfi 998 999 /* 1000 * Now we are in the tmp address space. 1001 * Create a 1:1 mapping for 0-2GiB in the original TS. 1002 */ 10032: 1004 li r3, 0 1005 li r4, 0 /* TLB Word 0 */ 1006 li r5, 0 /* TLB Word 1 */ 1007 li r6, 0 1008 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */ 1009 1010 li r8, 0 /* PageIndex */ 1011 1012 xori r7, r7, 1 /* revert back to original TS */ 1013 1014write_utlb: 1015 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */ 1016 /* ERPN = 0 as we don't use memory above 2G */ 1017 1018 mr r4, r5 /* EPN = RPN */ 1019 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M) 1020 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */ 1021 1022 tlbwe r4, r3, 0 /* Write out the entries */ 1023 tlbwe r5, r3, 1 1024 tlbwe r6, r3, 2 1025 addi r8, r8, 1 1026 cmpwi r8, 8 /* Have we completed ? */ 1027 bne write_utlb 1028 1029 /* make sure we complete the TLB write up */ 1030 isync 1031 1032 /* 1033 * Prepare to jump to the 1:1 mapping. 1034 * 1) Extract page size of the tmp mapping 1035 * DSIZ = TLB_Word0[22:27] 1036 * 2) Calculate the physical address of the address 1037 * to jump to. 1038 */ 1039 rlwinm r10, r24, 0, 22, 27 1040 1041 cmpwi r10, PPC47x_TLB0_4K 1042 bne 0f 1043 li r10, 0x1000 /* r10 = 4k */ 1044 bl 1f 1045 10460: 1047 /* Defaults to 256M */ 1048 lis r10, 0x1000 1049 1050 bl 1f 10511: mflr r4 1052 addi r4, r4, (2f-1b) /* virtual address of 2f */ 1053 1054 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */ 1055 not r10, r11 /* Pagemask = ~(offsetmask) */ 1056 1057 and r5, r25, r10 /* Physical page */ 1058 and r6, r4, r11 /* offset within the current page */ 1059 1060 or r5, r5, r6 /* Physical address for 2f */ 1061 1062 /* Switch the TS in MSR to the original one */ 1063 mfmsr r8 1064 insrwi r8, r7, 1, 26 1065 1066 mtspr SPRN_SRR1, r8 1067 mtspr SPRN_SRR0, r5 1068 rfi 1069 10702: 1071 /* Invalidate the tmp mapping */ 1072 lis r3, 0x8000 /* Way '0' */ 1073 1074 clrrwi r24, r24, 12 /* Clear the valid bit */ 1075 tlbwe r24, r3, 0 1076 tlbwe r25, r3, 1 1077 tlbwe r26, r3, 2 1078 1079 /* Make sure we complete the TLB write and flush the shadow TLB */ 1080 isync 1081 1082#endif 1083 1084ppc44x_map_done: 1085 1086 1087 /* Restore the parameters */ 1088 mr r3, r29 1089 mr r4, r30 1090 mr r5, r31 1091 1092 li r0, 0 1093#else 1094 li r0, 0 1095 1096 /* 1097 * Set Machine Status Register to a known status, 1098 * switch the MMU off and jump to 1: in a single step. 1099 */ 1100 1101 mr r8, r0 1102 ori r8, r8, MSR_RI|MSR_ME 1103 mtspr SPRN_SRR1, r8 1104 addi r8, r4, 1f - relocate_new_kernel 1105 mtspr SPRN_SRR0, r8 1106 sync 1107 rfi 1108 11091: 1110#endif 1111 /* from this point address translation is turned off */ 1112 /* and interrupts are disabled */ 1113 1114 /* set a new stack at the bottom of our page... */ 1115 /* (not really needed now) */ 1116 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */ 1117 stw r0, 0(r1) 1118 1119 /* Do the copies */ 1120 li r6, 0 /* checksum */ 1121 mr r0, r3 1122 b 1f 1123 11240: /* top, read another word for the indirection page */ 1125 lwzu r0, 4(r3) 1126 11271: 1128 /* is it a destination page? (r8) */ 1129 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ 1130 beq 2f 1131 1132 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ 1133 b 0b 1134 11352: /* is it an indirection page? (r3) */ 1136 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ 1137 beq 2f 1138 1139 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ 1140 subi r3, r3, 4 1141 b 0b 1142 11432: /* are we done? */ 1144 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ 1145 beq 2f 1146 b 3f 1147 11482: /* is it a source page? (r9) */ 1149 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ 1150 beq 0b 1151 1152 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ 1153 1154 li r7, PAGE_SIZE / 4 1155 mtctr r7 1156 subi r9, r9, 4 1157 subi r8, r8, 4 11589: 1159 lwzu r0, 4(r9) /* do the copy */ 1160 xor r6, r6, r0 1161 stwu r0, 4(r8) 1162 dcbst 0, r8 1163 sync 1164 icbi 0, r8 1165 bdnz 9b 1166 1167 addi r9, r9, 4 1168 addi r8, r8, 4 1169 b 0b 1170 11713: 1172 1173 /* To be certain of avoiding problems with self-modifying code 1174 * execute a serializing instruction here. 1175 */ 1176 isync 1177 sync 1178 1179 mfspr r3, SPRN_PIR /* current core we are running on */ 1180 mr r4, r5 /* load physical address of chunk called */ 1181 1182 /* jump to the entry point, usually the setup routine */ 1183 mtlr r5 1184 blrl 1185 11861: b 1b 1187 1188relocate_new_kernel_end: 1189 1190 .globl relocate_new_kernel_size 1191relocate_new_kernel_size: 1192 .long relocate_new_kernel_end - relocate_new_kernel 1193#endif 1194