1/* 2 * This file contains miscellaneous low-level functions. 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) 6 * and Paul Mackerras. 7 * 8 * kexec bits: 9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> 10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz 11 * PPC44x port. Copyright (C) 2011, IBM Corporation 12 * Author: Suzuki Poulose <suzuki@in.ibm.com> 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License 16 * as published by the Free Software Foundation; either version 17 * 2 of the License, or (at your option) any later version. 18 * 19 */ 20 21#include <linux/sys.h> 22#include <asm/unistd.h> 23#include <asm/errno.h> 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/cache.h> 27#include <asm/cputable.h> 28#include <asm/mmu.h> 29#include <asm/ppc_asm.h> 30#include <asm/thread_info.h> 31#include <asm/asm-offsets.h> 32#include <asm/processor.h> 33#include <asm/kexec.h> 34#include <asm/bug.h> 35#include <asm/ptrace.h> 36#include <asm/export.h> 37#include <asm/feature-fixups.h> 38 39 .text 40 41/* 42 * We store the saved ksp_limit in the unused part 43 * of the STACK_FRAME_OVERHEAD 44 */ 45_GLOBAL(call_do_softirq) 46 mflr r0 47 stw r0,4(r1) 48 lwz r10,THREAD+KSP_LIMIT(r2) 49 addi r11,r3,THREAD_INFO_GAP 50 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3) 51 mr r1,r3 52 stw r10,8(r1) 53 stw r11,THREAD+KSP_LIMIT(r2) 54 bl __do_softirq 55 lwz r10,8(r1) 56 lwz r1,0(r1) 57 lwz r0,4(r1) 58 stw r10,THREAD+KSP_LIMIT(r2) 59 mtlr r0 60 blr 61 62/* 63 * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp); 64 */ 65_GLOBAL(call_do_irq) 66 mflr r0 67 stw r0,4(r1) 68 lwz r10,THREAD+KSP_LIMIT(r2) 69 addi r11,r4,THREAD_INFO_GAP 70 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4) 71 mr r1,r4 72 stw r10,8(r1) 73 stw r11,THREAD+KSP_LIMIT(r2) 74 bl __do_irq 75 lwz r10,8(r1) 76 lwz r1,0(r1) 77 lwz r0,4(r1) 78 stw r10,THREAD+KSP_LIMIT(r2) 79 mtlr r0 80 blr 81 82/* 83 * This returns the high 64 bits of the product of two 64-bit numbers. 84 */ 85_GLOBAL(mulhdu) 86 cmpwi r6,0 87 cmpwi cr1,r3,0 88 mr r10,r4 89 mulhwu r4,r4,r5 90 beq 1f 91 mulhwu r0,r10,r6 92 mullw r7,r10,r5 93 addc r7,r0,r7 94 addze r4,r4 951: beqlr cr1 /* all done if high part of A is 0 */ 96 mullw r9,r3,r5 97 mulhwu r10,r3,r5 98 beq 2f 99 mullw r0,r3,r6 100 mulhwu r8,r3,r6 101 addc r7,r0,r7 102 adde r4,r4,r8 103 addze r10,r10 1042: addc r4,r4,r9 105 addze r3,r10 106 blr 107 108/* 109 * reloc_got2 runs through the .got2 section adding an offset 110 * to each entry. 111 */ 112_GLOBAL(reloc_got2) 113 mflr r11 114 lis r7,__got2_start@ha 115 addi r7,r7,__got2_start@l 116 lis r8,__got2_end@ha 117 addi r8,r8,__got2_end@l 118 subf r8,r7,r8 119 srwi. r8,r8,2 120 beqlr 121 mtctr r8 122 bl 1f 1231: mflr r0 124 lis r4,1b@ha 125 addi r4,r4,1b@l 126 subf r0,r4,r0 127 add r7,r0,r7 1282: lwz r0,0(r7) 129 add r0,r0,r3 130 stw r0,0(r7) 131 addi r7,r7,4 132 bdnz 2b 133 mtlr r11 134 blr 135 136/* 137 * call_setup_cpu - call the setup_cpu function for this cpu 138 * r3 = data offset, r24 = cpu number 139 * 140 * Setup function is called with: 141 * r3 = data offset 142 * r4 = ptr to CPU spec (relocated) 143 */ 144_GLOBAL(call_setup_cpu) 145 addis r4,r3,cur_cpu_spec@ha 146 addi r4,r4,cur_cpu_spec@l 147 lwz r4,0(r4) 148 add r4,r4,r3 149 lwz r5,CPU_SPEC_SETUP(r4) 150 cmpwi 0,r5,0 151 add r5,r5,r3 152 beqlr 153 mtctr r5 154 bctr 155 156#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) 157 158/* This gets called by via-pmu.c to switch the PLL selection 159 * on 750fx CPU. This function should really be moved to some 160 * other place (as most of the cpufreq code in via-pmu 161 */ 162_GLOBAL(low_choose_750fx_pll) 163 /* Clear MSR:EE */ 164 mfmsr r7 165 rlwinm r0,r7,0,17,15 166 mtmsr r0 167 168 /* If switching to PLL1, disable HID0:BTIC */ 169 cmplwi cr0,r3,0 170 beq 1f 171 mfspr r5,SPRN_HID0 172 rlwinm r5,r5,0,27,25 173 sync 174 mtspr SPRN_HID0,r5 175 isync 176 sync 177 1781: 179 /* Calc new HID1 value */ 180 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ 181 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ 182 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ 183 or r4,r4,r5 184 mtspr SPRN_HID1,r4 185 186 /* Store new HID1 image */ 187 CURRENT_THREAD_INFO(r6, r1) 188 lwz r6,TI_CPU(r6) 189 slwi r6,r6,2 190 addis r6,r6,nap_save_hid1@ha 191 stw r4,nap_save_hid1@l(r6) 192 193 /* If switching to PLL0, enable HID0:BTIC */ 194 cmplwi cr0,r3,0 195 bne 1f 196 mfspr r5,SPRN_HID0 197 ori r5,r5,HID0_BTIC 198 sync 199 mtspr SPRN_HID0,r5 200 isync 201 sync 202 2031: 204 /* Return */ 205 mtmsr r7 206 blr 207 208_GLOBAL(low_choose_7447a_dfs) 209 /* Clear MSR:EE */ 210 mfmsr r7 211 rlwinm r0,r7,0,17,15 212 mtmsr r0 213 214 /* Calc new HID1 value */ 215 mfspr r4,SPRN_HID1 216 insrwi r4,r3,1,9 /* insert parameter into bit 9 */ 217 sync 218 mtspr SPRN_HID1,r4 219 sync 220 isync 221 222 /* Return */ 223 mtmsr r7 224 blr 225 226#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ 227 228/* 229 * complement mask on the msr then "or" some values on. 230 * _nmask_and_or_msr(nmask, value_to_or) 231 */ 232_GLOBAL(_nmask_and_or_msr) 233 mfmsr r0 /* Get current msr */ 234 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ 235 or r0,r0,r4 /* Or on the bits in r4 (second parm) */ 236 SYNC /* Some chip revs have problems here... */ 237 mtmsr r0 /* Update machine state */ 238 isync 239 blr /* Done */ 240 241#ifdef CONFIG_40x 242 243/* 244 * Do an IO access in real mode 245 */ 246_GLOBAL(real_readb) 247 mfmsr r7 248 rlwinm r0,r7,0,~MSR_DR 249 sync 250 mtmsr r0 251 sync 252 isync 253 lbz r3,0(r3) 254 sync 255 mtmsr r7 256 sync 257 isync 258 blr 259 260 /* 261 * Do an IO access in real mode 262 */ 263_GLOBAL(real_writeb) 264 mfmsr r7 265 rlwinm r0,r7,0,~MSR_DR 266 sync 267 mtmsr r0 268 sync 269 isync 270 stb r3,0(r4) 271 sync 272 mtmsr r7 273 sync 274 isync 275 blr 276 277#endif /* CONFIG_40x */ 278 279 280/* 281 * Flush instruction cache. 282 * This is a no-op on the 601. 283 */ 284#ifndef CONFIG_PPC_8xx 285_GLOBAL(flush_instruction_cache) 286#if defined(CONFIG_4xx) 287#ifdef CONFIG_403GCX 288 li r3, 512 289 mtctr r3 290 lis r4, KERNELBASE@h 2911: iccci 0, r4 292 addi r4, r4, 16 293 bdnz 1b 294#else 295 lis r3, KERNELBASE@h 296 iccci 0,r3 297#endif 298#elif defined(CONFIG_FSL_BOOKE) 299BEGIN_FTR_SECTION 300 mfspr r3,SPRN_L1CSR0 301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC 302 /* msync; isync recommended here */ 303 mtspr SPRN_L1CSR0,r3 304 isync 305 blr 306END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) 307 mfspr r3,SPRN_L1CSR1 308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR 309 mtspr SPRN_L1CSR1,r3 310#else 311 mfspr r3,SPRN_PVR 312 rlwinm r3,r3,16,16,31 313 cmpwi 0,r3,1 314 beqlr /* for 601, do nothing */ 315 /* 603/604 processor - use invalidate-all bit in HID0 */ 316 mfspr r3,SPRN_HID0 317 ori r3,r3,HID0_ICFI 318 mtspr SPRN_HID0,r3 319#endif /* CONFIG_4xx */ 320 isync 321 blr 322EXPORT_SYMBOL(flush_instruction_cache) 323#endif /* CONFIG_PPC_8xx */ 324 325/* 326 * Write any modified data cache blocks out to memory 327 * and invalidate the corresponding instruction cache blocks. 328 * This is a no-op on the 601. 329 * 330 * flush_icache_range(unsigned long start, unsigned long stop) 331 */ 332_GLOBAL(flush_icache_range) 333BEGIN_FTR_SECTION 334 PURGE_PREFETCHED_INS 335 blr /* for 601, do nothing */ 336END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 337 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT 338 subf r4,r3,r4 339 addi r4,r4,L1_CACHE_BYTES - 1 340 srwi. r4,r4,L1_CACHE_SHIFT 341 beqlr 342 mtctr r4 343 mr r6,r3 3441: dcbst 0,r3 345 addi r3,r3,L1_CACHE_BYTES 346 bdnz 1b 347 sync /* wait for dcbst's to get to ram */ 348#ifndef CONFIG_44x 349 mtctr r4 3502: icbi 0,r6 351 addi r6,r6,L1_CACHE_BYTES 352 bdnz 2b 353#else 354 /* Flash invalidate on 44x because we are passed kmapped addresses and 355 this doesn't work for userspace pages due to the virtually tagged 356 icache. Sigh. */ 357 iccci 0, r0 358#endif 359 sync /* additional sync needed on g4 */ 360 isync 361 blr 362_ASM_NOKPROBE_SYMBOL(flush_icache_range) 363EXPORT_SYMBOL(flush_icache_range) 364 365/* 366 * Flush a particular page from the data cache to RAM. 367 * Note: this is necessary because the instruction cache does *not* 368 * snoop from the data cache. 369 * This is a no-op on the 601 which has a unified cache. 370 * 371 * void __flush_dcache_icache(void *page) 372 */ 373_GLOBAL(__flush_dcache_icache) 374BEGIN_FTR_SECTION 375 PURGE_PREFETCHED_INS 376 blr 377END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 378 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 379 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 380 mtctr r4 381 mr r6,r3 3820: dcbst 0,r3 /* Write line to ram */ 383 addi r3,r3,L1_CACHE_BYTES 384 bdnz 0b 385 sync 386#ifdef CONFIG_44x 387 /* We don't flush the icache on 44x. Those have a virtual icache 388 * and we don't have access to the virtual address here (it's 389 * not the page vaddr but where it's mapped in user space). The 390 * flushing of the icache on these is handled elsewhere, when 391 * a change in the address space occurs, before returning to 392 * user space 393 */ 394BEGIN_MMU_FTR_SECTION 395 blr 396END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x) 397#endif /* CONFIG_44x */ 398 mtctr r4 3991: icbi 0,r6 400 addi r6,r6,L1_CACHE_BYTES 401 bdnz 1b 402 sync 403 isync 404 blr 405 406#ifndef CONFIG_BOOKE 407/* 408 * Flush a particular page from the data cache to RAM, identified 409 * by its physical address. We turn off the MMU so we can just use 410 * the physical address (this may be a highmem page without a kernel 411 * mapping). 412 * 413 * void __flush_dcache_icache_phys(unsigned long physaddr) 414 */ 415_GLOBAL(__flush_dcache_icache_phys) 416BEGIN_FTR_SECTION 417 PURGE_PREFETCHED_INS 418 blr /* for 601, do nothing */ 419END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 420 mfmsr r10 421 rlwinm r0,r10,0,28,26 /* clear DR */ 422 mtmsr r0 423 isync 424 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */ 425 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */ 426 mtctr r4 427 mr r6,r3 4280: dcbst 0,r3 /* Write line to ram */ 429 addi r3,r3,L1_CACHE_BYTES 430 bdnz 0b 431 sync 432 mtctr r4 4331: icbi 0,r6 434 addi r6,r6,L1_CACHE_BYTES 435 bdnz 1b 436 sync 437 mtmsr r10 /* restore DR */ 438 isync 439 blr 440#endif /* CONFIG_BOOKE */ 441 442/* 443 * Copy a whole page. We use the dcbz instruction on the destination 444 * to reduce memory traffic (it eliminates the unnecessary reads of 445 * the destination into cache). This requires that the destination 446 * is cacheable. 447 */ 448#define COPY_16_BYTES \ 449 lwz r6,4(r4); \ 450 lwz r7,8(r4); \ 451 lwz r8,12(r4); \ 452 lwzu r9,16(r4); \ 453 stw r6,4(r3); \ 454 stw r7,8(r3); \ 455 stw r8,12(r3); \ 456 stwu r9,16(r3) 457 458_GLOBAL(copy_page) 459 addi r3,r3,-4 460 addi r4,r4,-4 461 462 li r5,4 463 464#if MAX_COPY_PREFETCH > 1 465 li r0,MAX_COPY_PREFETCH 466 li r11,4 467 mtctr r0 46811: dcbt r11,r4 469 addi r11,r11,L1_CACHE_BYTES 470 bdnz 11b 471#else /* MAX_COPY_PREFETCH == 1 */ 472 dcbt r5,r4 473 li r11,L1_CACHE_BYTES+4 474#endif /* MAX_COPY_PREFETCH */ 475 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH 476 crclr 4*cr0+eq 4772: 478 mtctr r0 4791: 480 dcbt r11,r4 481 dcbz r5,r3 482 COPY_16_BYTES 483#if L1_CACHE_BYTES >= 32 484 COPY_16_BYTES 485#if L1_CACHE_BYTES >= 64 486 COPY_16_BYTES 487 COPY_16_BYTES 488#if L1_CACHE_BYTES >= 128 489 COPY_16_BYTES 490 COPY_16_BYTES 491 COPY_16_BYTES 492 COPY_16_BYTES 493#endif 494#endif 495#endif 496 bdnz 1b 497 beqlr 498 crnot 4*cr0+eq,4*cr0+eq 499 li r0,MAX_COPY_PREFETCH 500 li r11,4 501 b 2b 502EXPORT_SYMBOL(copy_page) 503 504/* 505 * Extended precision shifts. 506 * 507 * Updated to be valid for shift counts from 0 to 63 inclusive. 508 * -- Gabriel 509 * 510 * R3/R4 has 64 bit value 511 * R5 has shift count 512 * result in R3/R4 513 * 514 * ashrdi3: arithmetic right shift (sign propagation) 515 * lshrdi3: logical right shift 516 * ashldi3: left shift 517 */ 518_GLOBAL(__ashrdi3) 519 subfic r6,r5,32 520 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 521 addi r7,r5,32 # could be xori, or addi with -32 522 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 523 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 524 sraw r7,r3,r7 # t2 = MSW >> (count-32) 525 or r4,r4,r6 # LSW |= t1 526 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 527 sraw r3,r3,r5 # MSW = MSW >> count 528 or r4,r4,r7 # LSW |= t2 529 blr 530EXPORT_SYMBOL(__ashrdi3) 531 532_GLOBAL(__ashldi3) 533 subfic r6,r5,32 534 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count 535 addi r7,r5,32 # could be xori, or addi with -32 536 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) 537 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) 538 or r3,r3,r6 # MSW |= t1 539 slw r4,r4,r5 # LSW = LSW << count 540 or r3,r3,r7 # MSW |= t2 541 blr 542EXPORT_SYMBOL(__ashldi3) 543 544_GLOBAL(__lshrdi3) 545 subfic r6,r5,32 546 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 547 addi r7,r5,32 # could be xori, or addi with -32 548 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 549 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) 550 or r4,r4,r6 # LSW |= t1 551 srw r3,r3,r5 # MSW = MSW >> count 552 or r4,r4,r7 # LSW |= t2 553 blr 554EXPORT_SYMBOL(__lshrdi3) 555 556/* 557 * 64-bit comparison: __cmpdi2(s64 a, s64 b) 558 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 559 */ 560_GLOBAL(__cmpdi2) 561 cmpw r3,r5 562 li r3,1 563 bne 1f 564 cmplw r4,r6 565 beqlr 5661: li r3,0 567 bltlr 568 li r3,2 569 blr 570EXPORT_SYMBOL(__cmpdi2) 571/* 572 * 64-bit comparison: __ucmpdi2(u64 a, u64 b) 573 * Returns 0 if a < b, 1 if a == b, 2 if a > b. 574 */ 575_GLOBAL(__ucmpdi2) 576 cmplw r3,r5 577 li r3,1 578 bne 1f 579 cmplw r4,r6 580 beqlr 5811: li r3,0 582 bltlr 583 li r3,2 584 blr 585EXPORT_SYMBOL(__ucmpdi2) 586 587_GLOBAL(__bswapdi2) 588 rotlwi r9,r4,8 589 rotlwi r10,r3,8 590 rlwimi r9,r4,24,0,7 591 rlwimi r10,r3,24,0,7 592 rlwimi r9,r4,24,16,23 593 rlwimi r10,r3,24,16,23 594 mr r3,r9 595 mr r4,r10 596 blr 597EXPORT_SYMBOL(__bswapdi2) 598 599#ifdef CONFIG_SMP 600_GLOBAL(start_secondary_resume) 601 /* Reset stack */ 602 CURRENT_THREAD_INFO(r1, r1) 603 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 604 li r3,0 605 stw r3,0(r1) /* Zero the stack frame pointer */ 606 bl start_secondary 607 b . 608#endif /* CONFIG_SMP */ 609 610/* 611 * This routine is just here to keep GCC happy - sigh... 612 */ 613_GLOBAL(__main) 614 blr 615 616#ifdef CONFIG_KEXEC_CORE 617 /* 618 * Must be relocatable PIC code callable as a C function. 619 */ 620 .globl relocate_new_kernel 621relocate_new_kernel: 622 /* r3 = page_list */ 623 /* r4 = reboot_code_buffer */ 624 /* r5 = start_address */ 625 626#ifdef CONFIG_FSL_BOOKE 627 628 mr r29, r3 629 mr r30, r4 630 mr r31, r5 631 632#define ENTRY_MAPPING_KEXEC_SETUP 633#include "fsl_booke_entry_mapping.S" 634#undef ENTRY_MAPPING_KEXEC_SETUP 635 636 mr r3, r29 637 mr r4, r30 638 mr r5, r31 639 640 li r0, 0 641#elif defined(CONFIG_44x) 642 643 /* Save our parameters */ 644 mr r29, r3 645 mr r30, r4 646 mr r31, r5 647 648#ifdef CONFIG_PPC_47x 649 /* Check for 47x cores */ 650 mfspr r3,SPRN_PVR 651 srwi r3,r3,16 652 cmplwi cr0,r3,PVR_476FPE@h 653 beq setup_map_47x 654 cmplwi cr0,r3,PVR_476@h 655 beq setup_map_47x 656 cmplwi cr0,r3,PVR_476_ISS@h 657 beq setup_map_47x 658#endif /* CONFIG_PPC_47x */ 659 660/* 661 * Code for setting up 1:1 mapping for PPC440x for KEXEC 662 * 663 * We cannot switch off the MMU on PPC44x. 664 * So we: 665 * 1) Invalidate all the mappings except the one we are running from. 666 * 2) Create a tmp mapping for our code in the other address space(TS) and 667 * jump to it. Invalidate the entry we started in. 668 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS. 669 * 4) Jump to the 1:1 mapping in original TS. 670 * 5) Invalidate the tmp mapping. 671 * 672 * - Based on the kexec support code for FSL BookE 673 * 674 */ 675 676 /* 677 * Load the PID with kernel PID (0). 678 * Also load our MSR_IS and TID to MMUCR for TLB search. 679 */ 680 li r3, 0 681 mtspr SPRN_PID, r3 682 mfmsr r4 683 andi. r4,r4,MSR_IS@l 684 beq wmmucr 685 oris r3,r3,PPC44x_MMUCR_STS@h 686wmmucr: 687 mtspr SPRN_MMUCR,r3 688 sync 689 690 /* 691 * Invalidate all the TLB entries except the current entry 692 * where we are running from 693 */ 694 bl 0f /* Find our address */ 6950: mflr r5 /* Make it accessible */ 696 tlbsx r23,0,r5 /* Find entry we are in */ 697 li r4,0 /* Start at TLB entry 0 */ 698 li r3,0 /* Set PAGEID inval value */ 6991: cmpw r23,r4 /* Is this our entry? */ 700 beq skip /* If so, skip the inval */ 701 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ 702skip: 703 addi r4,r4,1 /* Increment */ 704 cmpwi r4,64 /* Are we done? */ 705 bne 1b /* If not, repeat */ 706 isync 707 708 /* Create a temp mapping and jump to it */ 709 andi. r6, r23, 1 /* Find the index to use */ 710 addi r24, r6, 1 /* r24 will contain 1 or 2 */ 711 712 mfmsr r9 /* get the MSR */ 713 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */ 714 xori r7, r5, 1 /* Use the other address space */ 715 716 /* Read the current mapping entries */ 717 tlbre r3, r23, PPC44x_TLB_PAGEID 718 tlbre r4, r23, PPC44x_TLB_XLAT 719 tlbre r5, r23, PPC44x_TLB_ATTRIB 720 721 /* Save our current XLAT entry */ 722 mr r25, r4 723 724 /* Extract the TLB PageSize */ 725 li r10, 1 /* r10 will hold PageSize */ 726 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */ 727 728 /* XXX: As of now we use 256M, 4K pages */ 729 cmpwi r11, PPC44x_TLB_256M 730 bne tlb_4k 731 rotlwi r10, r10, 28 /* r10 = 256M */ 732 b write_out 733tlb_4k: 734 cmpwi r11, PPC44x_TLB_4K 735 bne default 736 rotlwi r10, r10, 12 /* r10 = 4K */ 737 b write_out 738default: 739 rotlwi r10, r10, 10 /* r10 = 1K */ 740 741write_out: 742 /* 743 * Write out the tmp 1:1 mapping for this code in other address space 744 * Fixup EPN = RPN , TS=other address space 745 */ 746 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */ 747 748 /* Write out the tmp mapping entries */ 749 tlbwe r3, r24, PPC44x_TLB_PAGEID 750 tlbwe r4, r24, PPC44x_TLB_XLAT 751 tlbwe r5, r24, PPC44x_TLB_ATTRIB 752 753 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */ 754 not r10, r11 /* Mask for PageNum */ 755 756 /* Switch to other address space in MSR */ 757 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 758 759 bl 1f 7601: mflr r8 761 addi r8, r8, (2f-1b) /* Find the target offset */ 762 763 /* Jump to the tmp mapping */ 764 mtspr SPRN_SRR0, r8 765 mtspr SPRN_SRR1, r9 766 rfi 767 7682: 769 /* Invalidate the entry we were executing from */ 770 li r3, 0 771 tlbwe r3, r23, PPC44x_TLB_PAGEID 772 773 /* attribute fields. rwx for SUPERVISOR mode */ 774 li r5, 0 775 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) 776 777 /* Create 1:1 mapping in 256M pages */ 778 xori r7, r7, 1 /* Revert back to Original TS */ 779 780 li r8, 0 /* PageNumber */ 781 li r6, 3 /* TLB Index, start at 3 */ 782 783next_tlb: 784 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */ 785 mr r4, r3 /* RPN = EPN */ 786 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */ 787 insrwi r3, r7, 1, 23 /* Set TS from r7 */ 788 789 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */ 790 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */ 791 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */ 792 793 addi r8, r8, 1 /* Increment PN */ 794 addi r6, r6, 1 /* Increment TLB Index */ 795 cmpwi r8, 8 /* Are we done ? */ 796 bne next_tlb 797 isync 798 799 /* Jump to the new mapping 1:1 */ 800 li r9,0 801 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ 802 803 bl 1f 8041: mflr r8 805 and r8, r8, r11 /* Get our offset within page */ 806 addi r8, r8, (2f-1b) 807 808 and r5, r25, r10 /* Get our target PageNum */ 809 or r8, r8, r5 /* Target jump address */ 810 811 mtspr SPRN_SRR0, r8 812 mtspr SPRN_SRR1, r9 813 rfi 8142: 815 /* Invalidate the tmp entry we used */ 816 li r3, 0 817 tlbwe r3, r24, PPC44x_TLB_PAGEID 818 sync 819 b ppc44x_map_done 820 821#ifdef CONFIG_PPC_47x 822 823 /* 1:1 mapping for 47x */ 824 825setup_map_47x: 826 827 /* 828 * Load the kernel pid (0) to PID and also to MMUCR[TID]. 829 * Also set the MSR IS->MMUCR STS 830 */ 831 li r3, 0 832 mtspr SPRN_PID, r3 /* Set PID */ 833 mfmsr r4 /* Get MSR */ 834 andi. r4, r4, MSR_IS@l /* TS=1? */ 835 beq 1f /* If not, leave STS=0 */ 836 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */ 8371: mtspr SPRN_MMUCR, r3 /* Put MMUCR */ 838 sync 839 840 /* Find the entry we are running from */ 841 bl 2f 8422: mflr r23 843 tlbsx r23, 0, r23 844 tlbre r24, r23, 0 /* TLB Word 0 */ 845 tlbre r25, r23, 1 /* TLB Word 1 */ 846 tlbre r26, r23, 2 /* TLB Word 2 */ 847 848 849 /* 850 * Invalidates all the tlb entries by writing to 256 RPNs(r4) 851 * of 4k page size in all 4 ways (0-3 in r3). 852 * This would invalidate the entire UTLB including the one we are 853 * running from. However the shadow TLB entries would help us 854 * to continue the execution, until we flush them (rfi/isync). 855 */ 856 addis r3, 0, 0x8000 /* specify the way */ 857 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */ 858 addi r5, 0, 0 859 b clear_utlb_entry 860 861 /* Align the loop to speed things up. from head_44x.S */ 862 .align 6 863 864clear_utlb_entry: 865 866 tlbwe r4, r3, 0 867 tlbwe r5, r3, 1 868 tlbwe r5, r3, 2 869 addis r3, r3, 0x2000 /* Increment the way */ 870 cmpwi r3, 0 871 bne clear_utlb_entry 872 addis r3, 0, 0x8000 873 addis r4, r4, 0x100 /* Increment the EPN */ 874 cmpwi r4, 0 875 bne clear_utlb_entry 876 877 /* Create the entries in the other address space */ 878 mfmsr r5 879 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */ 880 xori r7, r7, 1 /* r7 = !TS */ 881 882 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */ 883 884 /* 885 * write out the TLB entries for the tmp mapping 886 * Use way '0' so that we could easily invalidate it later. 887 */ 888 lis r3, 0x8000 /* Way '0' */ 889 890 tlbwe r24, r3, 0 891 tlbwe r25, r3, 1 892 tlbwe r26, r3, 2 893 894 /* Update the msr to the new TS */ 895 insrwi r5, r7, 1, 26 896 897 bl 1f 8981: mflr r6 899 addi r6, r6, (2f-1b) 900 901 mtspr SPRN_SRR0, r6 902 mtspr SPRN_SRR1, r5 903 rfi 904 905 /* 906 * Now we are in the tmp address space. 907 * Create a 1:1 mapping for 0-2GiB in the original TS. 908 */ 9092: 910 li r3, 0 911 li r4, 0 /* TLB Word 0 */ 912 li r5, 0 /* TLB Word 1 */ 913 li r6, 0 914 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */ 915 916 li r8, 0 /* PageIndex */ 917 918 xori r7, r7, 1 /* revert back to original TS */ 919 920write_utlb: 921 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */ 922 /* ERPN = 0 as we don't use memory above 2G */ 923 924 mr r4, r5 /* EPN = RPN */ 925 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M) 926 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */ 927 928 tlbwe r4, r3, 0 /* Write out the entries */ 929 tlbwe r5, r3, 1 930 tlbwe r6, r3, 2 931 addi r8, r8, 1 932 cmpwi r8, 8 /* Have we completed ? */ 933 bne write_utlb 934 935 /* make sure we complete the TLB write up */ 936 isync 937 938 /* 939 * Prepare to jump to the 1:1 mapping. 940 * 1) Extract page size of the tmp mapping 941 * DSIZ = TLB_Word0[22:27] 942 * 2) Calculate the physical address of the address 943 * to jump to. 944 */ 945 rlwinm r10, r24, 0, 22, 27 946 947 cmpwi r10, PPC47x_TLB0_4K 948 bne 0f 949 li r10, 0x1000 /* r10 = 4k */ 950 bl 1f 951 9520: 953 /* Defaults to 256M */ 954 lis r10, 0x1000 955 956 bl 1f 9571: mflr r4 958 addi r4, r4, (2f-1b) /* virtual address of 2f */ 959 960 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */ 961 not r10, r11 /* Pagemask = ~(offsetmask) */ 962 963 and r5, r25, r10 /* Physical page */ 964 and r6, r4, r11 /* offset within the current page */ 965 966 or r5, r5, r6 /* Physical address for 2f */ 967 968 /* Switch the TS in MSR to the original one */ 969 mfmsr r8 970 insrwi r8, r7, 1, 26 971 972 mtspr SPRN_SRR1, r8 973 mtspr SPRN_SRR0, r5 974 rfi 975 9762: 977 /* Invalidate the tmp mapping */ 978 lis r3, 0x8000 /* Way '0' */ 979 980 clrrwi r24, r24, 12 /* Clear the valid bit */ 981 tlbwe r24, r3, 0 982 tlbwe r25, r3, 1 983 tlbwe r26, r3, 2 984 985 /* Make sure we complete the TLB write and flush the shadow TLB */ 986 isync 987 988#endif 989 990ppc44x_map_done: 991 992 993 /* Restore the parameters */ 994 mr r3, r29 995 mr r4, r30 996 mr r5, r31 997 998 li r0, 0 999#else 1000 li r0, 0 1001 1002 /* 1003 * Set Machine Status Register to a known status, 1004 * switch the MMU off and jump to 1: in a single step. 1005 */ 1006 1007 mr r8, r0 1008 ori r8, r8, MSR_RI|MSR_ME 1009 mtspr SPRN_SRR1, r8 1010 addi r8, r4, 1f - relocate_new_kernel 1011 mtspr SPRN_SRR0, r8 1012 sync 1013 rfi 1014 10151: 1016#endif 1017 /* from this point address translation is turned off */ 1018 /* and interrupts are disabled */ 1019 1020 /* set a new stack at the bottom of our page... */ 1021 /* (not really needed now) */ 1022 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */ 1023 stw r0, 0(r1) 1024 1025 /* Do the copies */ 1026 li r6, 0 /* checksum */ 1027 mr r0, r3 1028 b 1f 1029 10300: /* top, read another word for the indirection page */ 1031 lwzu r0, 4(r3) 1032 10331: 1034 /* is it a destination page? (r8) */ 1035 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ 1036 beq 2f 1037 1038 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ 1039 b 0b 1040 10412: /* is it an indirection page? (r3) */ 1042 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ 1043 beq 2f 1044 1045 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ 1046 subi r3, r3, 4 1047 b 0b 1048 10492: /* are we done? */ 1050 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ 1051 beq 2f 1052 b 3f 1053 10542: /* is it a source page? (r9) */ 1055 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ 1056 beq 0b 1057 1058 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ 1059 1060 li r7, PAGE_SIZE / 4 1061 mtctr r7 1062 subi r9, r9, 4 1063 subi r8, r8, 4 10649: 1065 lwzu r0, 4(r9) /* do the copy */ 1066 xor r6, r6, r0 1067 stwu r0, 4(r8) 1068 dcbst 0, r8 1069 sync 1070 icbi 0, r8 1071 bdnz 9b 1072 1073 addi r9, r9, 4 1074 addi r8, r8, 4 1075 b 0b 1076 10773: 1078 1079 /* To be certain of avoiding problems with self-modifying code 1080 * execute a serializing instruction here. 1081 */ 1082 isync 1083 sync 1084 1085 mfspr r3, SPRN_PIR /* current core we are running on */ 1086 mr r4, r5 /* load physical address of chunk called */ 1087 1088 /* jump to the entry point, usually the setup routine */ 1089 mtlr r5 1090 blrl 1091 10921: b 1b 1093 1094relocate_new_kernel_end: 1095 1096 .globl relocate_new_kernel_size 1097relocate_new_kernel_size: 1098 .long relocate_new_kernel_end - relocate_new_kernel 1099#endif 1100