xref: /openbmc/linux/arch/powerpc/kernel/misc_32.S (revision 51ad5b54) 
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * This file contains miscellaneous low-level functions.
4 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras.
8 *
9 */
10
11#include <linux/sys.h>
12#include <asm/unistd.h>
13#include <asm/errno.h>
14#include <asm/reg.h>
15#include <asm/page.h>
16#include <asm/cache.h>
17#include <asm/cputable.h>
18#include <asm/mmu.h>
19#include <asm/ppc_asm.h>
20#include <asm/thread_info.h>
21#include <asm/asm-offsets.h>
22#include <asm/processor.h>
23#include <asm/bug.h>
24#include <asm/ptrace.h>
25#include <asm/export.h>
26#include <asm/feature-fixups.h>
27
28	.text
29
30/*
31 * We store the saved ksp_limit in the unused part
32 * of the STACK_FRAME_OVERHEAD
33 */
34_GLOBAL(call_do_softirq)
35	mflr	r0
36	stw	r0,4(r1)
37	lwz	r10,THREAD+KSP_LIMIT(r2)
38	stw	r3, THREAD+KSP_LIMIT(r2)
39	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
40	mr	r1,r3
41	stw	r10,8(r1)
42	bl	__do_softirq
43	lwz	r10,8(r1)
44	lwz	r1,0(r1)
45	lwz	r0,4(r1)
46	stw	r10,THREAD+KSP_LIMIT(r2)
47	mtlr	r0
48	blr
49
50/*
51 * void call_do_irq(struct pt_regs *regs, void *sp);
52 */
53_GLOBAL(call_do_irq)
54	mflr	r0
55	stw	r0,4(r1)
56	lwz	r10,THREAD+KSP_LIMIT(r2)
57	stw	r4, THREAD+KSP_LIMIT(r2)
58	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
59	mr	r1,r4
60	stw	r10,8(r1)
61	bl	__do_irq
62	lwz	r10,8(r1)
63	lwz	r1,0(r1)
64	lwz	r0,4(r1)
65	stw	r10,THREAD+KSP_LIMIT(r2)
66	mtlr	r0
67	blr
68
69/*
70 * This returns the high 64 bits of the product of two 64-bit numbers.
71 */
72_GLOBAL(mulhdu)
73	cmpwi	r6,0
74	cmpwi	cr1,r3,0
75	mr	r10,r4
76	mulhwu	r4,r4,r5
77	beq	1f
78	mulhwu	r0,r10,r6
79	mullw	r7,r10,r5
80	addc	r7,r0,r7
81	addze	r4,r4
821:	beqlr	cr1		/* all done if high part of A is 0 */
83	mullw	r9,r3,r5
84	mulhwu	r10,r3,r5
85	beq	2f
86	mullw	r0,r3,r6
87	mulhwu	r8,r3,r6
88	addc	r7,r0,r7
89	adde	r4,r4,r8
90	addze	r10,r10
912:	addc	r4,r4,r9
92	addze	r3,r10
93	blr
94
95/*
96 * reloc_got2 runs through the .got2 section adding an offset
97 * to each entry.
98 */
99_GLOBAL(reloc_got2)
100	mflr	r11
101	lis	r7,__got2_start@ha
102	addi	r7,r7,__got2_start@l
103	lis	r8,__got2_end@ha
104	addi	r8,r8,__got2_end@l
105	subf	r8,r7,r8
106	srwi.	r8,r8,2
107	beqlr
108	mtctr	r8
109	bl	1f
1101:	mflr	r0
111	lis	r4,1b@ha
112	addi	r4,r4,1b@l
113	subf	r0,r4,r0
114	add	r7,r0,r7
1152:	lwz	r0,0(r7)
116	add	r0,r0,r3
117	stw	r0,0(r7)
118	addi	r7,r7,4
119	bdnz	2b
120	mtlr	r11
121	blr
122
123/*
124 * call_setup_cpu - call the setup_cpu function for this cpu
125 * r3 = data offset, r24 = cpu number
126 *
127 * Setup function is called with:
128 *   r3 = data offset
129 *   r4 = ptr to CPU spec (relocated)
130 */
131_GLOBAL(call_setup_cpu)
132	addis	r4,r3,cur_cpu_spec@ha
133	addi	r4,r4,cur_cpu_spec@l
134	lwz	r4,0(r4)
135	add	r4,r4,r3
136	lwz	r5,CPU_SPEC_SETUP(r4)
137	cmpwi	0,r5,0
138	add	r5,r5,r3
139	beqlr
140	mtctr	r5
141	bctr
142
143#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_PPC_BOOK3S_32)
144
145/* This gets called by via-pmu.c to switch the PLL selection
146 * on 750fx CPU. This function should really be moved to some
147 * other place (as most of the cpufreq code in via-pmu
148 */
149_GLOBAL(low_choose_750fx_pll)
150	/* Clear MSR:EE */
151	mfmsr	r7
152	rlwinm	r0,r7,0,17,15
153	mtmsr	r0
154
155	/* If switching to PLL1, disable HID0:BTIC */
156	cmplwi	cr0,r3,0
157	beq	1f
158	mfspr	r5,SPRN_HID0
159	rlwinm	r5,r5,0,27,25
160	sync
161	mtspr	SPRN_HID0,r5
162	isync
163	sync
164
1651:
166	/* Calc new HID1 value */
167	mfspr	r4,SPRN_HID1	/* Build a HID1:PS bit from parameter */
168	rlwinm	r5,r3,16,15,15	/* Clear out HID1:PS from value read */
169	rlwinm	r4,r4,0,16,14	/* Could have I used rlwimi here ? */
170	or	r4,r4,r5
171	mtspr	SPRN_HID1,r4
172
173#ifdef CONFIG_SMP
174	/* Store new HID1 image */
175	lwz	r6,TASK_CPU(r2)
176	slwi	r6,r6,2
177#else
178	li	r6, 0
179#endif
180	addis	r6,r6,nap_save_hid1@ha
181	stw	r4,nap_save_hid1@l(r6)
182
183	/* If switching to PLL0, enable HID0:BTIC */
184	cmplwi	cr0,r3,0
185	bne	1f
186	mfspr	r5,SPRN_HID0
187	ori	r5,r5,HID0_BTIC
188	sync
189	mtspr	SPRN_HID0,r5
190	isync
191	sync
192
1931:
194	/* Return */
195	mtmsr	r7
196	blr
197
198_GLOBAL(low_choose_7447a_dfs)
199	/* Clear MSR:EE */
200	mfmsr	r7
201	rlwinm	r0,r7,0,17,15
202	mtmsr	r0
203
204	/* Calc new HID1 value */
205	mfspr	r4,SPRN_HID1
206	insrwi	r4,r3,1,9	/* insert parameter into bit 9 */
207	sync
208	mtspr	SPRN_HID1,r4
209	sync
210	isync
211
212	/* Return */
213	mtmsr	r7
214	blr
215
216#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */
217
218/*
219 * complement mask on the msr then "or" some values on.
220 *     _nmask_and_or_msr(nmask, value_to_or)
221 */
222_GLOBAL(_nmask_and_or_msr)
223	mfmsr	r0		/* Get current msr */
224	andc	r0,r0,r3	/* And off the bits set in r3 (first parm) */
225	or	r0,r0,r4	/* Or on the bits in r4 (second parm) */
226	SYNC			/* Some chip revs have problems here... */
227	mtmsr	r0		/* Update machine state */
228	isync
229	blr			/* Done */
230
231#ifdef CONFIG_40x
232
233/*
234 * Do an IO access in real mode
235 */
236_GLOBAL(real_readb)
237	mfmsr	r7
238	rlwinm	r0,r7,0,~MSR_DR
239	sync
240	mtmsr	r0
241	sync
242	isync
243	lbz	r3,0(r3)
244	sync
245	mtmsr	r7
246	sync
247	isync
248	blr
249_ASM_NOKPROBE_SYMBOL(real_readb)
250
251	/*
252 * Do an IO access in real mode
253 */
254_GLOBAL(real_writeb)
255	mfmsr	r7
256	rlwinm	r0,r7,0,~MSR_DR
257	sync
258	mtmsr	r0
259	sync
260	isync
261	stb	r3,0(r4)
262	sync
263	mtmsr	r7
264	sync
265	isync
266	blr
267_ASM_NOKPROBE_SYMBOL(real_writeb)
268
269#endif /* CONFIG_40x */
270
271
272/*
273 * Flush instruction cache.
274 * This is a no-op on the 601.
275 */
276#ifndef CONFIG_PPC_8xx
277_GLOBAL(flush_instruction_cache)
278#if defined(CONFIG_4xx)
279	lis	r3, KERNELBASE@h
280	iccci	0,r3
281#elif defined(CONFIG_FSL_BOOKE)
282#ifdef CONFIG_E200
283	mfspr   r3,SPRN_L1CSR0
284	ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
285	/* msync; isync recommended here */
286	mtspr   SPRN_L1CSR0,r3
287	isync
288	blr
289#endif
290	mfspr	r3,SPRN_L1CSR1
291	ori	r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
292	mtspr	SPRN_L1CSR1,r3
293#elif defined(CONFIG_PPC_BOOK3S_601)
294	blr			/* for 601, do nothing */
295#else
296	/* 603/604 processor - use invalidate-all bit in HID0 */
297	mfspr	r3,SPRN_HID0
298	ori	r3,r3,HID0_ICFI
299	mtspr	SPRN_HID0,r3
300#endif /* CONFIG_4xx */
301	isync
302	blr
303EXPORT_SYMBOL(flush_instruction_cache)
304#endif /* CONFIG_PPC_8xx */
305
306/*
307 * Copy a whole page.  We use the dcbz instruction on the destination
308 * to reduce memory traffic (it eliminates the unnecessary reads of
309 * the destination into cache).  This requires that the destination
310 * is cacheable.
311 */
312#define COPY_16_BYTES		\
313	lwz	r6,4(r4);	\
314	lwz	r7,8(r4);	\
315	lwz	r8,12(r4);	\
316	lwzu	r9,16(r4);	\
317	stw	r6,4(r3);	\
318	stw	r7,8(r3);	\
319	stw	r8,12(r3);	\
320	stwu	r9,16(r3)
321
322_GLOBAL(copy_page)
323	rlwinm	r5, r3, 0, L1_CACHE_BYTES - 1
324	addi	r3,r3,-4
325
3260:	twnei	r5, 0	/* WARN if r3 is not cache aligned */
327	EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
328
329	addi	r4,r4,-4
330
331	li	r5,4
332
333#if MAX_COPY_PREFETCH > 1
334	li	r0,MAX_COPY_PREFETCH
335	li	r11,4
336	mtctr	r0
33711:	dcbt	r11,r4
338	addi	r11,r11,L1_CACHE_BYTES
339	bdnz	11b
340#else /* MAX_COPY_PREFETCH == 1 */
341	dcbt	r5,r4
342	li	r11,L1_CACHE_BYTES+4
343#endif /* MAX_COPY_PREFETCH */
344	li	r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
345	crclr	4*cr0+eq
3462:
347	mtctr	r0
3481:
349	dcbt	r11,r4
350	dcbz	r5,r3
351	COPY_16_BYTES
352#if L1_CACHE_BYTES >= 32
353	COPY_16_BYTES
354#if L1_CACHE_BYTES >= 64
355	COPY_16_BYTES
356	COPY_16_BYTES
357#if L1_CACHE_BYTES >= 128
358	COPY_16_BYTES
359	COPY_16_BYTES
360	COPY_16_BYTES
361	COPY_16_BYTES
362#endif
363#endif
364#endif
365	bdnz	1b
366	beqlr
367	crnot	4*cr0+eq,4*cr0+eq
368	li	r0,MAX_COPY_PREFETCH
369	li	r11,4
370	b	2b
371EXPORT_SYMBOL(copy_page)
372
373/*
374 * Extended precision shifts.
375 *
376 * Updated to be valid for shift counts from 0 to 63 inclusive.
377 * -- Gabriel
378 *
379 * R3/R4 has 64 bit value
380 * R5    has shift count
381 * result in R3/R4
382 *
383 *  ashrdi3: arithmetic right shift (sign propagation)
384 *  lshrdi3: logical right shift
385 *  ashldi3: left shift
386 */
387_GLOBAL(__ashrdi3)
388	subfic	r6,r5,32
389	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
390	addi	r7,r5,32	# could be xori, or addi with -32
391	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
392	rlwinm	r8,r7,0,32	# t3 = (count < 32) ? 32 : 0
393	sraw	r7,r3,r7	# t2 = MSW >> (count-32)
394	or	r4,r4,r6	# LSW |= t1
395	slw	r7,r7,r8	# t2 = (count < 32) ? 0 : t2
396	sraw	r3,r3,r5	# MSW = MSW >> count
397	or	r4,r4,r7	# LSW |= t2
398	blr
399EXPORT_SYMBOL(__ashrdi3)
400
401_GLOBAL(__ashldi3)
402	subfic	r6,r5,32
403	slw	r3,r3,r5	# MSW = count > 31 ? 0 : MSW << count
404	addi	r7,r5,32	# could be xori, or addi with -32
405	srw	r6,r4,r6	# t1 = count > 31 ? 0 : LSW >> (32-count)
406	slw	r7,r4,r7	# t2 = count < 32 ? 0 : LSW << (count-32)
407	or	r3,r3,r6	# MSW |= t1
408	slw	r4,r4,r5	# LSW = LSW << count
409	or	r3,r3,r7	# MSW |= t2
410	blr
411EXPORT_SYMBOL(__ashldi3)
412
413_GLOBAL(__lshrdi3)
414	subfic	r6,r5,32
415	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
416	addi	r7,r5,32	# could be xori, or addi with -32
417	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
418	srw	r7,r3,r7	# t2 = count < 32 ? 0 : MSW >> (count-32)
419	or	r4,r4,r6	# LSW |= t1
420	srw	r3,r3,r5	# MSW = MSW >> count
421	or	r4,r4,r7	# LSW |= t2
422	blr
423EXPORT_SYMBOL(__lshrdi3)
424
425/*
426 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
427 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
428 */
429_GLOBAL(__cmpdi2)
430	cmpw	r3,r5
431	li	r3,1
432	bne	1f
433	cmplw	r4,r6
434	beqlr
4351:	li	r3,0
436	bltlr
437	li	r3,2
438	blr
439EXPORT_SYMBOL(__cmpdi2)
440/*
441 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
442 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
443 */
444_GLOBAL(__ucmpdi2)
445	cmplw	r3,r5
446	li	r3,1
447	bne	1f
448	cmplw	r4,r6
449	beqlr
4501:	li	r3,0
451	bltlr
452	li	r3,2
453	blr
454EXPORT_SYMBOL(__ucmpdi2)
455
456_GLOBAL(__bswapdi2)
457	rotlwi  r9,r4,8
458	rotlwi  r10,r3,8
459	rlwimi  r9,r4,24,0,7
460	rlwimi  r10,r3,24,0,7
461	rlwimi  r9,r4,24,16,23
462	rlwimi  r10,r3,24,16,23
463	mr      r3,r9
464	mr      r4,r10
465	blr
466EXPORT_SYMBOL(__bswapdi2)
467
468#ifdef CONFIG_SMP
469_GLOBAL(start_secondary_resume)
470	/* Reset stack */
471	rlwinm	r1, r1, 0, 0, 31 - THREAD_SHIFT
472	addi	r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
473	li	r3,0
474	stw	r3,0(r1)		/* Zero the stack frame pointer	*/
475	bl	start_secondary
476	b	.
477#endif /* CONFIG_SMP */
478
479/*
480 * This routine is just here to keep GCC happy - sigh...
481 */
482_GLOBAL(__main)
483	blr
484