1 /* 2 * Machine check exception handling CPU-side for power7 and power8 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * Copyright 2013 IBM Corporation 19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> 20 */ 21 22 #undef DEBUG 23 #define pr_fmt(fmt) "mce_power: " fmt 24 25 #include <linux/types.h> 26 #include <linux/ptrace.h> 27 #include <asm/mmu.h> 28 #include <asm/mce.h> 29 #include <asm/machdep.h> 30 #include <asm/pgtable.h> 31 #include <asm/pte-walk.h> 32 #include <asm/sstep.h> 33 #include <asm/exception-64s.h> 34 35 /* 36 * Convert an address related to an mm to a PFN. NOTE: we are in real 37 * mode, we could potentially race with page table updates. 38 */ 39 unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr) 40 { 41 pte_t *ptep; 42 unsigned long flags; 43 struct mm_struct *mm; 44 45 if (user_mode(regs)) 46 mm = current->mm; 47 else 48 mm = &init_mm; 49 50 local_irq_save(flags); 51 if (mm == current->mm) 52 ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL); 53 else 54 ptep = find_init_mm_pte(addr, NULL); 55 local_irq_restore(flags); 56 if (!ptep || pte_special(*ptep)) 57 return ULONG_MAX; 58 return pte_pfn(*ptep); 59 } 60 61 /* flush SLBs and reload */ 62 #ifdef CONFIG_PPC_BOOK3S_64 63 void flush_and_reload_slb(void) 64 { 65 /* Invalidate all SLBs */ 66 slb_flush_all_realmode(); 67 68 #ifdef CONFIG_KVM_BOOK3S_HANDLER 69 /* 70 * If machine check is hit when in guest or in transition, we will 71 * only flush the SLBs and continue. 72 */ 73 if (get_paca()->kvm_hstate.in_guest) 74 return; 75 #endif 76 if (early_radix_enabled()) 77 return; 78 79 /* 80 * This probably shouldn't happen, but it may be possible it's 81 * called in early boot before SLB shadows are allocated. 82 */ 83 if (!get_slb_shadow()) 84 return; 85 86 slb_restore_bolted_realmode(); 87 } 88 #endif 89 90 static void flush_erat(void) 91 { 92 #ifdef CONFIG_PPC_BOOK3S_64 93 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) { 94 flush_and_reload_slb(); 95 return; 96 } 97 #endif 98 /* PPC_INVALIDATE_ERAT can only be used on ISA v3 and newer */ 99 asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); 100 } 101 102 #define MCE_FLUSH_SLB 1 103 #define MCE_FLUSH_TLB 2 104 #define MCE_FLUSH_ERAT 3 105 106 static int mce_flush(int what) 107 { 108 #ifdef CONFIG_PPC_BOOK3S_64 109 if (what == MCE_FLUSH_SLB) { 110 flush_and_reload_slb(); 111 return 1; 112 } 113 #endif 114 if (what == MCE_FLUSH_ERAT) { 115 flush_erat(); 116 return 1; 117 } 118 if (what == MCE_FLUSH_TLB) { 119 tlbiel_all(); 120 return 1; 121 } 122 123 return 0; 124 } 125 126 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) 127 128 struct mce_ierror_table { 129 unsigned long srr1_mask; 130 unsigned long srr1_value; 131 bool nip_valid; /* nip is a valid indicator of faulting address */ 132 unsigned int error_type; 133 unsigned int error_subtype; 134 unsigned int error_class; 135 unsigned int initiator; 136 unsigned int severity; 137 bool sync_error; 138 }; 139 140 static const struct mce_ierror_table mce_p7_ierror_table[] = { 141 { 0x00000000001c0000, 0x0000000000040000, true, 142 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 143 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 144 { 0x00000000001c0000, 0x0000000000080000, true, 145 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 146 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 147 { 0x00000000001c0000, 0x00000000000c0000, true, 148 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 149 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 150 { 0x00000000001c0000, 0x0000000000100000, true, 151 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */ 152 MCE_ECLASS_SOFT_INDETERMINATE, 153 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 154 { 0x00000000001c0000, 0x0000000000140000, true, 155 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 156 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 157 { 0x00000000001c0000, 0x0000000000180000, true, 158 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE, 159 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 160 { 0x00000000001c0000, 0x00000000001c0000, true, 161 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 162 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 163 { 0, 0, 0, 0, 0, 0, 0 } }; 164 165 static const struct mce_ierror_table mce_p8_ierror_table[] = { 166 { 0x00000000081c0000, 0x0000000000040000, true, 167 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 168 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 169 { 0x00000000081c0000, 0x0000000000080000, true, 170 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 171 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 172 { 0x00000000081c0000, 0x00000000000c0000, true, 173 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 174 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 175 { 0x00000000081c0000, 0x0000000000100000, true, 176 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 177 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 178 { 0x00000000081c0000, 0x0000000000140000, true, 179 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 180 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 181 { 0x00000000081c0000, 0x0000000000180000, true, 182 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, 183 MCE_ECLASS_HARDWARE, 184 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 185 { 0x00000000081c0000, 0x00000000001c0000, true, 186 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 187 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 188 { 0x00000000081c0000, 0x0000000008000000, true, 189 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE, 190 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 191 { 0x00000000081c0000, 0x0000000008040000, true, 192 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT, 193 MCE_ECLASS_HARDWARE, 194 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 195 { 0, 0, 0, 0, 0, 0, 0 } }; 196 197 static const struct mce_ierror_table mce_p9_ierror_table[] = { 198 { 0x00000000081c0000, 0x0000000000040000, true, 199 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE, 200 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 201 { 0x00000000081c0000, 0x0000000000080000, true, 202 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 203 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 204 { 0x00000000081c0000, 0x00000000000c0000, true, 205 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 206 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 207 { 0x00000000081c0000, 0x0000000000100000, true, 208 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 209 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 210 { 0x00000000081c0000, 0x0000000000140000, true, 211 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 212 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 213 { 0x00000000081c0000, 0x0000000000180000, true, 214 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE, 215 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 216 { 0x00000000081c0000, 0x00000000001c0000, true, 217 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE, 218 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 219 { 0x00000000081c0000, 0x0000000008000000, true, 220 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE, 221 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 222 { 0x00000000081c0000, 0x0000000008040000, true, 223 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT, 224 MCE_ECLASS_HARDWARE, 225 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 226 { 0x00000000081c0000, 0x00000000080c0000, true, 227 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE, 228 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 229 { 0x00000000081c0000, 0x0000000008100000, true, 230 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE, 231 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 232 { 0x00000000081c0000, 0x0000000008140000, false, 233 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE, 234 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */ 235 { 0x00000000081c0000, 0x0000000008180000, false, 236 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT, 237 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */ 238 { 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE, 239 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN, 240 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 241 { 0, 0, 0, 0, 0, 0, 0 } }; 242 243 struct mce_derror_table { 244 unsigned long dsisr_value; 245 bool dar_valid; /* dar is a valid indicator of faulting address */ 246 unsigned int error_type; 247 unsigned int error_subtype; 248 unsigned int error_class; 249 unsigned int initiator; 250 unsigned int severity; 251 bool sync_error; 252 }; 253 254 static const struct mce_derror_table mce_p7_derror_table[] = { 255 { 0x00008000, false, 256 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE, 257 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 258 { 0x00004000, true, 259 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 260 MCE_ECLASS_HARDWARE, 261 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 262 { 0x00000800, true, 263 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 264 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 265 { 0x00000400, true, 266 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 267 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 268 { 0x00000080, true, 269 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 270 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 271 { 0x00000100, true, 272 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 273 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 274 { 0x00000040, true, 275 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */ 276 MCE_ECLASS_HARD_INDETERMINATE, 277 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 278 { 0, false, 0, 0, 0, 0, 0 } }; 279 280 static const struct mce_derror_table mce_p8_derror_table[] = { 281 { 0x00008000, false, 282 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE, 283 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 284 { 0x00004000, true, 285 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 286 MCE_ECLASS_HARDWARE, 287 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 288 { 0x00002000, true, 289 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE, 290 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 291 { 0x00001000, true, 292 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT, 293 MCE_ECLASS_HARDWARE, 294 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 295 { 0x00000800, true, 296 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 297 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 298 { 0x00000400, true, 299 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 300 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 301 { 0x00000200, true, 302 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */ 303 MCE_ECLASS_SOFT_INDETERMINATE, 304 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 305 { 0x00000080, true, 306 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */ 307 MCE_ECLASS_SOFT_INDETERMINATE, 308 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 309 { 0x00000100, true, 310 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 311 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 312 { 0, false, 0, 0, 0, 0, 0 } }; 313 314 static const struct mce_derror_table mce_p9_derror_table[] = { 315 { 0x00008000, false, 316 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE, 317 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 318 { 0x00004000, true, 319 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 320 MCE_ECLASS_HARDWARE, 321 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 322 { 0x00002000, true, 323 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE, 324 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 325 { 0x00001000, true, 326 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT, 327 MCE_ECLASS_HARDWARE, 328 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 329 { 0x00000800, true, 330 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 331 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 332 { 0x00000400, true, 333 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE, 334 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 335 { 0x00000200, false, 336 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE, 337 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 338 { 0x00000080, true, 339 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */ 340 MCE_ECLASS_SOFT_INDETERMINATE, 341 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true }, 342 { 0x00000100, true, 343 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE, 344 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 345 { 0x00000040, true, 346 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE, 347 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 348 { 0x00000020, false, 349 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE, 350 MCE_ECLASS_HARDWARE, 351 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 352 { 0x00000010, false, 353 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN, 354 MCE_ECLASS_HARDWARE, 355 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 356 { 0x00000008, false, 357 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE, 358 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true }, 359 { 0, false, 0, 0, 0, 0, 0 } }; 360 361 static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr, 362 uint64_t *phys_addr) 363 { 364 /* 365 * Carefully look at the NIP to determine 366 * the instruction to analyse. Reading the NIP 367 * in real-mode is tricky and can lead to recursive 368 * faults 369 */ 370 int instr; 371 unsigned long pfn, instr_addr; 372 struct instruction_op op; 373 struct pt_regs tmp = *regs; 374 375 pfn = addr_to_pfn(regs, regs->nip); 376 if (pfn != ULONG_MAX) { 377 instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK); 378 instr = *(unsigned int *)(instr_addr); 379 if (!analyse_instr(&op, &tmp, instr)) { 380 pfn = addr_to_pfn(regs, op.ea); 381 *addr = op.ea; 382 *phys_addr = (pfn << PAGE_SHIFT); 383 return 0; 384 } 385 /* 386 * analyse_instr() might fail if the instruction 387 * is not a load/store, although this is unexpected 388 * for load/store errors or if we got the NIP 389 * wrong 390 */ 391 } 392 *addr = 0; 393 return -1; 394 } 395 396 static int mce_handle_ierror(struct pt_regs *regs, 397 const struct mce_ierror_table table[], 398 struct mce_error_info *mce_err, uint64_t *addr, 399 uint64_t *phys_addr) 400 { 401 uint64_t srr1 = regs->msr; 402 int handled = 0; 403 int i; 404 405 *addr = 0; 406 407 for (i = 0; table[i].srr1_mask; i++) { 408 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value) 409 continue; 410 411 /* attempt to correct the error */ 412 switch (table[i].error_type) { 413 case MCE_ERROR_TYPE_SLB: 414 handled = mce_flush(MCE_FLUSH_SLB); 415 break; 416 case MCE_ERROR_TYPE_ERAT: 417 handled = mce_flush(MCE_FLUSH_ERAT); 418 break; 419 case MCE_ERROR_TYPE_TLB: 420 handled = mce_flush(MCE_FLUSH_TLB); 421 break; 422 } 423 424 /* now fill in mce_error_info */ 425 mce_err->error_type = table[i].error_type; 426 mce_err->error_class = table[i].error_class; 427 switch (table[i].error_type) { 428 case MCE_ERROR_TYPE_UE: 429 mce_err->u.ue_error_type = table[i].error_subtype; 430 break; 431 case MCE_ERROR_TYPE_SLB: 432 mce_err->u.slb_error_type = table[i].error_subtype; 433 break; 434 case MCE_ERROR_TYPE_ERAT: 435 mce_err->u.erat_error_type = table[i].error_subtype; 436 break; 437 case MCE_ERROR_TYPE_TLB: 438 mce_err->u.tlb_error_type = table[i].error_subtype; 439 break; 440 case MCE_ERROR_TYPE_USER: 441 mce_err->u.user_error_type = table[i].error_subtype; 442 break; 443 case MCE_ERROR_TYPE_RA: 444 mce_err->u.ra_error_type = table[i].error_subtype; 445 break; 446 case MCE_ERROR_TYPE_LINK: 447 mce_err->u.link_error_type = table[i].error_subtype; 448 break; 449 } 450 mce_err->sync_error = table[i].sync_error; 451 mce_err->severity = table[i].severity; 452 mce_err->initiator = table[i].initiator; 453 if (table[i].nip_valid) { 454 *addr = regs->nip; 455 if (mce_err->sync_error && 456 table[i].error_type == MCE_ERROR_TYPE_UE) { 457 unsigned long pfn; 458 459 if (get_paca()->in_mce < MAX_MCE_DEPTH) { 460 pfn = addr_to_pfn(regs, regs->nip); 461 if (pfn != ULONG_MAX) { 462 *phys_addr = 463 (pfn << PAGE_SHIFT); 464 } 465 } 466 } 467 } 468 return handled; 469 } 470 471 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN; 472 mce_err->error_class = MCE_ECLASS_UNKNOWN; 473 mce_err->severity = MCE_SEV_SEVERE; 474 mce_err->initiator = MCE_INITIATOR_CPU; 475 mce_err->sync_error = true; 476 477 return 0; 478 } 479 480 static int mce_handle_derror(struct pt_regs *regs, 481 const struct mce_derror_table table[], 482 struct mce_error_info *mce_err, uint64_t *addr, 483 uint64_t *phys_addr) 484 { 485 uint64_t dsisr = regs->dsisr; 486 int handled = 0; 487 int found = 0; 488 int i; 489 490 *addr = 0; 491 492 for (i = 0; table[i].dsisr_value; i++) { 493 if (!(dsisr & table[i].dsisr_value)) 494 continue; 495 496 /* attempt to correct the error */ 497 switch (table[i].error_type) { 498 case MCE_ERROR_TYPE_SLB: 499 if (mce_flush(MCE_FLUSH_SLB)) 500 handled = 1; 501 break; 502 case MCE_ERROR_TYPE_ERAT: 503 if (mce_flush(MCE_FLUSH_ERAT)) 504 handled = 1; 505 break; 506 case MCE_ERROR_TYPE_TLB: 507 if (mce_flush(MCE_FLUSH_TLB)) 508 handled = 1; 509 break; 510 } 511 512 /* 513 * Attempt to handle multiple conditions, but only return 514 * one. Ensure uncorrectable errors are first in the table 515 * to match. 516 */ 517 if (found) 518 continue; 519 520 /* now fill in mce_error_info */ 521 mce_err->error_type = table[i].error_type; 522 mce_err->error_class = table[i].error_class; 523 switch (table[i].error_type) { 524 case MCE_ERROR_TYPE_UE: 525 mce_err->u.ue_error_type = table[i].error_subtype; 526 break; 527 case MCE_ERROR_TYPE_SLB: 528 mce_err->u.slb_error_type = table[i].error_subtype; 529 break; 530 case MCE_ERROR_TYPE_ERAT: 531 mce_err->u.erat_error_type = table[i].error_subtype; 532 break; 533 case MCE_ERROR_TYPE_TLB: 534 mce_err->u.tlb_error_type = table[i].error_subtype; 535 break; 536 case MCE_ERROR_TYPE_USER: 537 mce_err->u.user_error_type = table[i].error_subtype; 538 break; 539 case MCE_ERROR_TYPE_RA: 540 mce_err->u.ra_error_type = table[i].error_subtype; 541 break; 542 case MCE_ERROR_TYPE_LINK: 543 mce_err->u.link_error_type = table[i].error_subtype; 544 break; 545 } 546 mce_err->sync_error = table[i].sync_error; 547 mce_err->severity = table[i].severity; 548 mce_err->initiator = table[i].initiator; 549 if (table[i].dar_valid) 550 *addr = regs->dar; 551 else if (mce_err->sync_error && 552 table[i].error_type == MCE_ERROR_TYPE_UE) { 553 /* 554 * We do a maximum of 4 nested MCE calls, see 555 * kernel/exception-64s.h 556 */ 557 if (get_paca()->in_mce < MAX_MCE_DEPTH) 558 mce_find_instr_ea_and_pfn(regs, addr, phys_addr); 559 } 560 found = 1; 561 } 562 563 if (found) 564 return handled; 565 566 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN; 567 mce_err->error_class = MCE_ECLASS_UNKNOWN; 568 mce_err->severity = MCE_SEV_SEVERE; 569 mce_err->initiator = MCE_INITIATOR_CPU; 570 mce_err->sync_error = true; 571 572 return 0; 573 } 574 575 static long mce_handle_ue_error(struct pt_regs *regs) 576 { 577 long handled = 0; 578 579 /* 580 * On specific SCOM read via MMIO we may get a machine check 581 * exception with SRR0 pointing inside opal. If that is the 582 * case OPAL may have recovery address to re-read SCOM data in 583 * different way and hence we can recover from this MC. 584 */ 585 586 if (ppc_md.mce_check_early_recovery) { 587 if (ppc_md.mce_check_early_recovery(regs)) 588 handled = 1; 589 } 590 return handled; 591 } 592 593 static long mce_handle_error(struct pt_regs *regs, 594 const struct mce_derror_table dtable[], 595 const struct mce_ierror_table itable[]) 596 { 597 struct mce_error_info mce_err = { 0 }; 598 uint64_t addr, phys_addr = ULONG_MAX; 599 uint64_t srr1 = regs->msr; 600 long handled; 601 602 if (SRR1_MC_LOADSTORE(srr1)) 603 handled = mce_handle_derror(regs, dtable, &mce_err, &addr, 604 &phys_addr); 605 else 606 handled = mce_handle_ierror(regs, itable, &mce_err, &addr, 607 &phys_addr); 608 609 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE) 610 handled = mce_handle_ue_error(regs); 611 612 save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr); 613 614 return handled; 615 } 616 617 long __machine_check_early_realmode_p7(struct pt_regs *regs) 618 { 619 /* P7 DD1 leaves top bits of DSISR undefined */ 620 regs->dsisr &= 0x0000ffff; 621 622 return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table); 623 } 624 625 long __machine_check_early_realmode_p8(struct pt_regs *regs) 626 { 627 return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table); 628 } 629 630 long __machine_check_early_realmode_p9(struct pt_regs *regs) 631 { 632 /* 633 * On POWER9 DD2.1 and below, it's possible to get a machine check 634 * caused by a paste instruction where only DSISR bit 25 is set. This 635 * will result in the MCE handler seeing an unknown event and the kernel 636 * crashing. An MCE that occurs like this is spurious, so we don't need 637 * to do anything in terms of servicing it. If there is something that 638 * needs to be serviced, the CPU will raise the MCE again with the 639 * correct DSISR so that it can be serviced properly. So detect this 640 * case and mark it as handled. 641 */ 642 if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000) 643 return 1; 644 645 return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table); 646 } 647