1 /* 2 * Machine check exception handling CPU-side for power7 and power8 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * Copyright 2013 IBM Corporation 19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> 20 */ 21 22 #undef DEBUG 23 #define pr_fmt(fmt) "mce_power: " fmt 24 25 #include <linux/types.h> 26 #include <linux/ptrace.h> 27 #include <asm/mmu.h> 28 #include <asm/mce.h> 29 #include <asm/machdep.h> 30 31 static void flush_tlb_206(unsigned int num_sets, unsigned int action) 32 { 33 unsigned long rb; 34 unsigned int i; 35 36 switch (action) { 37 case TLB_INVAL_SCOPE_GLOBAL: 38 rb = TLBIEL_INVAL_SET; 39 break; 40 case TLB_INVAL_SCOPE_LPID: 41 rb = TLBIEL_INVAL_SET_LPID; 42 break; 43 default: 44 BUG(); 45 break; 46 } 47 48 asm volatile("ptesync" : : : "memory"); 49 for (i = 0; i < num_sets; i++) { 50 asm volatile("tlbiel %0" : : "r" (rb)); 51 rb += 1 << TLBIEL_INVAL_SET_SHIFT; 52 } 53 asm volatile("ptesync" : : : "memory"); 54 } 55 56 /* 57 * Generic routines to flush TLB on POWER processors. These routines 58 * are used as flush_tlb hook in the cpu_spec. 59 * 60 * action => TLB_INVAL_SCOPE_GLOBAL: Invalidate all TLBs. 61 * TLB_INVAL_SCOPE_LPID: Invalidate TLB for current LPID. 62 */ 63 void __flush_tlb_power7(unsigned int action) 64 { 65 flush_tlb_206(POWER7_TLB_SETS, action); 66 } 67 68 void __flush_tlb_power8(unsigned int action) 69 { 70 flush_tlb_206(POWER8_TLB_SETS, action); 71 } 72 73 void __flush_tlb_power9(unsigned int action) 74 { 75 if (radix_enabled()) 76 flush_tlb_206(POWER9_TLB_SETS_RADIX, action); 77 78 flush_tlb_206(POWER9_TLB_SETS_HASH, action); 79 } 80 81 82 /* flush SLBs and reload */ 83 #ifdef CONFIG_PPC_STD_MMU_64 84 static void flush_and_reload_slb(void) 85 { 86 struct slb_shadow *slb; 87 unsigned long i, n; 88 89 /* Invalidate all SLBs */ 90 asm volatile("slbmte %0,%0; slbia" : : "r" (0)); 91 92 #ifdef CONFIG_KVM_BOOK3S_HANDLER 93 /* 94 * If machine check is hit when in guest or in transition, we will 95 * only flush the SLBs and continue. 96 */ 97 if (get_paca()->kvm_hstate.in_guest) 98 return; 99 #endif 100 101 /* For host kernel, reload the SLBs from shadow SLB buffer. */ 102 slb = get_slb_shadow(); 103 if (!slb) 104 return; 105 106 n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE); 107 108 /* Load up the SLB entries from shadow SLB */ 109 for (i = 0; i < n; i++) { 110 unsigned long rb = be64_to_cpu(slb->save_area[i].esid); 111 unsigned long rs = be64_to_cpu(slb->save_area[i].vsid); 112 113 rb = (rb & ~0xFFFul) | i; 114 asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb)); 115 } 116 } 117 #endif 118 119 static void flush_erat(void) 120 { 121 asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); 122 } 123 124 #define MCE_FLUSH_SLB 1 125 #define MCE_FLUSH_TLB 2 126 #define MCE_FLUSH_ERAT 3 127 128 static int mce_flush(int what) 129 { 130 #ifdef CONFIG_PPC_STD_MMU_64 131 if (what == MCE_FLUSH_SLB) { 132 flush_and_reload_slb(); 133 return 1; 134 } 135 #endif 136 if (what == MCE_FLUSH_ERAT) { 137 flush_erat(); 138 return 1; 139 } 140 if (what == MCE_FLUSH_TLB) { 141 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) { 142 cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); 143 return 1; 144 } 145 } 146 147 return 0; 148 } 149 150 static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb, uint64_t erat) 151 { 152 if ((dsisr & slb) && mce_flush(MCE_FLUSH_SLB)) 153 dsisr &= ~slb; 154 if ((dsisr & erat) && mce_flush(MCE_FLUSH_ERAT)) 155 dsisr &= ~erat; 156 if ((dsisr & tlb) && mce_flush(MCE_FLUSH_TLB)) 157 dsisr &= ~tlb; 158 /* Any other errors we don't understand? */ 159 if (dsisr) 160 return 0; 161 return 1; 162 } 163 164 static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits) 165 { 166 long handled = 1; 167 168 /* 169 * flush and reload SLBs for SLB errors and flush TLBs for TLB errors. 170 * reset the error bits whenever we handle them so that at the end 171 * we can check whether we handled all of them or not. 172 * */ 173 #ifdef CONFIG_PPC_STD_MMU_64 174 if (dsisr & slb_error_bits) { 175 flush_and_reload_slb(); 176 /* reset error bits */ 177 dsisr &= ~(slb_error_bits); 178 } 179 if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) { 180 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) 181 cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); 182 /* reset error bits */ 183 dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB; 184 } 185 #endif 186 /* Any other errors we don't understand? */ 187 if (dsisr & 0xffffffffUL) 188 handled = 0; 189 190 return handled; 191 } 192 193 static long mce_handle_derror_p7(uint64_t dsisr) 194 { 195 return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS); 196 } 197 198 static long mce_handle_common_ierror(uint64_t srr1) 199 { 200 long handled = 0; 201 202 switch (P7_SRR1_MC_IFETCH(srr1)) { 203 case 0: 204 break; 205 #ifdef CONFIG_PPC_STD_MMU_64 206 case P7_SRR1_MC_IFETCH_SLB_PARITY: 207 case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: 208 /* flush and reload SLBs for SLB errors. */ 209 flush_and_reload_slb(); 210 handled = 1; 211 break; 212 case P7_SRR1_MC_IFETCH_TLB_MULTIHIT: 213 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) { 214 cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL); 215 handled = 1; 216 } 217 break; 218 #endif 219 default: 220 break; 221 } 222 223 return handled; 224 } 225 226 static long mce_handle_ierror_p7(uint64_t srr1) 227 { 228 long handled = 0; 229 230 handled = mce_handle_common_ierror(srr1); 231 232 #ifdef CONFIG_PPC_STD_MMU_64 233 if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) { 234 flush_and_reload_slb(); 235 handled = 1; 236 } 237 #endif 238 return handled; 239 } 240 241 static void mce_get_common_ierror(struct mce_error_info *mce_err, uint64_t srr1) 242 { 243 switch (P7_SRR1_MC_IFETCH(srr1)) { 244 case P7_SRR1_MC_IFETCH_SLB_PARITY: 245 mce_err->error_type = MCE_ERROR_TYPE_SLB; 246 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY; 247 break; 248 case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: 249 mce_err->error_type = MCE_ERROR_TYPE_SLB; 250 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT; 251 break; 252 case P7_SRR1_MC_IFETCH_TLB_MULTIHIT: 253 mce_err->error_type = MCE_ERROR_TYPE_TLB; 254 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT; 255 break; 256 case P7_SRR1_MC_IFETCH_UE: 257 case P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL: 258 mce_err->error_type = MCE_ERROR_TYPE_UE; 259 mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH; 260 break; 261 case P7_SRR1_MC_IFETCH_UE_TLB_RELOAD: 262 mce_err->error_type = MCE_ERROR_TYPE_UE; 263 mce_err->u.ue_error_type = 264 MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH; 265 break; 266 } 267 } 268 269 static void mce_get_ierror_p7(struct mce_error_info *mce_err, uint64_t srr1) 270 { 271 mce_get_common_ierror(mce_err, srr1); 272 if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) { 273 mce_err->error_type = MCE_ERROR_TYPE_SLB; 274 mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE; 275 } 276 } 277 278 static void mce_get_derror_p7(struct mce_error_info *mce_err, uint64_t dsisr) 279 { 280 if (dsisr & P7_DSISR_MC_UE) { 281 mce_err->error_type = MCE_ERROR_TYPE_UE; 282 mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE; 283 } else if (dsisr & P7_DSISR_MC_UE_TABLEWALK) { 284 mce_err->error_type = MCE_ERROR_TYPE_UE; 285 mce_err->u.ue_error_type = 286 MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE; 287 } else if (dsisr & P7_DSISR_MC_ERAT_MULTIHIT) { 288 mce_err->error_type = MCE_ERROR_TYPE_ERAT; 289 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT; 290 } else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT) { 291 mce_err->error_type = MCE_ERROR_TYPE_SLB; 292 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT; 293 } else if (dsisr & P7_DSISR_MC_SLB_PARITY_MFSLB) { 294 mce_err->error_type = MCE_ERROR_TYPE_SLB; 295 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY; 296 } else if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) { 297 mce_err->error_type = MCE_ERROR_TYPE_TLB; 298 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT; 299 } else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT_PARITY) { 300 mce_err->error_type = MCE_ERROR_TYPE_SLB; 301 mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE; 302 } 303 } 304 305 static long mce_handle_ue_error(struct pt_regs *regs) 306 { 307 long handled = 0; 308 309 /* 310 * On specific SCOM read via MMIO we may get a machine check 311 * exception with SRR0 pointing inside opal. If that is the 312 * case OPAL may have recovery address to re-read SCOM data in 313 * different way and hence we can recover from this MC. 314 */ 315 316 if (ppc_md.mce_check_early_recovery) { 317 if (ppc_md.mce_check_early_recovery(regs)) 318 handled = 1; 319 } 320 return handled; 321 } 322 323 long __machine_check_early_realmode_p7(struct pt_regs *regs) 324 { 325 uint64_t srr1, nip, addr; 326 long handled = 1; 327 struct mce_error_info mce_error_info = { 0 }; 328 329 mce_error_info.severity = MCE_SEV_ERROR_SYNC; 330 mce_error_info.initiator = MCE_INITIATOR_CPU; 331 332 srr1 = regs->msr; 333 nip = regs->nip; 334 335 /* 336 * Handle memory errors depending whether this was a load/store or 337 * ifetch exception. Also, populate the mce error_type and 338 * type-specific error_type from either SRR1 or DSISR, depending 339 * whether this was a load/store or ifetch exception 340 */ 341 if (P7_SRR1_MC_LOADSTORE(srr1)) { 342 handled = mce_handle_derror_p7(regs->dsisr); 343 mce_get_derror_p7(&mce_error_info, regs->dsisr); 344 addr = regs->dar; 345 } else { 346 handled = mce_handle_ierror_p7(srr1); 347 mce_get_ierror_p7(&mce_error_info, srr1); 348 addr = regs->nip; 349 } 350 351 /* Handle UE error. */ 352 if (mce_error_info.error_type == MCE_ERROR_TYPE_UE) 353 handled = mce_handle_ue_error(regs); 354 355 save_mce_event(regs, handled, &mce_error_info, nip, addr); 356 return handled; 357 } 358 359 static void mce_get_ierror_p8(struct mce_error_info *mce_err, uint64_t srr1) 360 { 361 mce_get_common_ierror(mce_err, srr1); 362 if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) { 363 mce_err->error_type = MCE_ERROR_TYPE_ERAT; 364 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT; 365 } 366 } 367 368 static void mce_get_derror_p8(struct mce_error_info *mce_err, uint64_t dsisr) 369 { 370 mce_get_derror_p7(mce_err, dsisr); 371 if (dsisr & P8_DSISR_MC_ERAT_MULTIHIT_SEC) { 372 mce_err->error_type = MCE_ERROR_TYPE_ERAT; 373 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT; 374 } 375 } 376 377 static long mce_handle_ierror_p8(uint64_t srr1) 378 { 379 long handled = 0; 380 381 handled = mce_handle_common_ierror(srr1); 382 383 #ifdef CONFIG_PPC_STD_MMU_64 384 if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) { 385 flush_and_reload_slb(); 386 handled = 1; 387 } 388 #endif 389 return handled; 390 } 391 392 static long mce_handle_derror_p8(uint64_t dsisr) 393 { 394 return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS); 395 } 396 397 long __machine_check_early_realmode_p8(struct pt_regs *regs) 398 { 399 uint64_t srr1, nip, addr; 400 long handled = 1; 401 struct mce_error_info mce_error_info = { 0 }; 402 403 mce_error_info.severity = MCE_SEV_ERROR_SYNC; 404 mce_error_info.initiator = MCE_INITIATOR_CPU; 405 406 srr1 = regs->msr; 407 nip = regs->nip; 408 409 if (P7_SRR1_MC_LOADSTORE(srr1)) { 410 handled = mce_handle_derror_p8(regs->dsisr); 411 mce_get_derror_p8(&mce_error_info, regs->dsisr); 412 addr = regs->dar; 413 } else { 414 handled = mce_handle_ierror_p8(srr1); 415 mce_get_ierror_p8(&mce_error_info, srr1); 416 addr = regs->nip; 417 } 418 419 /* Handle UE error. */ 420 if (mce_error_info.error_type == MCE_ERROR_TYPE_UE) 421 handled = mce_handle_ue_error(regs); 422 423 save_mce_event(regs, handled, &mce_error_info, nip, addr); 424 return handled; 425 } 426 427 static int mce_handle_derror_p9(struct pt_regs *regs) 428 { 429 uint64_t dsisr = regs->dsisr; 430 431 return mce_handle_flush_derrors(dsisr, 432 P9_DSISR_MC_SLB_PARITY_MFSLB | 433 P9_DSISR_MC_SLB_MULTIHIT_MFSLB, 434 435 P9_DSISR_MC_TLB_MULTIHIT_MFTLB, 436 437 P9_DSISR_MC_ERAT_MULTIHIT); 438 } 439 440 static int mce_handle_ierror_p9(struct pt_regs *regs) 441 { 442 uint64_t srr1 = regs->msr; 443 444 switch (P9_SRR1_MC_IFETCH(srr1)) { 445 case P9_SRR1_MC_IFETCH_SLB_PARITY: 446 case P9_SRR1_MC_IFETCH_SLB_MULTIHIT: 447 return mce_flush(MCE_FLUSH_SLB); 448 case P9_SRR1_MC_IFETCH_TLB_MULTIHIT: 449 return mce_flush(MCE_FLUSH_TLB); 450 case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT: 451 return mce_flush(MCE_FLUSH_ERAT); 452 default: 453 return 0; 454 } 455 } 456 457 static void mce_get_derror_p9(struct pt_regs *regs, 458 struct mce_error_info *mce_err, uint64_t *addr) 459 { 460 uint64_t dsisr = regs->dsisr; 461 462 mce_err->severity = MCE_SEV_ERROR_SYNC; 463 mce_err->initiator = MCE_INITIATOR_CPU; 464 465 if (dsisr & P9_DSISR_MC_USER_TLBIE) 466 *addr = regs->nip; 467 else 468 *addr = regs->dar; 469 470 if (dsisr & P9_DSISR_MC_UE) { 471 mce_err->error_type = MCE_ERROR_TYPE_UE; 472 mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE; 473 } else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) { 474 mce_err->error_type = MCE_ERROR_TYPE_UE; 475 mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE; 476 } else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) { 477 mce_err->error_type = MCE_ERROR_TYPE_LINK; 478 mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT; 479 } else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) { 480 mce_err->error_type = MCE_ERROR_TYPE_LINK; 481 mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT; 482 } else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) { 483 mce_err->error_type = MCE_ERROR_TYPE_ERAT; 484 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT; 485 } else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) { 486 mce_err->error_type = MCE_ERROR_TYPE_TLB; 487 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT; 488 } else if (dsisr & P9_DSISR_MC_USER_TLBIE) { 489 mce_err->error_type = MCE_ERROR_TYPE_USER; 490 mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE; 491 } else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) { 492 mce_err->error_type = MCE_ERROR_TYPE_SLB; 493 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY; 494 } else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) { 495 mce_err->error_type = MCE_ERROR_TYPE_SLB; 496 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT; 497 } else if (dsisr & P9_DSISR_MC_RA_LOAD) { 498 mce_err->error_type = MCE_ERROR_TYPE_RA; 499 mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD; 500 } else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) { 501 mce_err->error_type = MCE_ERROR_TYPE_RA; 502 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE; 503 } else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) { 504 mce_err->error_type = MCE_ERROR_TYPE_RA; 505 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN; 506 } else if (dsisr & P9_DSISR_MC_RA_FOREIGN) { 507 mce_err->error_type = MCE_ERROR_TYPE_RA; 508 mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN; 509 } 510 } 511 512 static void mce_get_ierror_p9(struct pt_regs *regs, 513 struct mce_error_info *mce_err, uint64_t *addr) 514 { 515 uint64_t srr1 = regs->msr; 516 517 switch (P9_SRR1_MC_IFETCH(srr1)) { 518 case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE: 519 case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT: 520 mce_err->severity = MCE_SEV_FATAL; 521 break; 522 default: 523 mce_err->severity = MCE_SEV_ERROR_SYNC; 524 break; 525 } 526 527 mce_err->initiator = MCE_INITIATOR_CPU; 528 529 *addr = regs->nip; 530 531 switch (P9_SRR1_MC_IFETCH(srr1)) { 532 case P9_SRR1_MC_IFETCH_UE: 533 mce_err->error_type = MCE_ERROR_TYPE_UE; 534 mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH; 535 break; 536 case P9_SRR1_MC_IFETCH_SLB_PARITY: 537 mce_err->error_type = MCE_ERROR_TYPE_SLB; 538 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY; 539 break; 540 case P9_SRR1_MC_IFETCH_SLB_MULTIHIT: 541 mce_err->error_type = MCE_ERROR_TYPE_SLB; 542 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT; 543 break; 544 case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT: 545 mce_err->error_type = MCE_ERROR_TYPE_ERAT; 546 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT; 547 break; 548 case P9_SRR1_MC_IFETCH_TLB_MULTIHIT: 549 mce_err->error_type = MCE_ERROR_TYPE_TLB; 550 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT; 551 break; 552 case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD: 553 mce_err->error_type = MCE_ERROR_TYPE_UE; 554 mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH; 555 break; 556 case P9_SRR1_MC_IFETCH_LINK_TIMEOUT: 557 mce_err->error_type = MCE_ERROR_TYPE_LINK; 558 mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT; 559 break; 560 case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT: 561 mce_err->error_type = MCE_ERROR_TYPE_LINK; 562 mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT; 563 break; 564 case P9_SRR1_MC_IFETCH_RA: 565 mce_err->error_type = MCE_ERROR_TYPE_RA; 566 mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH; 567 break; 568 case P9_SRR1_MC_IFETCH_RA_TABLEWALK: 569 mce_err->error_type = MCE_ERROR_TYPE_RA; 570 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH; 571 break; 572 case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE: 573 mce_err->error_type = MCE_ERROR_TYPE_RA; 574 mce_err->u.ra_error_type = MCE_RA_ERROR_STORE; 575 break; 576 case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT: 577 mce_err->error_type = MCE_ERROR_TYPE_LINK; 578 mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT; 579 break; 580 case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN: 581 mce_err->error_type = MCE_ERROR_TYPE_RA; 582 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN; 583 break; 584 default: 585 break; 586 } 587 } 588 589 long __machine_check_early_realmode_p9(struct pt_regs *regs) 590 { 591 uint64_t nip, addr; 592 long handled; 593 struct mce_error_info mce_error_info = { 0 }; 594 595 nip = regs->nip; 596 597 if (P9_SRR1_MC_LOADSTORE(regs->msr)) { 598 handled = mce_handle_derror_p9(regs); 599 mce_get_derror_p9(regs, &mce_error_info, &addr); 600 } else { 601 handled = mce_handle_ierror_p9(regs); 602 mce_get_ierror_p9(regs, &mce_error_info, &addr); 603 } 604 605 /* Handle UE error. */ 606 if (mce_error_info.error_type == MCE_ERROR_TYPE_UE) 607 handled = mce_handle_ue_error(regs); 608 609 save_mce_event(regs, handled, &mce_error_info, nip, addr); 610 return handled; 611 } 612