1/* 2 * This file contains idle entry/exit functions for POWER7, 3 * POWER8 and POWER9 CPUs. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 11#include <linux/threads.h> 12#include <asm/processor.h> 13#include <asm/page.h> 14#include <asm/cputable.h> 15#include <asm/thread_info.h> 16#include <asm/ppc_asm.h> 17#include <asm/asm-offsets.h> 18#include <asm/ppc-opcode.h> 19#include <asm/hw_irq.h> 20#include <asm/kvm_book3s_asm.h> 21#include <asm/opal.h> 22#include <asm/cpuidle.h> 23#include <asm/exception-64s.h> 24#include <asm/book3s/64/mmu-hash.h> 25#include <asm/mmu.h> 26 27#undef DEBUG 28 29/* 30 * Use unused space in the interrupt stack to save and restore 31 * registers for winkle support. 32 */ 33#define _MMCR0 GPR0 34#define _SDR1 GPR3 35#define _PTCR GPR3 36#define _RPR GPR4 37#define _SPURR GPR5 38#define _PURR GPR6 39#define _TSCR GPR7 40#define _DSCR GPR8 41#define _AMOR GPR9 42#define _WORT GPR10 43#define _WORC GPR11 44#define _LPCR GPR12 45 46#define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16 47 48 .text 49 50/* 51 * Used by threads before entering deep idle states. Saves SPRs 52 * in interrupt stack frame 53 */ 54save_sprs_to_stack: 55 /* 56 * Note all register i.e per-core, per-subcore or per-thread is saved 57 * here since any thread in the core might wake up first 58 */ 59BEGIN_FTR_SECTION 60 /* 61 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring 62 * SDR1 here 63 */ 64 mfspr r3,SPRN_PTCR 65 std r3,_PTCR(r1) 66 mfspr r3,SPRN_LPCR 67 std r3,_LPCR(r1) 68FTR_SECTION_ELSE 69 mfspr r3,SPRN_SDR1 70 std r3,_SDR1(r1) 71ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) 72 mfspr r3,SPRN_RPR 73 std r3,_RPR(r1) 74 mfspr r3,SPRN_SPURR 75 std r3,_SPURR(r1) 76 mfspr r3,SPRN_PURR 77 std r3,_PURR(r1) 78 mfspr r3,SPRN_TSCR 79 std r3,_TSCR(r1) 80 mfspr r3,SPRN_DSCR 81 std r3,_DSCR(r1) 82 mfspr r3,SPRN_AMOR 83 std r3,_AMOR(r1) 84 mfspr r3,SPRN_WORT 85 std r3,_WORT(r1) 86 mfspr r3,SPRN_WORC 87 std r3,_WORC(r1) 88/* 89 * On POWER9, there are idle states such as stop4, invoked via cpuidle, 90 * that lose hypervisor resources. In such cases, we need to save 91 * additional SPRs before entering those idle states so that they can 92 * be restored to their older values on wakeup from the idle state. 93 * 94 * On POWER8, the only such deep idle state is winkle which is used 95 * only in the context of CPU-Hotplug, where these additional SPRs are 96 * reinitiazed to a sane value. Hence there is no need to save/restore 97 * these SPRs. 98 */ 99BEGIN_FTR_SECTION 100 blr 101END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) 102 103power9_save_additional_sprs: 104 mfspr r3, SPRN_PID 105 mfspr r4, SPRN_LDBAR 106 std r3, STOP_PID(r13) 107 std r4, STOP_LDBAR(r13) 108 109 mfspr r3, SPRN_FSCR 110 mfspr r4, SPRN_HFSCR 111 std r3, STOP_FSCR(r13) 112 std r4, STOP_HFSCR(r13) 113 114 mfspr r3, SPRN_MMCRA 115 mfspr r4, SPRN_MMCR0 116 std r3, STOP_MMCRA(r13) 117 std r4, _MMCR0(r1) 118 119 mfspr r3, SPRN_MMCR1 120 mfspr r4, SPRN_MMCR2 121 std r3, STOP_MMCR1(r13) 122 std r4, STOP_MMCR2(r13) 123 blr 124 125power9_restore_additional_sprs: 126 ld r3,_LPCR(r1) 127 ld r4, STOP_PID(r13) 128 mtspr SPRN_LPCR,r3 129 mtspr SPRN_PID, r4 130 131 ld r3, STOP_LDBAR(r13) 132 ld r4, STOP_FSCR(r13) 133 mtspr SPRN_LDBAR, r3 134 mtspr SPRN_FSCR, r4 135 136 ld r3, STOP_HFSCR(r13) 137 ld r4, STOP_MMCRA(r13) 138 mtspr SPRN_HFSCR, r3 139 mtspr SPRN_MMCRA, r4 140 141 ld r3, _MMCR0(r1) 142 ld r4, STOP_MMCR1(r13) 143 mtspr SPRN_MMCR0, r3 144 mtspr SPRN_MMCR1, r4 145 146 ld r3, STOP_MMCR2(r13) 147 mtspr SPRN_MMCR2, r3 148 blr 149 150/* 151 * Used by threads when the lock bit of core_idle_state is set. 152 * Threads will spin in HMT_LOW until the lock bit is cleared. 153 * r14 - pointer to core_idle_state 154 * r15 - used to load contents of core_idle_state 155 * r9 - used as a temporary variable 156 */ 157 158core_idle_lock_held: 159 HMT_LOW 1603: lwz r15,0(r14) 161 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 162 bne 3b 163 HMT_MEDIUM 164 lwarx r15,0,r14 165 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 166 bne- core_idle_lock_held 167 blr 168 169/* 170 * Pass requested state in r3: 171 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8 172 * - Requested PSSCR value in POWER9 173 * 174 * Address of idle handler to branch to in realmode in r4 175 */ 176pnv_powersave_common: 177 /* Use r3 to pass state nap/sleep/winkle */ 178 /* NAP is a state loss, we create a regs frame on the 179 * stack, fill it up with the state we care about and 180 * stick a pointer to it in PACAR1. We really only 181 * need to save PC, some CR bits and the NV GPRs, 182 * but for now an interrupt frame will do. 183 */ 184 mtctr r4 185 186 mflr r0 187 std r0,16(r1) 188 stdu r1,-INT_FRAME_SIZE(r1) 189 std r0,_LINK(r1) 190 std r0,_NIP(r1) 191 192 /* We haven't lost state ... yet */ 193 li r0,0 194 stb r0,PACA_NAPSTATELOST(r13) 195 196 /* Continue saving state */ 197 SAVE_GPR(2, r1) 198 SAVE_NVGPRS(r1) 199 mfcr r5 200 std r5,_CCR(r1) 201 std r1,PACAR1(r13) 202 203BEGIN_FTR_SECTION 204 /* 205 * POWER9 does not require real mode to stop, and presently does not 206 * set hwthread_state for KVM (threads don't share MMU context), so 207 * we can remain in virtual mode for this. 208 */ 209 bctr 210END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) 211 /* 212 * POWER8 213 * Go to real mode to do the nap, as required by the architecture. 214 * Also, we need to be in real mode before setting hwthread_state, 215 * because as soon as we do that, another thread can switch 216 * the MMU context to the guest. 217 */ 218 LOAD_REG_IMMEDIATE(r7, MSR_IDLE) 219 mtmsrd r7,0 220 bctr 221 222/* 223 * This is the sequence required to execute idle instructions, as 224 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0. 225 */ 226#define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \ 227 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ 228 std r0,0(r1); \ 229 ptesync; \ 230 ld r0,0(r1); \ 231236: cmpd cr0,r0,r0; \ 232 bne 236b; \ 233 IDLE_INST; 234 235 236 .globl pnv_enter_arch207_idle_mode 237pnv_enter_arch207_idle_mode: 238#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 239 /* Tell KVM we're entering idle */ 240 li r4,KVM_HWTHREAD_IN_IDLE 241 /******************************************************/ 242 /* N O T E W E L L ! ! ! N O T E W E L L */ 243 /* The following store to HSTATE_HWTHREAD_STATE(r13) */ 244 /* MUST occur in real mode, i.e. with the MMU off, */ 245 /* and the MMU must stay off until we clear this flag */ 246 /* and test HSTATE_HWTHREAD_REQ(r13) in */ 247 /* pnv_powersave_wakeup in this file. */ 248 /* The reason is that another thread can switch the */ 249 /* MMU to a guest context whenever this flag is set */ 250 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ 251 /* that would potentially cause this thread to start */ 252 /* executing instructions from guest memory in */ 253 /* hypervisor mode, leading to a host crash or data */ 254 /* corruption, or worse. */ 255 /******************************************************/ 256 stb r4,HSTATE_HWTHREAD_STATE(r13) 257#endif 258 stb r3,PACA_THREAD_IDLE_STATE(r13) 259 cmpwi cr3,r3,PNV_THREAD_SLEEP 260 bge cr3,2f 261 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) 262 /* No return */ 2632: 264 /* Sleep or winkle */ 265 lbz r7,PACA_THREAD_MASK(r13) 266 ld r14,PACA_CORE_IDLE_STATE_PTR(r13) 267 li r5,0 268 beq cr3,3f 269 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h 2703: 271lwarx_loop1: 272 lwarx r15,0,r14 273 274 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 275 bnel- core_idle_lock_held 276 277 add r15,r15,r5 /* Add if winkle */ 278 andc r15,r15,r7 /* Clear thread bit */ 279 280 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS 281 282/* 283 * If cr0 = 0, then current thread is the last thread of the core entering 284 * sleep. Last thread needs to execute the hardware bug workaround code if 285 * required by the platform. 286 * Make the workaround call unconditionally here. The below branch call is 287 * patched out when the idle states are discovered if the platform does not 288 * require it. 289 */ 290.global pnv_fastsleep_workaround_at_entry 291pnv_fastsleep_workaround_at_entry: 292 beq fastsleep_workaround_at_entry 293 294 stwcx. r15,0,r14 295 bne- lwarx_loop1 296 isync 297 298common_enter: /* common code for all the threads entering sleep or winkle */ 299 bgt cr3,enter_winkle 300 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) 301 302fastsleep_workaround_at_entry: 303 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 304 stwcx. r15,0,r14 305 bne- lwarx_loop1 306 isync 307 308 /* Fast sleep workaround */ 309 li r3,1 310 li r4,1 311 bl opal_config_cpu_idle_state 312 313 /* Unlock */ 314 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 315 lwsync 316 stw r15,0(r14) 317 b common_enter 318 319enter_winkle: 320 bl save_sprs_to_stack 321 322 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) 323 324/* 325 * r3 - PSSCR value corresponding to the requested stop state. 326 */ 327power_enter_stop: 328#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 329 /* Tell KVM we're entering idle */ 330 li r4,KVM_HWTHREAD_IN_IDLE 331 /* DO THIS IN REAL MODE! See comment above. */ 332 stb r4,HSTATE_HWTHREAD_STATE(r13) 333#endif 334/* 335 * Check if we are executing the lite variant with ESL=EC=0 336 */ 337 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED 338 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */ 339 bne .Lhandle_esl_ec_set 340 PPC_STOP 341 li r3,0 /* Since we didn't lose state, return 0 */ 342 343 /* 344 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so 345 * it can determine if the wakeup reason is an HMI in 346 * CHECK_HMI_INTERRUPT. 347 * 348 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup 349 * reason, so there is no point setting r12 to SRR1. 350 * 351 * Further, we clear r12 here, so that we don't accidentally enter the 352 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI. 353 */ 354 li r12, 0 355 b pnv_wakeup_noloss 356 357.Lhandle_esl_ec_set: 358BEGIN_FTR_SECTION 359 /* 360 * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after 361 * a state-loss idle. Saving and restoring MMCR0 over idle is a 362 * workaround. 363 */ 364 mfspr r4,SPRN_MMCR0 365 std r4,_MMCR0(r1) 366END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1) 367 368/* 369 * Check if the requested state is a deep idle state. 370 */ 371 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) 372 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) 373 cmpd r3,r4 374 bge .Lhandle_deep_stop 375 PPC_STOP /* Does not return (system reset interrupt) */ 376 377.Lhandle_deep_stop: 378/* 379 * Entering deep idle state. 380 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to 381 * stack and enter stop 382 */ 383 lbz r7,PACA_THREAD_MASK(r13) 384 ld r14,PACA_CORE_IDLE_STATE_PTR(r13) 385 386lwarx_loop_stop: 387 lwarx r15,0,r14 388 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 389 bnel- core_idle_lock_held 390 andc r15,r15,r7 /* Clear thread bit */ 391 392 stwcx. r15,0,r14 393 bne- lwarx_loop_stop 394 isync 395 396 bl save_sprs_to_stack 397 398 PPC_STOP /* Does not return (system reset interrupt) */ 399 400/* 401 * Entered with MSR[EE]=0 and no soft-masked interrupts pending. 402 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE). 403 */ 404_GLOBAL(power7_idle_insn) 405 /* Now check if user or arch enabled NAP mode */ 406 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode) 407 b pnv_powersave_common 408 409#define CHECK_HMI_INTERRUPT \ 410BEGIN_FTR_SECTION_NESTED(66); \ 411 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \ 412FTR_SECTION_ELSE_NESTED(66); \ 413 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \ 414ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ 415 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \ 416 bne+ 20f; \ 417 /* Invoke opal call to handle hmi */ \ 418 ld r2,PACATOC(r13); \ 419 ld r1,PACAR1(r13); \ 420 std r3,ORIG_GPR3(r1); /* Save original r3 */ \ 421 li r3,0; /* NULL argument */ \ 422 bl hmi_exception_realmode; \ 423 nop; \ 424 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \ 42520: nop; 426 427/* 428 * Entered with MSR[EE]=0 and no soft-masked interrupts pending. 429 * r3 contains desired PSSCR register value. 430 */ 431_GLOBAL(power9_idle_stop) 432 std r3, PACA_REQ_PSSCR(r13) 433 mtspr SPRN_PSSCR,r3 434 LOAD_REG_ADDR(r4,power_enter_stop) 435 b pnv_powersave_common 436 /* No return */ 437 438/* 439 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1, 440 * HSPRG0 will be set to the HSPRG0 value of one of the 441 * threads in this core. Thus the value we have in r13 442 * may not be this thread's paca pointer. 443 * 444 * Fortunately, the TIR remains invariant. Since this thread's 445 * paca pointer is recorded in all its sibling's paca, we can 446 * correctly recover this thread's paca pointer if we 447 * know the index of this thread in the core. 448 * 449 * This index can be obtained from the TIR. 450 * 451 * i.e, thread's position in the core = TIR. 452 * If this value is i, then this thread's paca is 453 * paca->thread_sibling_pacas[i]. 454 */ 455power9_dd1_recover_paca: 456 mfspr r4, SPRN_TIR 457 /* 458 * Since each entry in thread_sibling_pacas is 8 bytes 459 * we need to left-shift by 3 bits. Thus r4 = i * 8 460 */ 461 sldi r4, r4, 3 462 /* Get &paca->thread_sibling_pacas[0] in r5 */ 463 ld r5, PACA_SIBLING_PACA_PTRS(r13) 464 /* Load paca->thread_sibling_pacas[i] into r13 */ 465 ldx r13, r4, r5 466 SET_PACA(r13) 467 /* 468 * Indicate that we have lost NVGPR state 469 * which needs to be restored from the stack. 470 */ 471 li r3, 1 472 stb r3,PACA_NAPSTATELOST(r13) 473 blr 474 475/* 476 * Called from machine check handler for powersave wakeups. 477 * Low level machine check processing has already been done. Now just 478 * go through the wake up path to get everything in order. 479 * 480 * r3 - The original SRR1 value. 481 * Original SRR[01] have been clobbered. 482 * MSR_RI is clear. 483 */ 484.global pnv_powersave_wakeup_mce 485pnv_powersave_wakeup_mce: 486 /* Set cr3 for pnv_powersave_wakeup */ 487 rlwinm r11,r3,47-31,30,31 488 cmpwi cr3,r11,2 489 490 /* 491 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake 492 * reason into r12, which allows reuse of the system reset wakeup 493 * code without being mistaken for another type of wakeup. 494 */ 495 oris r12,r3,SRR1_WAKEMCE_RESVD@h 496 497 b pnv_powersave_wakeup 498 499/* 500 * Called from reset vector for powersave wakeups. 501 * cr3 - set to gt if waking up with partial/complete hypervisor state loss 502 * r12 - SRR1 503 */ 504.global pnv_powersave_wakeup 505pnv_powersave_wakeup: 506 ld r2, PACATOC(r13) 507 508BEGIN_FTR_SECTION 509BEGIN_FTR_SECTION_NESTED(70) 510 bl power9_dd1_recover_paca 511END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70) 512 bl pnv_restore_hyp_resource_arch300 513FTR_SECTION_ELSE 514 bl pnv_restore_hyp_resource_arch207 515ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) 516 517 li r0,PNV_THREAD_RUNNING 518 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ 519 520 mr r3,r12 521 522#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 523 li r0,KVM_HWTHREAD_IN_KERNEL 524 stb r0,HSTATE_HWTHREAD_STATE(r13) 525 /* Order setting hwthread_state vs. testing hwthread_req */ 526 sync 527 lbz r0,HSTATE_HWTHREAD_REQ(r13) 528 cmpwi r0,0 529 beq 1f 530 b kvm_start_guest 5311: 532#endif 533 534 /* Return SRR1 from power7_nap() */ 535 blt cr3,pnv_wakeup_noloss 536 b pnv_wakeup_loss 537 538/* 539 * Check whether we have woken up with hypervisor state loss. 540 * If yes, restore hypervisor state and return back to link. 541 * 542 * cr3 - set to gt if waking up with partial/complete hypervisor state loss 543 */ 544pnv_restore_hyp_resource_arch300: 545 /* 546 * Workaround for POWER9, if we lost resources, the ERAT 547 * might have been mixed up and needs flushing. We also need 548 * to reload MMCR0 (see comment above). We also need to set 549 * then clear bit 60 in MMCRA to ensure the PMU starts running. 550 */ 551 blt cr3,1f 552BEGIN_FTR_SECTION 553 PPC_INVALIDATE_ERAT 554 ld r1,PACAR1(r13) 555 ld r4,_MMCR0(r1) 556 mtspr SPRN_MMCR0,r4 557END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1) 558 mfspr r4,SPRN_MMCRA 559 ori r4,r4,(1 << (63-60)) 560 mtspr SPRN_MMCRA,r4 561 xori r4,r4,(1 << (63-60)) 562 mtspr SPRN_MMCRA,r4 5631: 564 /* 565 * POWER ISA 3. Use PSSCR to determine if we 566 * are waking up from deep idle state 567 */ 568 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) 569 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) 570 571BEGIN_FTR_SECTION_NESTED(71) 572 /* 573 * Assume that we are waking up from the state 574 * same as the Requested Level (RL) in the PSSCR 575 * which are Bits 60-63 576 */ 577 ld r5,PACA_REQ_PSSCR(r13) 578 rldicl r5,r5,0,60 579FTR_SECTION_ELSE_NESTED(71) 580 /* 581 * 0-3 bits correspond to Power-Saving Level Status 582 * which indicates the idle state we are waking up from 583 */ 584 mfspr r5, SPRN_PSSCR 585 rldicl r5,r5,4,60 586ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71) 587 cmpd cr4,r5,r4 588 bge cr4,pnv_wakeup_tb_loss /* returns to caller */ 589 590 blr /* Waking up without hypervisor state loss. */ 591 592/* Same calling convention as arch300 */ 593pnv_restore_hyp_resource_arch207: 594 /* 595 * POWER ISA 2.07 or less. 596 * Check if we slept with sleep or winkle. 597 */ 598 lbz r4,PACA_THREAD_IDLE_STATE(r13) 599 cmpwi cr2,r4,PNV_THREAD_NAP 600 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */ 601 602 /* 603 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking 604 * up from nap. At this stage CR3 shouldn't contains 'gt' since that 605 * indicates we are waking with hypervisor state loss from nap. 606 */ 607 bgt cr3,. 608 609 blr /* Waking up without hypervisor state loss */ 610 611/* 612 * Called if waking up from idle state which can cause either partial or 613 * complete hyp state loss. 614 * In POWER8, called if waking up from fastsleep or winkle 615 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state 616 * 617 * r13 - PACA 618 * cr3 - gt if waking up with partial/complete hypervisor state loss 619 * 620 * If ISA300: 621 * cr4 - gt or eq if waking up from complete hypervisor state loss. 622 * 623 * If ISA207: 624 * r4 - PACA_THREAD_IDLE_STATE 625 */ 626pnv_wakeup_tb_loss: 627 ld r1,PACAR1(r13) 628 /* 629 * Before entering any idle state, the NVGPRs are saved in the stack. 630 * If there was a state loss, or PACA_NAPSTATELOST was set, then the 631 * NVGPRs are restored. If we are here, it is likely that state is lost, 632 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach 633 * here are the same as the test to restore NVGPRS: 634 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300, 635 * and SRR1 test for restoring NVGPRs. 636 * 637 * We are about to clobber NVGPRs now, so set NAPSTATELOST to 638 * guarantee they will always be restored. This might be tightened 639 * with careful reading of specs (particularly for ISA300) but this 640 * is already a slow wakeup path and it's simpler to be safe. 641 */ 642 li r0,1 643 stb r0,PACA_NAPSTATELOST(r13) 644 645 /* 646 * 647 * Save SRR1 and LR in NVGPRs as they might be clobbered in 648 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required 649 * to determine the wakeup reason if we branch to kvm_start_guest. LR 650 * is required to return back to reset vector after hypervisor state 651 * restore is complete. 652 */ 653 mr r19,r12 654 mr r18,r4 655 mflr r17 656BEGIN_FTR_SECTION 657 CHECK_HMI_INTERRUPT 658END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 659 660 ld r14,PACA_CORE_IDLE_STATE_PTR(r13) 661 lbz r7,PACA_THREAD_MASK(r13) 662 663 /* 664 * Take the core lock to synchronize against other threads. 665 * 666 * Lock bit is set in one of the 2 cases- 667 * a. In the sleep/winkle enter path, the last thread is executing 668 * fastsleep workaround code. 669 * b. In the wake up path, another thread is executing fastsleep 670 * workaround undo code or resyncing timebase or restoring context 671 * In either case loop until the lock bit is cleared. 672 */ 6731: 674 lwarx r15,0,r14 675 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h 676 bnel- core_idle_lock_held 677 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 678 stwcx. r15,0,r14 679 bne- 1b 680 isync 681 682 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS 683 cmpwi cr2,r9,0 684 685 /* 686 * At this stage 687 * cr2 - eq if first thread to wakeup in core 688 * cr3- gt if waking up with partial/complete hypervisor state loss 689 * ISA300: 690 * cr4 - gt or eq if waking up from complete hypervisor state loss. 691 */ 692 693BEGIN_FTR_SECTION 694 /* 695 * Were we in winkle? 696 * If yes, check if all threads were in winkle, decrement our 697 * winkle count, set all thread winkle bits if all were in winkle. 698 * Check if our thread has a winkle bit set, and set cr4 accordingly 699 * (to match ISA300, above). Pseudo-code for core idle state 700 * transitions for ISA207 is as follows (everything happens atomically 701 * due to store conditional and/or lock bit): 702 * 703 * nap_idle() { } 704 * nap_wake() { } 705 * 706 * sleep_idle() 707 * { 708 * core_idle_state &= ~thread_in_core 709 * } 710 * 711 * sleep_wake() 712 * { 713 * bool first_in_core, first_in_subcore; 714 * 715 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; 716 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; 717 * 718 * core_idle_state |= thread_in_core; 719 * } 720 * 721 * winkle_idle() 722 * { 723 * core_idle_state &= ~thread_in_core; 724 * core_idle_state += 1 << WINKLE_COUNT_SHIFT; 725 * } 726 * 727 * winkle_wake() 728 * { 729 * bool first_in_core, first_in_subcore, winkle_state_lost; 730 * 731 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; 732 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; 733 * 734 * core_idle_state |= thread_in_core; 735 * 736 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT)) 737 * core_idle_state |= THREAD_WINKLE_BITS; 738 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT; 739 * 740 * winkle_state_lost = core_idle_state & 741 * (thread_in_core << WINKLE_THREAD_SHIFT); 742 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT); 743 * } 744 * 745 */ 746 cmpwi r18,PNV_THREAD_WINKLE 747 bne 2f 748 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h 749 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h 750 beq 2f 751 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */ 7522: 753 /* Shift thread bit to winkle mask, then test if this thread is set, 754 * and remove it from the winkle bits */ 755 slwi r8,r7,8 756 and r8,r8,r15 757 andc r15,r15,r8 758 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */ 759 760 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13) 761 and r4,r4,r15 762 cmpwi r4,0 /* Check if first in subcore */ 763 764 or r15,r15,r7 /* Set thread bit */ 765 beq first_thread_in_subcore 766END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) 767 768 or r15,r15,r7 /* Set thread bit */ 769 beq cr2,first_thread_in_core 770 771 /* Not first thread in core or subcore to wake up */ 772 b clear_lock 773 774first_thread_in_subcore: 775 /* 776 * If waking up from sleep, subcore state is not lost. Hence 777 * skip subcore state restore 778 */ 779 blt cr4,subcore_state_restored 780 781 /* Restore per-subcore state */ 782 ld r4,_SDR1(r1) 783 mtspr SPRN_SDR1,r4 784 785 ld r4,_RPR(r1) 786 mtspr SPRN_RPR,r4 787 ld r4,_AMOR(r1) 788 mtspr SPRN_AMOR,r4 789 790subcore_state_restored: 791 /* 792 * Check if the thread is also the first thread in the core. If not, 793 * skip to clear_lock. 794 */ 795 bne cr2,clear_lock 796 797first_thread_in_core: 798 799 /* 800 * First thread in the core waking up from any state which can cause 801 * partial or complete hypervisor state loss. It needs to 802 * call the fastsleep workaround code if the platform requires it. 803 * Call it unconditionally here. The below branch instruction will 804 * be patched out if the platform does not have fastsleep or does not 805 * require the workaround. Patching will be performed during the 806 * discovery of idle-states. 807 */ 808.global pnv_fastsleep_workaround_at_exit 809pnv_fastsleep_workaround_at_exit: 810 b fastsleep_workaround_at_exit 811 812timebase_resync: 813 /* 814 * Use cr3 which indicates that we are waking up with atleast partial 815 * hypervisor state loss to determine if TIMEBASE RESYNC is needed. 816 */ 817 ble cr3,.Ltb_resynced 818 /* Time base re-sync */ 819 bl opal_resync_timebase; 820 /* 821 * If waking up from sleep (POWER8), per core state 822 * is not lost, skip to clear_lock. 823 */ 824.Ltb_resynced: 825 blt cr4,clear_lock 826 827 /* 828 * First thread in the core to wake up and its waking up with 829 * complete hypervisor state loss. Restore per core hypervisor 830 * state. 831 */ 832BEGIN_FTR_SECTION 833 ld r4,_PTCR(r1) 834 mtspr SPRN_PTCR,r4 835 ld r4,_RPR(r1) 836 mtspr SPRN_RPR,r4 837END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) 838 839 ld r4,_TSCR(r1) 840 mtspr SPRN_TSCR,r4 841 ld r4,_WORC(r1) 842 mtspr SPRN_WORC,r4 843 844clear_lock: 845 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h 846 lwsync 847 stw r15,0(r14) 848 849common_exit: 850 /* 851 * Common to all threads. 852 * 853 * If waking up from sleep, hypervisor state is not lost. Hence 854 * skip hypervisor state restore. 855 */ 856 blt cr4,hypervisor_state_restored 857 858 /* Waking up from winkle */ 859 860BEGIN_MMU_FTR_SECTION 861 b no_segments 862END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) 863 /* Restore SLB from PACA */ 864 ld r8,PACA_SLBSHADOWPTR(r13) 865 866 .rept SLB_NUM_BOLTED 867 li r3, SLBSHADOW_SAVEAREA 868 LDX_BE r5, r8, r3 869 addi r3, r3, 8 870 LDX_BE r6, r8, r3 871 andis. r7,r5,SLB_ESID_V@h 872 beq 1f 873 slbmte r6,r5 8741: addi r8,r8,16 875 .endr 876no_segments: 877 878 /* Restore per thread state */ 879 880 ld r4,_SPURR(r1) 881 mtspr SPRN_SPURR,r4 882 ld r4,_PURR(r1) 883 mtspr SPRN_PURR,r4 884 ld r4,_DSCR(r1) 885 mtspr SPRN_DSCR,r4 886 ld r4,_WORT(r1) 887 mtspr SPRN_WORT,r4 888 889 /* Call cur_cpu_spec->cpu_restore() */ 890 LOAD_REG_ADDR(r4, cur_cpu_spec) 891 ld r4,0(r4) 892 ld r12,CPU_SPEC_RESTORE(r4) 893#ifdef PPC64_ELF_ABI_v1 894 ld r12,0(r12) 895#endif 896 mtctr r12 897 bctrl 898 899/* 900 * On POWER9, we can come here on wakeup from a cpuidle stop state. 901 * Hence restore the additional SPRs to the saved value. 902 * 903 * On POWER8, we come here only on winkle. Since winkle is used 904 * only in the case of CPU-Hotplug, we don't need to restore 905 * the additional SPRs. 906 */ 907BEGIN_FTR_SECTION 908 bl power9_restore_additional_sprs 909END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) 910hypervisor_state_restored: 911 912 mr r12,r19 913 mtlr r17 914 blr /* return to pnv_powersave_wakeup */ 915 916fastsleep_workaround_at_exit: 917 li r3,1 918 li r4,0 919 bl opal_config_cpu_idle_state 920 b timebase_resync 921 922/* 923 * R3 here contains the value that will be returned to the caller 924 * of power7_nap. 925 * R12 contains SRR1 for CHECK_HMI_INTERRUPT. 926 */ 927.global pnv_wakeup_loss 928pnv_wakeup_loss: 929 ld r1,PACAR1(r13) 930BEGIN_FTR_SECTION 931 CHECK_HMI_INTERRUPT 932END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 933 REST_NVGPRS(r1) 934 REST_GPR(2, r1) 935 ld r4,PACAKMSR(r13) 936 ld r5,_LINK(r1) 937 ld r6,_CCR(r1) 938 addi r1,r1,INT_FRAME_SIZE 939 mtlr r5 940 mtcr r6 941 mtmsrd r4 942 blr 943 944/* 945 * R3 here contains the value that will be returned to the caller 946 * of power7_nap. 947 * R12 contains SRR1 for CHECK_HMI_INTERRUPT. 948 */ 949pnv_wakeup_noloss: 950 lbz r0,PACA_NAPSTATELOST(r13) 951 cmpwi r0,0 952 bne pnv_wakeup_loss 953 ld r1,PACAR1(r13) 954BEGIN_FTR_SECTION 955 CHECK_HMI_INTERRUPT 956END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 957 ld r4,PACAKMSR(r13) 958 ld r5,_NIP(r1) 959 ld r6,_CCR(r1) 960 addi r1,r1,INT_FRAME_SIZE 961 mtlr r5 962 mtcr r6 963 mtmsrd r4 964 blr 965