114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * This file contains the power_save function for 6xx & 7xxx CPUs 314cf11afSPaul Mackerras * rewritten in assembler 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * Warning ! This code assumes that if your machine has a 750fx 614cf11afSPaul Mackerras * it will have PLL 1 set to low speed mode (used during NAP/DOZE). 714cf11afSPaul Mackerras * if this is not the case some additional changes will have to 814cf11afSPaul Mackerras * be done to check a runtime var (a bit like powersave-nap) 914cf11afSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras */ 1514cf11afSPaul Mackerras 1614cf11afSPaul Mackerras#include <linux/config.h> 1714cf11afSPaul Mackerras#include <linux/threads.h> 18b3b8dc6cSPaul Mackerras#include <asm/reg.h> 1914cf11afSPaul Mackerras#include <asm/page.h> 2014cf11afSPaul Mackerras#include <asm/cputable.h> 2114cf11afSPaul Mackerras#include <asm/thread_info.h> 2214cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2314cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2414cf11afSPaul Mackerras 2514cf11afSPaul Mackerras .text 2614cf11afSPaul Mackerras 2714cf11afSPaul Mackerras/* 2814cf11afSPaul Mackerras * Init idle, called at early CPU setup time from head.S for each CPU 2914cf11afSPaul Mackerras * Make sure no rest of NAP mode remains in HID0, save default 3014cf11afSPaul Mackerras * values for some CPU specific registers. Called with r24 3114cf11afSPaul Mackerras * containing CPU number and r3 reloc offset 3214cf11afSPaul Mackerras */ 3314cf11afSPaul Mackerras_GLOBAL(init_idle_6xx) 3414cf11afSPaul MackerrasBEGIN_FTR_SECTION 3514cf11afSPaul Mackerras mfspr r4,SPRN_HID0 3614cf11afSPaul Mackerras rlwinm r4,r4,0,10,8 /* Clear NAP */ 3714cf11afSPaul Mackerras mtspr SPRN_HID0, r4 3814cf11afSPaul Mackerras b 1f 3914cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 4014cf11afSPaul Mackerras blr 4114cf11afSPaul Mackerras1: 4214cf11afSPaul Mackerras slwi r5,r24,2 4314cf11afSPaul Mackerras add r5,r5,r3 4414cf11afSPaul MackerrasBEGIN_FTR_SECTION 4514cf11afSPaul Mackerras mfspr r4,SPRN_MSSCR0 4614cf11afSPaul Mackerras addis r6,r5, nap_save_msscr0@ha 4714cf11afSPaul Mackerras stw r4,nap_save_msscr0@l(r6) 4814cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 4914cf11afSPaul MackerrasBEGIN_FTR_SECTION 5014cf11afSPaul Mackerras mfspr r4,SPRN_HID1 5114cf11afSPaul Mackerras addis r6,r5,nap_save_hid1@ha 5214cf11afSPaul Mackerras stw r4,nap_save_hid1@l(r6) 5314cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 5414cf11afSPaul Mackerras blr 5514cf11afSPaul Mackerras 5614cf11afSPaul Mackerras/* 5714cf11afSPaul Mackerras * Here is the power_save_6xx function. This could eventually be 5814cf11afSPaul Mackerras * split into several functions & changing the function pointer 5914cf11afSPaul Mackerras * depending on the various features. 6014cf11afSPaul Mackerras */ 6114cf11afSPaul Mackerras_GLOBAL(ppc6xx_idle) 6214cf11afSPaul Mackerras /* Check if we can nap or doze, put HID0 mask in r3 6314cf11afSPaul Mackerras */ 6414cf11afSPaul Mackerras lis r3, 0 6514cf11afSPaul MackerrasBEGIN_FTR_SECTION 6614cf11afSPaul Mackerras lis r3,HID0_DOZE@h 6714cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 6814cf11afSPaul MackerrasBEGIN_FTR_SECTION 6914cf11afSPaul Mackerras /* We must dynamically check for the NAP feature as it 7014cf11afSPaul Mackerras * can be cleared by CPU init after the fixups are done 7114cf11afSPaul Mackerras */ 7214cf11afSPaul Mackerras lis r4,cur_cpu_spec@ha 7314cf11afSPaul Mackerras lwz r4,cur_cpu_spec@l(r4) 7414cf11afSPaul Mackerras lwz r4,CPU_SPEC_FEATURES(r4) 7514cf11afSPaul Mackerras andi. r0,r4,CPU_FTR_CAN_NAP 7614cf11afSPaul Mackerras beq 1f 7714cf11afSPaul Mackerras /* Now check if user or arch enabled NAP mode */ 7814cf11afSPaul Mackerras lis r4,powersave_nap@ha 7914cf11afSPaul Mackerras lwz r4,powersave_nap@l(r4) 8014cf11afSPaul Mackerras cmpwi 0,r4,0 8114cf11afSPaul Mackerras beq 1f 8214cf11afSPaul Mackerras lis r3,HID0_NAP@h 8314cf11afSPaul Mackerras1: 8414cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 8514cf11afSPaul Mackerras cmpwi 0,r3,0 8614cf11afSPaul Mackerras beqlr 8714cf11afSPaul Mackerras 8814cf11afSPaul Mackerras /* Some pre-nap cleanups needed on some CPUs */ 8914cf11afSPaul Mackerras andis. r0,r3,HID0_NAP@h 9014cf11afSPaul Mackerras beq 2f 9114cf11afSPaul MackerrasBEGIN_FTR_SECTION 9214cf11afSPaul Mackerras /* Disable L2 prefetch on some 745x and try to ensure 9314cf11afSPaul Mackerras * L2 prefetch engines are idle. As explained by errata 9414cf11afSPaul Mackerras * text, we can't be sure they are, we just hope very hard 9514cf11afSPaul Mackerras * that well be enough (sic !). At least I noticed Apple 9614cf11afSPaul Mackerras * doesn't even bother doing the dcbf's here... 9714cf11afSPaul Mackerras */ 9814cf11afSPaul Mackerras mfspr r4,SPRN_MSSCR0 9914cf11afSPaul Mackerras rlwinm r4,r4,0,0,29 10014cf11afSPaul Mackerras sync 10114cf11afSPaul Mackerras mtspr SPRN_MSSCR0,r4 10214cf11afSPaul Mackerras sync 10314cf11afSPaul Mackerras isync 10414cf11afSPaul Mackerras lis r4,KERNELBASE@h 10514cf11afSPaul Mackerras dcbf 0,r4 10614cf11afSPaul Mackerras dcbf 0,r4 10714cf11afSPaul Mackerras dcbf 0,r4 10814cf11afSPaul Mackerras dcbf 0,r4 10914cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 11014cf11afSPaul Mackerras2: 11114cf11afSPaul MackerrasBEGIN_FTR_SECTION 11214cf11afSPaul Mackerras /* Go to low speed mode on some 750FX */ 11314cf11afSPaul Mackerras lis r4,powersave_lowspeed@ha 11414cf11afSPaul Mackerras lwz r4,powersave_lowspeed@l(r4) 11514cf11afSPaul Mackerras cmpwi 0,r4,0 11614cf11afSPaul Mackerras beq 1f 11714cf11afSPaul Mackerras mfspr r4,SPRN_HID1 11814cf11afSPaul Mackerras oris r4,r4,0x0001 11914cf11afSPaul Mackerras mtspr SPRN_HID1,r4 12014cf11afSPaul Mackerras1: 12114cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 12214cf11afSPaul Mackerras 12314cf11afSPaul Mackerras /* Go to NAP or DOZE now */ 12414cf11afSPaul Mackerras mfspr r4,SPRN_HID0 12514cf11afSPaul Mackerras lis r5,(HID0_NAP|HID0_SLEEP)@h 12614cf11afSPaul MackerrasBEGIN_FTR_SECTION 12714cf11afSPaul Mackerras oris r5,r5,HID0_DOZE@h 12814cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 12914cf11afSPaul Mackerras andc r4,r4,r5 13014cf11afSPaul Mackerras or r4,r4,r3 13114cf11afSPaul MackerrasBEGIN_FTR_SECTION 13214cf11afSPaul Mackerras oris r4,r4,HID0_DPM@h /* that should be done once for all */ 13314cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM) 13414cf11afSPaul Mackerras mtspr SPRN_HID0,r4 13514cf11afSPaul MackerrasBEGIN_FTR_SECTION 13614cf11afSPaul Mackerras DSSALL 13714cf11afSPaul Mackerras sync 13814cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 139f39224a8SPaul Mackerras rlwinm r9,r1,0,0,31-THREAD_SHIFT /* current thread_info */ 140f39224a8SPaul Mackerras lwz r8,TI_LOCAL_FLAGS(r9) /* set napping bit */ 141f39224a8SPaul Mackerras ori r8,r8,_TLF_NAPPING /* so when we take an exception */ 142f39224a8SPaul Mackerras stw r8,TI_LOCAL_FLAGS(r9) /* it will return to our caller */ 143ff2e6d7eSPaul Mackerras mfmsr r7 144ff2e6d7eSPaul Mackerras ori r7,r7,MSR_EE 14514cf11afSPaul Mackerras oris r7,r7,MSR_POW@h 146f39224a8SPaul Mackerras1: sync 14714cf11afSPaul Mackerras mtmsr r7 14814cf11afSPaul Mackerras isync 149f39224a8SPaul Mackerras b 1b 15014cf11afSPaul Mackerras 15114cf11afSPaul Mackerras/* 15214cf11afSPaul Mackerras * Return from NAP/DOZE mode, restore some CPU specific registers, 15314cf11afSPaul Mackerras * we are called with DR/IR still off and r2 containing physical 154f39224a8SPaul Mackerras * address of current. R11 points to the exception frame (physical 155f39224a8SPaul Mackerras * address). We have to preserve r10. 15614cf11afSPaul Mackerras */ 15714cf11afSPaul Mackerras_GLOBAL(power_save_6xx_restore) 158f39224a8SPaul Mackerras lwz r9,_LINK(r11) /* interrupted in ppc6xx_idle: */ 159f39224a8SPaul Mackerras stw r9,_NIP(r11) /* make it do a blr */ 16014cf11afSPaul Mackerras 161f39224a8SPaul Mackerras#ifdef CONFIG_SMP 162f39224a8SPaul Mackerras mfspr r12,SPRN_SPRG3 163f39224a8SPaul Mackerras lwz r11,TI_CPU(r12) /* get cpu number * 4 */ 16414cf11afSPaul Mackerras slwi r11,r11,2 165f39224a8SPaul Mackerras#else 166f39224a8SPaul Mackerras li r11,0 167f39224a8SPaul Mackerras#endif 16814cf11afSPaul Mackerras /* Todo make sure all these are in the same page 169f39224a8SPaul Mackerras * and load r11 (@ha part + CPU offset) only once 17014cf11afSPaul Mackerras */ 17114cf11afSPaul MackerrasBEGIN_FTR_SECTION 172f39224a8SPaul Mackerras mfspr r9,SPRN_HID0 173f39224a8SPaul Mackerras andis. r9,r9,HID0_NAP@h 174f39224a8SPaul Mackerras beq 1f 17514cf11afSPaul Mackerras addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha 17614cf11afSPaul Mackerras lwz r9,nap_save_msscr0@l(r9) 17714cf11afSPaul Mackerras mtspr SPRN_MSSCR0, r9 17814cf11afSPaul Mackerras sync 17914cf11afSPaul Mackerras isync 18014cf11afSPaul Mackerras1: 18114cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 18214cf11afSPaul MackerrasBEGIN_FTR_SECTION 18314cf11afSPaul Mackerras addis r9,r11,(nap_save_hid1-KERNELBASE)@ha 18414cf11afSPaul Mackerras lwz r9,nap_save_hid1@l(r9) 18514cf11afSPaul Mackerras mtspr SPRN_HID1, r9 18614cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 18714cf11afSPaul Mackerras b transfer_to_handler_cont 18814cf11afSPaul Mackerras 18914cf11afSPaul Mackerras .data 19014cf11afSPaul Mackerras 19114cf11afSPaul Mackerras_GLOBAL(nap_save_msscr0) 19214cf11afSPaul Mackerras .space 4*NR_CPUS 19314cf11afSPaul Mackerras 19414cf11afSPaul Mackerras_GLOBAL(nap_save_hid1) 19514cf11afSPaul Mackerras .space 4*NR_CPUS 19614cf11afSPaul Mackerras 19714cf11afSPaul Mackerras_GLOBAL(powersave_lowspeed) 19814cf11afSPaul Mackerras .long 0 199