114cf11afSPaul Mackerras/* 214cf11afSPaul Mackerras * This file contains the power_save function for 6xx & 7xxx CPUs 314cf11afSPaul Mackerras * rewritten in assembler 414cf11afSPaul Mackerras * 514cf11afSPaul Mackerras * Warning ! This code assumes that if your machine has a 750fx 614cf11afSPaul Mackerras * it will have PLL 1 set to low speed mode (used during NAP/DOZE). 714cf11afSPaul Mackerras * if this is not the case some additional changes will have to 814cf11afSPaul Mackerras * be done to check a runtime var (a bit like powersave-nap) 914cf11afSPaul Mackerras * 1014cf11afSPaul Mackerras * This program is free software; you can redistribute it and/or 1114cf11afSPaul Mackerras * modify it under the terms of the GNU General Public License 1214cf11afSPaul Mackerras * as published by the Free Software Foundation; either version 1314cf11afSPaul Mackerras * 2 of the License, or (at your option) any later version. 1414cf11afSPaul Mackerras */ 1514cf11afSPaul Mackerras 1614cf11afSPaul Mackerras#include <linux/config.h> 1714cf11afSPaul Mackerras#include <linux/threads.h> 1814cf11afSPaul Mackerras#include <asm/processor.h> 1914cf11afSPaul Mackerras#include <asm/page.h> 2014cf11afSPaul Mackerras#include <asm/cputable.h> 2114cf11afSPaul Mackerras#include <asm/thread_info.h> 2214cf11afSPaul Mackerras#include <asm/ppc_asm.h> 2314cf11afSPaul Mackerras#include <asm/asm-offsets.h> 2414cf11afSPaul Mackerras 2514cf11afSPaul Mackerras#undef DEBUG 2614cf11afSPaul Mackerras 2714cf11afSPaul Mackerras .text 2814cf11afSPaul Mackerras 2914cf11afSPaul Mackerras/* 3014cf11afSPaul Mackerras * Init idle, called at early CPU setup time from head.S for each CPU 3114cf11afSPaul Mackerras * Make sure no rest of NAP mode remains in HID0, save default 3214cf11afSPaul Mackerras * values for some CPU specific registers. Called with r24 3314cf11afSPaul Mackerras * containing CPU number and r3 reloc offset 3414cf11afSPaul Mackerras */ 3514cf11afSPaul Mackerras_GLOBAL(init_idle_6xx) 3614cf11afSPaul MackerrasBEGIN_FTR_SECTION 3714cf11afSPaul Mackerras mfspr r4,SPRN_HID0 3814cf11afSPaul Mackerras rlwinm r4,r4,0,10,8 /* Clear NAP */ 3914cf11afSPaul Mackerras mtspr SPRN_HID0, r4 4014cf11afSPaul Mackerras b 1f 4114cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 4214cf11afSPaul Mackerras blr 4314cf11afSPaul Mackerras1: 4414cf11afSPaul Mackerras slwi r5,r24,2 4514cf11afSPaul Mackerras add r5,r5,r3 4614cf11afSPaul MackerrasBEGIN_FTR_SECTION 4714cf11afSPaul Mackerras mfspr r4,SPRN_MSSCR0 4814cf11afSPaul Mackerras addis r6,r5, nap_save_msscr0@ha 4914cf11afSPaul Mackerras stw r4,nap_save_msscr0@l(r6) 5014cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 5114cf11afSPaul MackerrasBEGIN_FTR_SECTION 5214cf11afSPaul Mackerras mfspr r4,SPRN_HID1 5314cf11afSPaul Mackerras addis r6,r5,nap_save_hid1@ha 5414cf11afSPaul Mackerras stw r4,nap_save_hid1@l(r6) 5514cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 5614cf11afSPaul Mackerras blr 5714cf11afSPaul Mackerras 5814cf11afSPaul Mackerras/* 5914cf11afSPaul Mackerras * Here is the power_save_6xx function. This could eventually be 6014cf11afSPaul Mackerras * split into several functions & changing the function pointer 6114cf11afSPaul Mackerras * depending on the various features. 6214cf11afSPaul Mackerras */ 6314cf11afSPaul Mackerras_GLOBAL(ppc6xx_idle) 6414cf11afSPaul Mackerras /* Check if we can nap or doze, put HID0 mask in r3 6514cf11afSPaul Mackerras */ 6614cf11afSPaul Mackerras lis r3, 0 6714cf11afSPaul MackerrasBEGIN_FTR_SECTION 6814cf11afSPaul Mackerras lis r3,HID0_DOZE@h 6914cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 7014cf11afSPaul MackerrasBEGIN_FTR_SECTION 7114cf11afSPaul Mackerras /* We must dynamically check for the NAP feature as it 7214cf11afSPaul Mackerras * can be cleared by CPU init after the fixups are done 7314cf11afSPaul Mackerras */ 7414cf11afSPaul Mackerras lis r4,cur_cpu_spec@ha 7514cf11afSPaul Mackerras lwz r4,cur_cpu_spec@l(r4) 7614cf11afSPaul Mackerras lwz r4,CPU_SPEC_FEATURES(r4) 7714cf11afSPaul Mackerras andi. r0,r4,CPU_FTR_CAN_NAP 7814cf11afSPaul Mackerras beq 1f 7914cf11afSPaul Mackerras /* Now check if user or arch enabled NAP mode */ 8014cf11afSPaul Mackerras lis r4,powersave_nap@ha 8114cf11afSPaul Mackerras lwz r4,powersave_nap@l(r4) 8214cf11afSPaul Mackerras cmpwi 0,r4,0 8314cf11afSPaul Mackerras beq 1f 8414cf11afSPaul Mackerras lis r3,HID0_NAP@h 8514cf11afSPaul Mackerras1: 8614cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 8714cf11afSPaul Mackerras cmpwi 0,r3,0 8814cf11afSPaul Mackerras beqlr 8914cf11afSPaul Mackerras 9014cf11afSPaul Mackerras /* Clear MSR:EE */ 9114cf11afSPaul Mackerras mfmsr r7 9214cf11afSPaul Mackerras rlwinm r0,r7,0,17,15 9314cf11afSPaul Mackerras mtmsr r0 9414cf11afSPaul Mackerras 9514cf11afSPaul Mackerras /* Check current_thread_info()->flags */ 9614cf11afSPaul Mackerras rlwinm r4,r1,0,0,18 9714cf11afSPaul Mackerras lwz r4,TI_FLAGS(r4) 9814cf11afSPaul Mackerras andi. r0,r4,_TIF_NEED_RESCHED 9914cf11afSPaul Mackerras beq 1f 10014cf11afSPaul Mackerras mtmsr r7 /* out of line this ? */ 10114cf11afSPaul Mackerras blr 10214cf11afSPaul Mackerras1: 10314cf11afSPaul Mackerras /* Some pre-nap cleanups needed on some CPUs */ 10414cf11afSPaul Mackerras andis. r0,r3,HID0_NAP@h 10514cf11afSPaul Mackerras beq 2f 10614cf11afSPaul MackerrasBEGIN_FTR_SECTION 10714cf11afSPaul Mackerras /* Disable L2 prefetch on some 745x and try to ensure 10814cf11afSPaul Mackerras * L2 prefetch engines are idle. As explained by errata 10914cf11afSPaul Mackerras * text, we can't be sure they are, we just hope very hard 11014cf11afSPaul Mackerras * that well be enough (sic !). At least I noticed Apple 11114cf11afSPaul Mackerras * doesn't even bother doing the dcbf's here... 11214cf11afSPaul Mackerras */ 11314cf11afSPaul Mackerras mfspr r4,SPRN_MSSCR0 11414cf11afSPaul Mackerras rlwinm r4,r4,0,0,29 11514cf11afSPaul Mackerras sync 11614cf11afSPaul Mackerras mtspr SPRN_MSSCR0,r4 11714cf11afSPaul Mackerras sync 11814cf11afSPaul Mackerras isync 11914cf11afSPaul Mackerras lis r4,KERNELBASE@h 12014cf11afSPaul Mackerras dcbf 0,r4 12114cf11afSPaul Mackerras dcbf 0,r4 12214cf11afSPaul Mackerras dcbf 0,r4 12314cf11afSPaul Mackerras dcbf 0,r4 12414cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 12514cf11afSPaul Mackerras#ifdef DEBUG 12614cf11afSPaul Mackerras lis r6,nap_enter_count@ha 12714cf11afSPaul Mackerras lwz r4,nap_enter_count@l(r6) 12814cf11afSPaul Mackerras addi r4,r4,1 12914cf11afSPaul Mackerras stw r4,nap_enter_count@l(r6) 13014cf11afSPaul Mackerras#endif 13114cf11afSPaul Mackerras2: 13214cf11afSPaul MackerrasBEGIN_FTR_SECTION 13314cf11afSPaul Mackerras /* Go to low speed mode on some 750FX */ 13414cf11afSPaul Mackerras lis r4,powersave_lowspeed@ha 13514cf11afSPaul Mackerras lwz r4,powersave_lowspeed@l(r4) 13614cf11afSPaul Mackerras cmpwi 0,r4,0 13714cf11afSPaul Mackerras beq 1f 13814cf11afSPaul Mackerras mfspr r4,SPRN_HID1 13914cf11afSPaul Mackerras oris r4,r4,0x0001 14014cf11afSPaul Mackerras mtspr SPRN_HID1,r4 14114cf11afSPaul Mackerras1: 14214cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 14314cf11afSPaul Mackerras 14414cf11afSPaul Mackerras /* Go to NAP or DOZE now */ 14514cf11afSPaul Mackerras mfspr r4,SPRN_HID0 14614cf11afSPaul Mackerras lis r5,(HID0_NAP|HID0_SLEEP)@h 14714cf11afSPaul MackerrasBEGIN_FTR_SECTION 14814cf11afSPaul Mackerras oris r5,r5,HID0_DOZE@h 14914cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 15014cf11afSPaul Mackerras andc r4,r4,r5 15114cf11afSPaul Mackerras or r4,r4,r3 15214cf11afSPaul MackerrasBEGIN_FTR_SECTION 15314cf11afSPaul Mackerras oris r4,r4,HID0_DPM@h /* that should be done once for all */ 15414cf11afSPaul MackerrasEND_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM) 15514cf11afSPaul Mackerras mtspr SPRN_HID0,r4 15614cf11afSPaul MackerrasBEGIN_FTR_SECTION 15714cf11afSPaul Mackerras DSSALL 15814cf11afSPaul Mackerras sync 15914cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 16014cf11afSPaul Mackerras ori r7,r7,MSR_EE /* Could be ommited (already set) */ 16114cf11afSPaul Mackerras oris r7,r7,MSR_POW@h 16214cf11afSPaul Mackerras sync 16314cf11afSPaul Mackerras isync 16414cf11afSPaul Mackerras mtmsr r7 16514cf11afSPaul Mackerras isync 16614cf11afSPaul Mackerras sync 16714cf11afSPaul Mackerras blr 16814cf11afSPaul Mackerras 16914cf11afSPaul Mackerras/* 17014cf11afSPaul Mackerras * Return from NAP/DOZE mode, restore some CPU specific registers, 17114cf11afSPaul Mackerras * we are called with DR/IR still off and r2 containing physical 17214cf11afSPaul Mackerras * address of current. 17314cf11afSPaul Mackerras */ 17414cf11afSPaul Mackerras_GLOBAL(power_save_6xx_restore) 17514cf11afSPaul Mackerras mfspr r11,SPRN_HID0 17614cf11afSPaul Mackerras rlwinm. r11,r11,0,10,8 /* Clear NAP & copy NAP bit !state to cr1 EQ */ 17714cf11afSPaul Mackerras cror 4*cr1+eq,4*cr0+eq,4*cr0+eq 17814cf11afSPaul MackerrasBEGIN_FTR_SECTION 17914cf11afSPaul Mackerras rlwinm r11,r11,0,9,7 /* Clear DOZE */ 18014cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 18114cf11afSPaul Mackerras mtspr SPRN_HID0, r11 18214cf11afSPaul Mackerras 18314cf11afSPaul Mackerras#ifdef DEBUG 18414cf11afSPaul Mackerras beq cr1,1f 18514cf11afSPaul Mackerras lis r11,(nap_return_count-KERNELBASE)@ha 18614cf11afSPaul Mackerras lwz r9,nap_return_count@l(r11) 18714cf11afSPaul Mackerras addi r9,r9,1 18814cf11afSPaul Mackerras stw r9,nap_return_count@l(r11) 18914cf11afSPaul Mackerras1: 19014cf11afSPaul Mackerras#endif 19114cf11afSPaul Mackerras 19214cf11afSPaul Mackerras rlwinm r9,r1,0,0,18 19314cf11afSPaul Mackerras tophys(r9,r9) 19414cf11afSPaul Mackerras lwz r11,TI_CPU(r9) 19514cf11afSPaul Mackerras slwi r11,r11,2 19614cf11afSPaul Mackerras /* Todo make sure all these are in the same page 19714cf11afSPaul Mackerras * and load r22 (@ha part + CPU offset) only once 19814cf11afSPaul Mackerras */ 19914cf11afSPaul MackerrasBEGIN_FTR_SECTION 20014cf11afSPaul Mackerras beq cr1,1f 20114cf11afSPaul Mackerras addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha 20214cf11afSPaul Mackerras lwz r9,nap_save_msscr0@l(r9) 20314cf11afSPaul Mackerras mtspr SPRN_MSSCR0, r9 20414cf11afSPaul Mackerras sync 20514cf11afSPaul Mackerras isync 20614cf11afSPaul Mackerras1: 20714cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) 20814cf11afSPaul MackerrasBEGIN_FTR_SECTION 20914cf11afSPaul Mackerras addis r9,r11,(nap_save_hid1-KERNELBASE)@ha 21014cf11afSPaul Mackerras lwz r9,nap_save_hid1@l(r9) 21114cf11afSPaul Mackerras mtspr SPRN_HID1, r9 21214cf11afSPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) 21314cf11afSPaul Mackerras b transfer_to_handler_cont 21414cf11afSPaul Mackerras 21514cf11afSPaul Mackerras .data 21614cf11afSPaul Mackerras 21714cf11afSPaul Mackerras_GLOBAL(nap_save_msscr0) 21814cf11afSPaul Mackerras .space 4*NR_CPUS 21914cf11afSPaul Mackerras 22014cf11afSPaul Mackerras_GLOBAL(nap_save_hid1) 22114cf11afSPaul Mackerras .space 4*NR_CPUS 22214cf11afSPaul Mackerras 22314cf11afSPaul Mackerras_GLOBAL(powersave_nap) 22414cf11afSPaul Mackerras .long 0 22514cf11afSPaul Mackerras_GLOBAL(powersave_lowspeed) 22614cf11afSPaul Mackerras .long 0 22714cf11afSPaul Mackerras 22814cf11afSPaul Mackerras#ifdef DEBUG 22914cf11afSPaul Mackerras_GLOBAL(nap_enter_count) 23014cf11afSPaul Mackerras .space 4 23114cf11afSPaul Mackerras_GLOBAL(nap_return_count) 23214cf11afSPaul Mackerras .space 4 23314cf11afSPaul Mackerras#endif 234