1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __HEAD_BOOKE_H__ 3 #define __HEAD_BOOKE_H__ 4 5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */ 6 #include <asm/kvm_asm.h> 7 #include <asm/kvm_booke_hv_asm.h> 8 9 #ifdef __ASSEMBLY__ 10 11 /* 12 * Macros used for common Book-e exception handling 13 */ 14 15 #define SET_IVOR(vector_number, vector_label) \ 16 li r26,vector_label@l; \ 17 mtspr SPRN_IVOR##vector_number,r26; \ 18 sync 19 20 #if (THREAD_SHIFT < 15) 21 #define ALLOC_STACK_FRAME(reg, val) \ 22 addi reg,reg,val 23 #else 24 #define ALLOC_STACK_FRAME(reg, val) \ 25 addis reg,reg,val@ha; \ 26 addi reg,reg,val@l 27 #endif 28 29 /* 30 * Macro used to get to thread save registers. 31 * Note that entries 0-3 are used for the prolog code, and the remaining 32 * entries are available for specific exception use in the event a handler 33 * requires more than 4 scratch registers. 34 */ 35 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4)) 36 37 #ifdef CONFIG_PPC_FSL_BOOK3E 38 #define BOOKE_CLEAR_BTB(reg) \ 39 START_BTB_FLUSH_SECTION \ 40 BTB_FLUSH(reg) \ 41 END_BTB_FLUSH_SECTION 42 #else 43 #define BOOKE_CLEAR_BTB(reg) 44 #endif 45 46 47 #define NORMAL_EXCEPTION_PROLOG(trapno, intno) \ 48 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 49 mfspr r10, SPRN_SPRG_THREAD; \ 50 stw r11, THREAD_NORMSAVE(0)(r10); \ 51 stw r13, THREAD_NORMSAVE(2)(r10); \ 52 mfcr r13; /* save CR in r13 for now */\ 53 mfspr r11, SPRN_SRR1; \ 54 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ 55 andi. r11, r11, MSR_PR; /* check whether user or kernel */\ 56 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL); \ 57 mtmsr r11; \ 58 mr r11, r1; \ 59 beq 1f; \ 60 BOOKE_CLEAR_BTB(r11) \ 61 /* if from user, start at top of this thread's kernel stack */ \ 62 lwz r11, TASK_STACK - THREAD(r10); \ 63 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ 64 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \ 65 stw r13, _CCR(r11); /* save various registers */ \ 66 stw r12,GPR12(r11); \ 67 stw r9,GPR9(r11); \ 68 mfspr r13, SPRN_SPRG_RSCRATCH0; \ 69 stw r13, GPR10(r11); \ 70 lwz r12, THREAD_NORMSAVE(0)(r10); \ 71 stw r12,GPR11(r11); \ 72 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \ 73 mflr r10; \ 74 stw r10,_LINK(r11); \ 75 mfspr r12,SPRN_SRR0; \ 76 stw r1, GPR1(r11); \ 77 mfspr r9,SPRN_SRR1; \ 78 stw r1, 0(r11); \ 79 mr r1, r11; \ 80 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 81 COMMON_EXCEPTION_PROLOG_END trapno 82 83 .macro COMMON_EXCEPTION_PROLOG_END trapno 84 stw r0,GPR0(r1) 85 lis r10, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ 86 addi r10, r10, STACK_FRAME_REGS_MARKER@l 87 stw r10, 8(r1) 88 li r10, \trapno 89 stw r10,_TRAP(r1) 90 SAVE_4GPRS(3, r1) 91 SAVE_2GPRS(7, r1) 92 SAVE_NVGPRS(r1) 93 stw r2,GPR2(r1) 94 stw r12,_NIP(r1) 95 stw r9,_MSR(r1) 96 mfctr r10 97 mfspr r2,SPRN_SPRG_THREAD 98 stw r10,_CTR(r1) 99 tovirt(r2, r2) 100 mfspr r10,SPRN_XER 101 addi r2, r2, -THREAD 102 stw r10,_XER(r1) 103 addi r3,r1,STACK_FRAME_OVERHEAD 104 .endm 105 106 .macro prepare_transfer_to_handler 107 #ifdef CONFIG_E500 108 andi. r12,r9,MSR_PR 109 bne 777f 110 bl prepare_transfer_to_handler 111 777: 112 #endif 113 .endm 114 115 .macro SYSCALL_ENTRY trapno intno srr1 116 mfspr r10, SPRN_SPRG_THREAD 117 #ifdef CONFIG_KVM_BOOKE_HV 118 BEGIN_FTR_SECTION 119 mtspr SPRN_SPRG_WSCRATCH0, r10 120 stw r11, THREAD_NORMSAVE(0)(r10) 121 stw r13, THREAD_NORMSAVE(2)(r10) 122 mfcr r13 /* save CR in r13 for now */ 123 mfspr r11, SPRN_SRR1 124 mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */ 125 bf 3, 1975f 126 b kvmppc_handler_\intno\()_\srr1 127 1975: 128 mr r12, r13 129 lwz r13, THREAD_NORMSAVE(2)(r10) 130 FTR_SECTION_ELSE 131 mfcr r12 132 ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) 133 #else 134 mfcr r12 135 #endif 136 mfspr r9, SPRN_SRR1 137 BOOKE_CLEAR_BTB(r11) 138 mr r11, r1 139 lwz r1, TASK_STACK - THREAD(r10) 140 rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */ 141 ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE) 142 stw r12, _CCR(r1) 143 mfspr r12,SPRN_SRR0 144 stw r12,_NIP(r1) 145 b transfer_to_syscall /* jump to handler */ 146 .endm 147 148 /* To handle the additional exception priority levels on 40x and Book-E 149 * processors we allocate a stack per additional priority level. 150 * 151 * On 40x critical is the only additional level 152 * On 44x/e500 we have critical and machine check 153 * 154 * Additionally we reserve a SPRG for each priority level so we can free up a 155 * GPR to use as the base for indirect access to the exception stacks. This 156 * is necessary since the MMU is always on, for Book-E parts, and the stacks 157 * are offset from KERNELBASE. 158 * 159 * There is some space optimization to be had here if desired. However 160 * to allow for a common kernel with support for debug exceptions either 161 * going to critical or their own debug level we aren't currently 162 * providing configurations that micro-optimize space usage. 163 */ 164 165 #define MC_STACK_BASE mcheckirq_ctx 166 #define CRIT_STACK_BASE critirq_ctx 167 168 /* only on e500mc */ 169 #define DBG_STACK_BASE dbgirq_ctx 170 171 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 172 173 #ifdef CONFIG_SMP 174 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 175 mfspr r8,SPRN_PIR; \ 176 slwi r8,r8,2; \ 177 addis r8,r8,level##_STACK_BASE@ha; \ 178 lwz r8,level##_STACK_BASE@l(r8); \ 179 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 180 #else 181 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 182 lis r8,level##_STACK_BASE@ha; \ 183 lwz r8,level##_STACK_BASE@l(r8); \ 184 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 185 #endif 186 187 /* 188 * Exception prolog for critical/machine check exceptions. This is a 189 * little different from the normal exception prolog above since a 190 * critical/machine check exception can potentially occur at any point 191 * during normal exception processing. Thus we cannot use the same SPRG 192 * registers as the normal prolog above. Instead we use a portion of the 193 * critical/machine check exception stack at low physical addresses. 194 */ 195 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, trapno, intno, exc_level_srr0, exc_level_srr1) \ 196 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \ 197 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ 198 stw r9,GPR9(r8); /* save various registers */\ 199 mfcr r9; /* save CR in r9 for now */\ 200 stw r10,GPR10(r8); \ 201 stw r11,GPR11(r8); \ 202 stw r9,_CCR(r8); /* save CR on stack */\ 203 mfspr r11,exc_level_srr1; /* check whether user or kernel */\ 204 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ 205 BOOKE_CLEAR_BTB(r10) \ 206 andi. r11,r11,MSR_PR; \ 207 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ 208 mtmsr r11; \ 209 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 210 lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\ 211 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ 212 beq 1f; \ 213 /* COMING FROM USER MODE */ \ 214 stw r9,_CCR(r11); /* save CR */\ 215 lwz r10,GPR10(r8); /* copy regs from exception stack */\ 216 lwz r9,GPR9(r8); \ 217 stw r10,GPR10(r11); \ 218 lwz r10,GPR11(r8); \ 219 stw r9,GPR9(r11); \ 220 stw r10,GPR11(r11); \ 221 b 2f; \ 222 /* COMING FROM PRIV MODE */ \ 223 1: mr r11, r8; \ 224 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \ 225 stw r12,GPR12(r11); /* save various registers */\ 226 mflr r10; \ 227 stw r10,_LINK(r11); \ 228 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 229 stw r12,_DEAR(r11); /* since they may have had stuff */\ 230 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 231 stw r9,_ESR(r11); /* exception was taken */\ 232 mfspr r12,exc_level_srr0; \ 233 stw r1,GPR1(r11); \ 234 mfspr r9,exc_level_srr1; \ 235 stw r1,0(r11); \ 236 mr r1,r11; \ 237 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 238 COMMON_EXCEPTION_PROLOG_END trapno 239 240 #define SAVE_xSRR(xSRR) \ 241 mfspr r0,SPRN_##xSRR##0; \ 242 stw r0,_##xSRR##0(r1); \ 243 mfspr r0,SPRN_##xSRR##1; \ 244 stw r0,_##xSRR##1(r1) 245 246 247 .macro SAVE_MMU_REGS 248 #ifdef CONFIG_PPC_BOOK3E_MMU 249 mfspr r0,SPRN_MAS0 250 stw r0,MAS0(r1) 251 mfspr r0,SPRN_MAS1 252 stw r0,MAS1(r1) 253 mfspr r0,SPRN_MAS2 254 stw r0,MAS2(r1) 255 mfspr r0,SPRN_MAS3 256 stw r0,MAS3(r1) 257 mfspr r0,SPRN_MAS6 258 stw r0,MAS6(r1) 259 #ifdef CONFIG_PHYS_64BIT 260 mfspr r0,SPRN_MAS7 261 stw r0,MAS7(r1) 262 #endif /* CONFIG_PHYS_64BIT */ 263 #endif /* CONFIG_PPC_BOOK3E_MMU */ 264 #ifdef CONFIG_44x 265 mfspr r0,SPRN_MMUCR 266 stw r0,MMUCR(r1) 267 #endif 268 .endm 269 270 #define CRITICAL_EXCEPTION_PROLOG(trapno, intno) \ 271 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, trapno+2, intno, SPRN_CSRR0, SPRN_CSRR1) 272 #define DEBUG_EXCEPTION_PROLOG(trapno) \ 273 EXC_LEVEL_EXCEPTION_PROLOG(DBG, trapno+8, DEBUG, SPRN_DSRR0, SPRN_DSRR1) 274 #define MCHECK_EXCEPTION_PROLOG(trapno) \ 275 EXC_LEVEL_EXCEPTION_PROLOG(MC, trapno+4, MACHINE_CHECK, \ 276 SPRN_MCSRR0, SPRN_MCSRR1) 277 278 /* 279 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite 280 * being delivered to the host. This exception can only happen 281 * inside a KVM guest -- so we just handle up to the DO_KVM rather 282 * than try to fit this into one of the existing prolog macros. 283 */ 284 #define GUEST_DOORBELL_EXCEPTION \ 285 START_EXCEPTION(GuestDoorbell); \ 286 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 287 mfspr r10, SPRN_SPRG_THREAD; \ 288 stw r11, THREAD_NORMSAVE(0)(r10); \ 289 mfspr r11, SPRN_SRR1; \ 290 stw r13, THREAD_NORMSAVE(2)(r10); \ 291 mfcr r13; /* save CR in r13 for now */\ 292 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \ 293 trap 294 295 /* 296 * Exception vectors. 297 */ 298 #define START_EXCEPTION(label) \ 299 .align 5; \ 300 label: 301 302 #define EXCEPTION(n, intno, label, hdlr) \ 303 START_EXCEPTION(label); \ 304 NORMAL_EXCEPTION_PROLOG(n, intno); \ 305 prepare_transfer_to_handler; \ 306 bl hdlr; \ 307 b interrupt_return 308 309 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \ 310 START_EXCEPTION(label); \ 311 CRITICAL_EXCEPTION_PROLOG(n, intno); \ 312 SAVE_MMU_REGS; \ 313 SAVE_xSRR(SRR); \ 314 prepare_transfer_to_handler; \ 315 bl hdlr; \ 316 b ret_from_crit_exc 317 318 #define MCHECK_EXCEPTION(n, label, hdlr) \ 319 START_EXCEPTION(label); \ 320 MCHECK_EXCEPTION_PROLOG(n); \ 321 mfspr r5,SPRN_ESR; \ 322 stw r5,_ESR(r11); \ 323 SAVE_xSRR(DSRR); \ 324 SAVE_xSRR(CSRR); \ 325 SAVE_MMU_REGS; \ 326 SAVE_xSRR(SRR); \ 327 prepare_transfer_to_handler; \ 328 bl hdlr; \ 329 b ret_from_mcheck_exc 330 331 /* Check for a single step debug exception while in an exception 332 * handler before state has been saved. This is to catch the case 333 * where an instruction that we are trying to single step causes 334 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 335 * the exception handler generates a single step debug exception. 336 * 337 * If we get a debug trap on the first instruction of an exception handler, 338 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 339 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 340 * The exception handler was handling a non-critical interrupt, so it will 341 * save (and later restore) the MSR via SPRN_CSRR1, which will still have 342 * the MSR_DE bit set. 343 */ 344 #define DEBUG_DEBUG_EXCEPTION \ 345 START_EXCEPTION(DebugDebug); \ 346 DEBUG_EXCEPTION_PROLOG(2000); \ 347 \ 348 /* \ 349 * If there is a single step or branch-taken exception in an \ 350 * exception entry sequence, it was probably meant to apply to \ 351 * the code where the exception occurred (since exception entry \ 352 * doesn't turn off DE automatically). We simulate the effect \ 353 * of turning off DE on entry to an exception handler by turning \ 354 * off DE in the DSRR1 value and clearing the debug status. \ 355 */ \ 356 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 357 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 358 beq+ 2f; \ 359 \ 360 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 361 ori r10,r10,interrupt_base@l; \ 362 cmplw r12,r10; \ 363 blt+ 2f; /* addr below exception vectors */ \ 364 \ 365 lis r10,interrupt_end@h; \ 366 ori r10,r10,interrupt_end@l; \ 367 cmplw r12,r10; \ 368 bgt+ 2f; /* addr above exception vectors */ \ 369 \ 370 /* here it looks like we got an inappropriate debug exception. */ \ 371 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ 372 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 373 mtspr SPRN_DBSR,r10; \ 374 /* restore state and get out */ \ 375 lwz r10,_CCR(r11); \ 376 lwz r0,GPR0(r11); \ 377 lwz r1,GPR1(r11); \ 378 mtcrf 0x80,r10; \ 379 mtspr SPRN_DSRR0,r12; \ 380 mtspr SPRN_DSRR1,r9; \ 381 lwz r9,GPR9(r11); \ 382 lwz r12,GPR12(r11); \ 383 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \ 384 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \ 385 lwz r10,GPR10(r8); \ 386 lwz r11,GPR11(r8); \ 387 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \ 388 \ 389 PPC_RFDI; \ 390 b .; \ 391 \ 392 /* continue normal handling for a debug exception... */ \ 393 2: mfspr r4,SPRN_DBSR; \ 394 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\ 395 SAVE_xSRR(CSRR); \ 396 SAVE_MMU_REGS; \ 397 SAVE_xSRR(SRR); \ 398 prepare_transfer_to_handler; \ 399 bl DebugException; \ 400 b ret_from_debug_exc 401 402 #define DEBUG_CRIT_EXCEPTION \ 403 START_EXCEPTION(DebugCrit); \ 404 CRITICAL_EXCEPTION_PROLOG(2000,DEBUG); \ 405 \ 406 /* \ 407 * If there is a single step or branch-taken exception in an \ 408 * exception entry sequence, it was probably meant to apply to \ 409 * the code where the exception occurred (since exception entry \ 410 * doesn't turn off DE automatically). We simulate the effect \ 411 * of turning off DE on entry to an exception handler by turning \ 412 * off DE in the CSRR1 value and clearing the debug status. \ 413 */ \ 414 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 415 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 416 beq+ 2f; \ 417 \ 418 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 419 ori r10,r10,interrupt_base@l; \ 420 cmplw r12,r10; \ 421 blt+ 2f; /* addr below exception vectors */ \ 422 \ 423 lis r10,interrupt_end@h; \ 424 ori r10,r10,interrupt_end@l; \ 425 cmplw r12,r10; \ 426 bgt+ 2f; /* addr above exception vectors */ \ 427 \ 428 /* here it looks like we got an inappropriate debug exception. */ \ 429 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ 430 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 431 mtspr SPRN_DBSR,r10; \ 432 /* restore state and get out */ \ 433 lwz r10,_CCR(r11); \ 434 lwz r0,GPR0(r11); \ 435 lwz r1,GPR1(r11); \ 436 mtcrf 0x80,r10; \ 437 mtspr SPRN_CSRR0,r12; \ 438 mtspr SPRN_CSRR1,r9; \ 439 lwz r9,GPR9(r11); \ 440 lwz r12,GPR12(r11); \ 441 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \ 442 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ 443 lwz r10,GPR10(r8); \ 444 lwz r11,GPR11(r8); \ 445 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \ 446 \ 447 rfci; \ 448 b .; \ 449 \ 450 /* continue normal handling for a critical exception... */ \ 451 2: mfspr r4,SPRN_DBSR; \ 452 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\ 453 SAVE_MMU_REGS; \ 454 SAVE_xSRR(SRR); \ 455 prepare_transfer_to_handler; \ 456 bl DebugException; \ 457 b ret_from_crit_exc 458 459 #define DATA_STORAGE_EXCEPTION \ 460 START_EXCEPTION(DataStorage) \ 461 NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE); \ 462 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 463 stw r5,_ESR(r11); \ 464 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ 465 stw r4, _DEAR(r11); \ 466 prepare_transfer_to_handler; \ 467 bl do_page_fault; \ 468 b interrupt_return 469 470 #define INSTRUCTION_STORAGE_EXCEPTION \ 471 START_EXCEPTION(InstructionStorage) \ 472 NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \ 473 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 474 stw r5,_ESR(r11); \ 475 stw r12, _DEAR(r11); /* Pass SRR0 as arg2 */ \ 476 prepare_transfer_to_handler; \ 477 bl do_page_fault; \ 478 b interrupt_return 479 480 #define ALIGNMENT_EXCEPTION \ 481 START_EXCEPTION(Alignment) \ 482 NORMAL_EXCEPTION_PROLOG(0x600, ALIGNMENT); \ 483 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ 484 stw r4,_DEAR(r11); \ 485 prepare_transfer_to_handler; \ 486 bl alignment_exception; \ 487 REST_NVGPRS(r1); \ 488 b interrupt_return 489 490 #define PROGRAM_EXCEPTION \ 491 START_EXCEPTION(Program) \ 492 NORMAL_EXCEPTION_PROLOG(0x700, PROGRAM); \ 493 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ 494 stw r4,_ESR(r11); \ 495 prepare_transfer_to_handler; \ 496 bl program_check_exception; \ 497 REST_NVGPRS(r1); \ 498 b interrupt_return 499 500 #define DECREMENTER_EXCEPTION \ 501 START_EXCEPTION(Decrementer) \ 502 NORMAL_EXCEPTION_PROLOG(0x900, DECREMENTER); \ 503 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ 504 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ 505 prepare_transfer_to_handler; \ 506 bl timer_interrupt; \ 507 b interrupt_return 508 509 #define FP_UNAVAILABLE_EXCEPTION \ 510 START_EXCEPTION(FloatingPointUnavailable) \ 511 NORMAL_EXCEPTION_PROLOG(0x800, FP_UNAVAIL); \ 512 beq 1f; \ 513 bl load_up_fpu; /* if from user, just load it up */ \ 514 b fast_exception_return; \ 515 1: prepare_transfer_to_handler; \ 516 bl kernel_fp_unavailable_exception; \ 517 b interrupt_return 518 519 #else /* __ASSEMBLY__ */ 520 struct exception_regs { 521 unsigned long mas0; 522 unsigned long mas1; 523 unsigned long mas2; 524 unsigned long mas3; 525 unsigned long mas6; 526 unsigned long mas7; 527 unsigned long srr0; 528 unsigned long srr1; 529 unsigned long csrr0; 530 unsigned long csrr1; 531 unsigned long dsrr0; 532 unsigned long dsrr1; 533 }; 534 535 /* ensure this structure is always sized to a multiple of the stack alignment */ 536 #define STACK_EXC_LVL_FRAME_SIZE ALIGN(sizeof (struct exception_regs), 16) 537 538 #endif /* __ASSEMBLY__ */ 539 #endif /* __HEAD_BOOKE_H__ */ 540