1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __HEAD_BOOKE_H__ 3 #define __HEAD_BOOKE_H__ 4 5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */ 6 #include <asm/kvm_asm.h> 7 #include <asm/kvm_booke_hv_asm.h> 8 9 /* 10 * Macros used for common Book-e exception handling 11 */ 12 13 #define SET_IVOR(vector_number, vector_label) \ 14 li r26,vector_label@l; \ 15 mtspr SPRN_IVOR##vector_number,r26; \ 16 sync 17 18 #if (THREAD_SHIFT < 15) 19 #define ALLOC_STACK_FRAME(reg, val) \ 20 addi reg,reg,val 21 #else 22 #define ALLOC_STACK_FRAME(reg, val) \ 23 addis reg,reg,val@ha; \ 24 addi reg,reg,val@l 25 #endif 26 27 /* 28 * Macro used to get to thread save registers. 29 * Note that entries 0-3 are used for the prolog code, and the remaining 30 * entries are available for specific exception use in the event a handler 31 * requires more than 4 scratch registers. 32 */ 33 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4)) 34 35 #define NORMAL_EXCEPTION_PROLOG(intno) \ 36 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 37 mfspr r10, SPRN_SPRG_THREAD; \ 38 stw r11, THREAD_NORMSAVE(0)(r10); \ 39 stw r13, THREAD_NORMSAVE(2)(r10); \ 40 mfcr r13; /* save CR in r13 for now */\ 41 mfspr r11, SPRN_SRR1; \ 42 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ 43 andi. r11, r11, MSR_PR; /* check whether user or kernel */\ 44 mr r11, r1; \ 45 beq 1f; \ 46 /* if from user, start at top of this thread's kernel stack */ \ 47 lwz r11, THREAD_INFO-THREAD(r10); \ 48 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ 49 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \ 50 stw r13, _CCR(r11); /* save various registers */ \ 51 stw r12,GPR12(r11); \ 52 stw r9,GPR9(r11); \ 53 mfspr r13, SPRN_SPRG_RSCRATCH0; \ 54 stw r13, GPR10(r11); \ 55 lwz r12, THREAD_NORMSAVE(0)(r10); \ 56 stw r12,GPR11(r11); \ 57 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \ 58 mflr r10; \ 59 stw r10,_LINK(r11); \ 60 mfspr r12,SPRN_SRR0; \ 61 stw r1, GPR1(r11); \ 62 mfspr r9,SPRN_SRR1; \ 63 stw r1, 0(r11); \ 64 mr r1, r11; \ 65 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 66 stw r0,GPR0(r11); \ 67 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \ 68 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \ 69 stw r10, 8(r11); \ 70 SAVE_4GPRS(3, r11); \ 71 SAVE_2GPRS(7, r11) 72 73 /* To handle the additional exception priority levels on 40x and Book-E 74 * processors we allocate a stack per additional priority level. 75 * 76 * On 40x critical is the only additional level 77 * On 44x/e500 we have critical and machine check 78 * On e200 we have critical and debug (machine check occurs via critical) 79 * 80 * Additionally we reserve a SPRG for each priority level so we can free up a 81 * GPR to use as the base for indirect access to the exception stacks. This 82 * is necessary since the MMU is always on, for Book-E parts, and the stacks 83 * are offset from KERNELBASE. 84 * 85 * There is some space optimization to be had here if desired. However 86 * to allow for a common kernel with support for debug exceptions either 87 * going to critical or their own debug level we aren't currently 88 * providing configurations that micro-optimize space usage. 89 */ 90 91 #define MC_STACK_BASE mcheckirq_ctx 92 #define CRIT_STACK_BASE critirq_ctx 93 94 /* only on e500mc/e200 */ 95 #define DBG_STACK_BASE dbgirq_ctx 96 97 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 98 99 #ifdef CONFIG_SMP 100 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 101 mfspr r8,SPRN_PIR; \ 102 slwi r8,r8,2; \ 103 addis r8,r8,level##_STACK_BASE@ha; \ 104 lwz r8,level##_STACK_BASE@l(r8); \ 105 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 106 #else 107 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 108 lis r8,level##_STACK_BASE@ha; \ 109 lwz r8,level##_STACK_BASE@l(r8); \ 110 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 111 #endif 112 113 /* 114 * Exception prolog for critical/machine check exceptions. This is a 115 * little different from the normal exception prolog above since a 116 * critical/machine check exception can potentially occur at any point 117 * during normal exception processing. Thus we cannot use the same SPRG 118 * registers as the normal prolog above. Instead we use a portion of the 119 * critical/machine check exception stack at low physical addresses. 120 */ 121 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \ 122 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \ 123 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ 124 stw r9,GPR9(r8); /* save various registers */\ 125 mfcr r9; /* save CR in r9 for now */\ 126 stw r10,GPR10(r8); \ 127 stw r11,GPR11(r8); \ 128 stw r9,_CCR(r8); /* save CR on stack */\ 129 mfspr r11,exc_level_srr1; /* check whether user or kernel */\ 130 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ 131 andi. r11,r11,MSR_PR; \ 132 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 133 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ 134 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ 135 beq 1f; \ 136 /* COMING FROM USER MODE */ \ 137 stw r9,_CCR(r11); /* save CR */\ 138 lwz r10,GPR10(r8); /* copy regs from exception stack */\ 139 lwz r9,GPR9(r8); \ 140 stw r10,GPR10(r11); \ 141 lwz r10,GPR11(r8); \ 142 stw r9,GPR9(r11); \ 143 stw r10,GPR11(r11); \ 144 b 2f; \ 145 /* COMING FROM PRIV MODE */ \ 146 1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \ 147 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \ 148 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \ 149 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \ 150 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \ 151 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \ 152 mr r11,r8; \ 153 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \ 154 stw r12,GPR12(r11); /* save various registers */\ 155 mflr r10; \ 156 stw r10,_LINK(r11); \ 157 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 158 stw r12,_DEAR(r11); /* since they may have had stuff */\ 159 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 160 stw r9,_ESR(r11); /* exception was taken */\ 161 mfspr r12,exc_level_srr0; \ 162 stw r1,GPR1(r11); \ 163 mfspr r9,exc_level_srr1; \ 164 stw r1,0(r11); \ 165 mr r1,r11; \ 166 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 167 stw r0,GPR0(r11); \ 168 SAVE_4GPRS(3, r11); \ 169 SAVE_2GPRS(7, r11) 170 171 #define CRITICAL_EXCEPTION_PROLOG(intno) \ 172 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1) 173 #define DEBUG_EXCEPTION_PROLOG \ 174 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1) 175 #define MCHECK_EXCEPTION_PROLOG \ 176 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \ 177 SPRN_MCSRR0, SPRN_MCSRR1) 178 179 /* 180 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite 181 * being delivered to the host. This exception can only happen 182 * inside a KVM guest -- so we just handle up to the DO_KVM rather 183 * than try to fit this into one of the existing prolog macros. 184 */ 185 #define GUEST_DOORBELL_EXCEPTION \ 186 START_EXCEPTION(GuestDoorbell); \ 187 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 188 mfspr r10, SPRN_SPRG_THREAD; \ 189 stw r11, THREAD_NORMSAVE(0)(r10); \ 190 mfspr r11, SPRN_SRR1; \ 191 stw r13, THREAD_NORMSAVE(2)(r10); \ 192 mfcr r13; /* save CR in r13 for now */\ 193 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \ 194 trap 195 196 /* 197 * Exception vectors. 198 */ 199 #define START_EXCEPTION(label) \ 200 .align 5; \ 201 label: 202 203 #define EXCEPTION(n, intno, label, hdlr, xfer) \ 204 START_EXCEPTION(label); \ 205 NORMAL_EXCEPTION_PROLOG(intno); \ 206 addi r3,r1,STACK_FRAME_OVERHEAD; \ 207 xfer(n, hdlr) 208 209 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \ 210 START_EXCEPTION(label); \ 211 CRITICAL_EXCEPTION_PROLOG(intno); \ 212 addi r3,r1,STACK_FRAME_OVERHEAD; \ 213 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 214 NOCOPY, crit_transfer_to_handler, \ 215 ret_from_crit_exc) 216 217 #define MCHECK_EXCEPTION(n, label, hdlr) \ 218 START_EXCEPTION(label); \ 219 MCHECK_EXCEPTION_PROLOG; \ 220 mfspr r5,SPRN_ESR; \ 221 stw r5,_ESR(r11); \ 222 addi r3,r1,STACK_FRAME_OVERHEAD; \ 223 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 224 NOCOPY, mcheck_transfer_to_handler, \ 225 ret_from_mcheck_exc) 226 227 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ 228 li r10,trap; \ 229 stw r10,_TRAP(r11); \ 230 lis r10,msr@h; \ 231 ori r10,r10,msr@l; \ 232 copyee(r10, r9); \ 233 bl tfer; \ 234 .long hdlr; \ 235 .long ret 236 237 #define COPY_EE(d, s) rlwimi d,s,0,16,16 238 #define NOCOPY(d, s) 239 240 #define EXC_XFER_STD(n, hdlr) \ 241 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ 242 ret_from_except_full) 243 244 #define EXC_XFER_LITE(n, hdlr) \ 245 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ 246 ret_from_except) 247 248 #define EXC_XFER_EE(n, hdlr) \ 249 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ 250 ret_from_except_full) 251 252 #define EXC_XFER_EE_LITE(n, hdlr) \ 253 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ 254 ret_from_except) 255 256 /* Check for a single step debug exception while in an exception 257 * handler before state has been saved. This is to catch the case 258 * where an instruction that we are trying to single step causes 259 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 260 * the exception handler generates a single step debug exception. 261 * 262 * If we get a debug trap on the first instruction of an exception handler, 263 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 264 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 265 * The exception handler was handling a non-critical interrupt, so it will 266 * save (and later restore) the MSR via SPRN_CSRR1, which will still have 267 * the MSR_DE bit set. 268 */ 269 #define DEBUG_DEBUG_EXCEPTION \ 270 START_EXCEPTION(DebugDebug); \ 271 DEBUG_EXCEPTION_PROLOG; \ 272 \ 273 /* \ 274 * If there is a single step or branch-taken exception in an \ 275 * exception entry sequence, it was probably meant to apply to \ 276 * the code where the exception occurred (since exception entry \ 277 * doesn't turn off DE automatically). We simulate the effect \ 278 * of turning off DE on entry to an exception handler by turning \ 279 * off DE in the DSRR1 value and clearing the debug status. \ 280 */ \ 281 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 282 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 283 beq+ 2f; \ 284 \ 285 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 286 ori r10,r10,interrupt_base@l; \ 287 cmplw r12,r10; \ 288 blt+ 2f; /* addr below exception vectors */ \ 289 \ 290 lis r10,interrupt_end@h; \ 291 ori r10,r10,interrupt_end@l; \ 292 cmplw r12,r10; \ 293 bgt+ 2f; /* addr above exception vectors */ \ 294 \ 295 /* here it looks like we got an inappropriate debug exception. */ \ 296 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ 297 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 298 mtspr SPRN_DBSR,r10; \ 299 /* restore state and get out */ \ 300 lwz r10,_CCR(r11); \ 301 lwz r0,GPR0(r11); \ 302 lwz r1,GPR1(r11); \ 303 mtcrf 0x80,r10; \ 304 mtspr SPRN_DSRR0,r12; \ 305 mtspr SPRN_DSRR1,r9; \ 306 lwz r9,GPR9(r11); \ 307 lwz r12,GPR12(r11); \ 308 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \ 309 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \ 310 lwz r10,GPR10(r8); \ 311 lwz r11,GPR11(r8); \ 312 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \ 313 \ 314 PPC_RFDI; \ 315 b .; \ 316 \ 317 /* continue normal handling for a debug exception... */ \ 318 2: mfspr r4,SPRN_DBSR; \ 319 addi r3,r1,STACK_FRAME_OVERHEAD; \ 320 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) 321 322 #define DEBUG_CRIT_EXCEPTION \ 323 START_EXCEPTION(DebugCrit); \ 324 CRITICAL_EXCEPTION_PROLOG(DEBUG); \ 325 \ 326 /* \ 327 * If there is a single step or branch-taken exception in an \ 328 * exception entry sequence, it was probably meant to apply to \ 329 * the code where the exception occurred (since exception entry \ 330 * doesn't turn off DE automatically). We simulate the effect \ 331 * of turning off DE on entry to an exception handler by turning \ 332 * off DE in the CSRR1 value and clearing the debug status. \ 333 */ \ 334 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 335 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 336 beq+ 2f; \ 337 \ 338 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 339 ori r10,r10,interrupt_base@l; \ 340 cmplw r12,r10; \ 341 blt+ 2f; /* addr below exception vectors */ \ 342 \ 343 lis r10,interrupt_end@h; \ 344 ori r10,r10,interrupt_end@l; \ 345 cmplw r12,r10; \ 346 bgt+ 2f; /* addr above exception vectors */ \ 347 \ 348 /* here it looks like we got an inappropriate debug exception. */ \ 349 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ 350 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 351 mtspr SPRN_DBSR,r10; \ 352 /* restore state and get out */ \ 353 lwz r10,_CCR(r11); \ 354 lwz r0,GPR0(r11); \ 355 lwz r1,GPR1(r11); \ 356 mtcrf 0x80,r10; \ 357 mtspr SPRN_CSRR0,r12; \ 358 mtspr SPRN_CSRR1,r9; \ 359 lwz r9,GPR9(r11); \ 360 lwz r12,GPR12(r11); \ 361 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \ 362 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ 363 lwz r10,GPR10(r8); \ 364 lwz r11,GPR11(r8); \ 365 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \ 366 \ 367 rfci; \ 368 b .; \ 369 \ 370 /* continue normal handling for a critical exception... */ \ 371 2: mfspr r4,SPRN_DBSR; \ 372 addi r3,r1,STACK_FRAME_OVERHEAD; \ 373 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) 374 375 #define DATA_STORAGE_EXCEPTION \ 376 START_EXCEPTION(DataStorage) \ 377 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \ 378 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 379 stw r5,_ESR(r11); \ 380 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ 381 EXC_XFER_LITE(0x0300, handle_page_fault) 382 383 #define INSTRUCTION_STORAGE_EXCEPTION \ 384 START_EXCEPTION(InstructionStorage) \ 385 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \ 386 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 387 stw r5,_ESR(r11); \ 388 mr r4,r12; /* Pass SRR0 as arg2 */ \ 389 li r5,0; /* Pass zero as arg3 */ \ 390 EXC_XFER_LITE(0x0400, handle_page_fault) 391 392 #define ALIGNMENT_EXCEPTION \ 393 START_EXCEPTION(Alignment) \ 394 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \ 395 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ 396 stw r4,_DEAR(r11); \ 397 addi r3,r1,STACK_FRAME_OVERHEAD; \ 398 EXC_XFER_EE(0x0600, alignment_exception) 399 400 #define PROGRAM_EXCEPTION \ 401 START_EXCEPTION(Program) \ 402 NORMAL_EXCEPTION_PROLOG(PROGRAM); \ 403 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ 404 stw r4,_ESR(r11); \ 405 addi r3,r1,STACK_FRAME_OVERHEAD; \ 406 EXC_XFER_STD(0x0700, program_check_exception) 407 408 #define DECREMENTER_EXCEPTION \ 409 START_EXCEPTION(Decrementer) \ 410 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \ 411 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ 412 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ 413 addi r3,r1,STACK_FRAME_OVERHEAD; \ 414 EXC_XFER_LITE(0x0900, timer_interrupt) 415 416 #define FP_UNAVAILABLE_EXCEPTION \ 417 START_EXCEPTION(FloatingPointUnavailable) \ 418 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \ 419 beq 1f; \ 420 bl load_up_fpu; /* if from user, just load it up */ \ 421 b fast_exception_return; \ 422 1: addi r3,r1,STACK_FRAME_OVERHEAD; \ 423 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) 424 425 #ifndef __ASSEMBLY__ 426 struct exception_regs { 427 unsigned long mas0; 428 unsigned long mas1; 429 unsigned long mas2; 430 unsigned long mas3; 431 unsigned long mas6; 432 unsigned long mas7; 433 unsigned long srr0; 434 unsigned long srr1; 435 unsigned long csrr0; 436 unsigned long csrr1; 437 unsigned long dsrr0; 438 unsigned long dsrr1; 439 unsigned long saved_ksp_limit; 440 }; 441 442 /* ensure this structure is always sized to a multiple of the stack alignment */ 443 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16) 444 445 #endif /* __ASSEMBLY__ */ 446 #endif /* __HEAD_BOOKE_H__ */ 447