1 #ifndef __HEAD_BOOKE_H__ 2 #define __HEAD_BOOKE_H__ 3 4 /* 5 * Macros used for common Book-e exception handling 6 */ 7 8 #define SET_IVOR(vector_number, vector_label) \ 9 li r26,vector_label@l; \ 10 mtspr SPRN_IVOR##vector_number,r26; \ 11 sync 12 13 #if (THREAD_SHIFT < 15) 14 #define ALLOC_STACK_FRAME(reg, val) \ 15 addi reg,reg,val 16 #else 17 #define ALLOC_STACK_FRAME(reg, val) \ 18 addis reg,reg,val@ha; \ 19 addi reg,reg,val@l 20 #endif 21 22 #define NORMAL_EXCEPTION_PROLOG \ 23 mtspr SPRN_SPRG_WSCRATCH0,r10;/* save two registers to work with */\ 24 mtspr SPRN_SPRG_WSCRATCH1,r11; \ 25 mtspr SPRN_SPRG_WSCRATCH2,r1; \ 26 mfcr r10; /* save CR in r10 for now */\ 27 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ 28 andi. r11,r11,MSR_PR; \ 29 beq 1f; \ 30 mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 31 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ 32 ALLOC_STACK_FRAME(r1, THREAD_SIZE); \ 33 1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ 34 mr r11,r1; \ 35 stw r10,_CCR(r11); /* save various registers */\ 36 stw r12,GPR12(r11); \ 37 stw r9,GPR9(r11); \ 38 mfspr r10,SPRN_SPRG_RSCRATCH0; \ 39 stw r10,GPR10(r11); \ 40 mfspr r12,SPRN_SPRG_RSCRATCH1; \ 41 stw r12,GPR11(r11); \ 42 mflr r10; \ 43 stw r10,_LINK(r11); \ 44 mfspr r10,SPRN_SPRG_RSCRATCH2; \ 45 mfspr r12,SPRN_SRR0; \ 46 stw r10,GPR1(r11); \ 47 mfspr r9,SPRN_SRR1; \ 48 stw r10,0(r11); \ 49 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 50 stw r0,GPR0(r11); \ 51 SAVE_4GPRS(3, r11); \ 52 SAVE_2GPRS(7, r11) 53 54 /* To handle the additional exception priority levels on 40x and Book-E 55 * processors we allocate a stack per additional priority level. 56 * 57 * On 40x critical is the only additional level 58 * On 44x/e500 we have critical and machine check 59 * On e200 we have critical and debug (machine check occurs via critical) 60 * 61 * Additionally we reserve a SPRG for each priority level so we can free up a 62 * GPR to use as the base for indirect access to the exception stacks. This 63 * is necessary since the MMU is always on, for Book-E parts, and the stacks 64 * are offset from KERNELBASE. 65 * 66 * There is some space optimization to be had here if desired. However 67 * to allow for a common kernel with support for debug exceptions either 68 * going to critical or their own debug level we aren't currently 69 * providing configurations that micro-optimize space usage. 70 */ 71 72 #define MC_STACK_BASE mcheckirq_ctx 73 #define CRIT_STACK_BASE critirq_ctx 74 75 /* only on e500mc/e200 */ 76 #define DBG_STACK_BASE dbgirq_ctx 77 78 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 79 80 #ifdef CONFIG_SMP 81 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 82 mfspr r8,SPRN_PIR; \ 83 slwi r8,r8,2; \ 84 addis r8,r8,level##_STACK_BASE@ha; \ 85 lwz r8,level##_STACK_BASE@l(r8); \ 86 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 87 #else 88 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 89 lis r8,level##_STACK_BASE@ha; \ 90 lwz r8,level##_STACK_BASE@l(r8); \ 91 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 92 #endif 93 94 /* 95 * Exception prolog for critical/machine check exceptions. This is a 96 * little different from the normal exception prolog above since a 97 * critical/machine check exception can potentially occur at any point 98 * during normal exception processing. Thus we cannot use the same SPRG 99 * registers as the normal prolog above. Instead we use a portion of the 100 * critical/machine check exception stack at low physical addresses. 101 */ 102 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \ 103 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \ 104 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ 105 stw r9,GPR9(r8); /* save various registers */\ 106 mfcr r9; /* save CR in r9 for now */\ 107 stw r10,GPR10(r8); \ 108 stw r11,GPR11(r8); \ 109 stw r9,_CCR(r8); /* save CR on stack */\ 110 mfspr r10,exc_level_srr1; /* check whether user or kernel */\ 111 andi. r10,r10,MSR_PR; \ 112 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 113 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ 114 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ 115 beq 1f; \ 116 /* COMING FROM USER MODE */ \ 117 stw r9,_CCR(r11); /* save CR */\ 118 lwz r10,GPR10(r8); /* copy regs from exception stack */\ 119 lwz r9,GPR9(r8); \ 120 stw r10,GPR10(r11); \ 121 lwz r10,GPR11(r8); \ 122 stw r9,GPR9(r11); \ 123 stw r10,GPR11(r11); \ 124 b 2f; \ 125 /* COMING FROM PRIV MODE */ \ 126 1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \ 127 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \ 128 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \ 129 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \ 130 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \ 131 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \ 132 mr r11,r8; \ 133 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \ 134 stw r12,GPR12(r11); /* save various registers */\ 135 mflr r10; \ 136 stw r10,_LINK(r11); \ 137 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 138 stw r12,_DEAR(r11); /* since they may have had stuff */\ 139 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 140 stw r9,_ESR(r11); /* exception was taken */\ 141 mfspr r12,exc_level_srr0; \ 142 stw r1,GPR1(r11); \ 143 mfspr r9,exc_level_srr1; \ 144 stw r1,0(r11); \ 145 mr r1,r11; \ 146 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 147 stw r0,GPR0(r11); \ 148 SAVE_4GPRS(3, r11); \ 149 SAVE_2GPRS(7, r11) 150 151 #define CRITICAL_EXCEPTION_PROLOG \ 152 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1) 153 #define DEBUG_EXCEPTION_PROLOG \ 154 EXC_LEVEL_EXCEPTION_PROLOG(DBG, SPRN_DSRR0, SPRN_DSRR1) 155 #define MCHECK_EXCEPTION_PROLOG \ 156 EXC_LEVEL_EXCEPTION_PROLOG(MC, SPRN_MCSRR0, SPRN_MCSRR1) 157 158 /* 159 * Exception vectors. 160 */ 161 #define START_EXCEPTION(label) \ 162 .align 5; \ 163 label: 164 165 #define FINISH_EXCEPTION(func) \ 166 bl transfer_to_handler_full; \ 167 .long func; \ 168 .long ret_from_except_full 169 170 #define EXCEPTION(n, label, hdlr, xfer) \ 171 START_EXCEPTION(label); \ 172 NORMAL_EXCEPTION_PROLOG; \ 173 addi r3,r1,STACK_FRAME_OVERHEAD; \ 174 xfer(n, hdlr) 175 176 #define CRITICAL_EXCEPTION(n, label, hdlr) \ 177 START_EXCEPTION(label); \ 178 CRITICAL_EXCEPTION_PROLOG; \ 179 addi r3,r1,STACK_FRAME_OVERHEAD; \ 180 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 181 NOCOPY, crit_transfer_to_handler, \ 182 ret_from_crit_exc) 183 184 #define MCHECK_EXCEPTION(n, label, hdlr) \ 185 START_EXCEPTION(label); \ 186 MCHECK_EXCEPTION_PROLOG; \ 187 mfspr r5,SPRN_ESR; \ 188 stw r5,_ESR(r11); \ 189 addi r3,r1,STACK_FRAME_OVERHEAD; \ 190 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 191 NOCOPY, mcheck_transfer_to_handler, \ 192 ret_from_mcheck_exc) 193 194 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ 195 li r10,trap; \ 196 stw r10,_TRAP(r11); \ 197 lis r10,msr@h; \ 198 ori r10,r10,msr@l; \ 199 copyee(r10, r9); \ 200 bl tfer; \ 201 .long hdlr; \ 202 .long ret 203 204 #define COPY_EE(d, s) rlwimi d,s,0,16,16 205 #define NOCOPY(d, s) 206 207 #define EXC_XFER_STD(n, hdlr) \ 208 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ 209 ret_from_except_full) 210 211 #define EXC_XFER_LITE(n, hdlr) \ 212 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ 213 ret_from_except) 214 215 #define EXC_XFER_EE(n, hdlr) \ 216 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ 217 ret_from_except_full) 218 219 #define EXC_XFER_EE_LITE(n, hdlr) \ 220 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ 221 ret_from_except) 222 223 /* Check for a single step debug exception while in an exception 224 * handler before state has been saved. This is to catch the case 225 * where an instruction that we are trying to single step causes 226 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 227 * the exception handler generates a single step debug exception. 228 * 229 * If we get a debug trap on the first instruction of an exception handler, 230 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 231 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 232 * The exception handler was handling a non-critical interrupt, so it will 233 * save (and later restore) the MSR via SPRN_CSRR1, which will still have 234 * the MSR_DE bit set. 235 */ 236 #define DEBUG_DEBUG_EXCEPTION \ 237 START_EXCEPTION(DebugDebug); \ 238 DEBUG_EXCEPTION_PROLOG; \ 239 \ 240 /* \ 241 * If there is a single step or branch-taken exception in an \ 242 * exception entry sequence, it was probably meant to apply to \ 243 * the code where the exception occurred (since exception entry \ 244 * doesn't turn off DE automatically). We simulate the effect \ 245 * of turning off DE on entry to an exception handler by turning \ 246 * off DE in the DSRR1 value and clearing the debug status. \ 247 */ \ 248 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 249 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 250 beq+ 2f; \ 251 \ 252 lis r10,KERNELBASE@h; /* check if exception in vectors */ \ 253 ori r10,r10,KERNELBASE@l; \ 254 cmplw r12,r10; \ 255 blt+ 2f; /* addr below exception vectors */ \ 256 \ 257 lis r10,DebugDebug@h; \ 258 ori r10,r10,DebugDebug@l; \ 259 cmplw r12,r10; \ 260 bgt+ 2f; /* addr above exception vectors */ \ 261 \ 262 /* here it looks like we got an inappropriate debug exception. */ \ 263 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ 264 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 265 mtspr SPRN_DBSR,r10; \ 266 /* restore state and get out */ \ 267 lwz r10,_CCR(r11); \ 268 lwz r0,GPR0(r11); \ 269 lwz r1,GPR1(r11); \ 270 mtcrf 0x80,r10; \ 271 mtspr SPRN_DSRR0,r12; \ 272 mtspr SPRN_DSRR1,r9; \ 273 lwz r9,GPR9(r11); \ 274 lwz r12,GPR12(r11); \ 275 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \ 276 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \ 277 lwz r10,GPR10(r8); \ 278 lwz r11,GPR11(r8); \ 279 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \ 280 \ 281 PPC_RFDI; \ 282 b .; \ 283 \ 284 /* continue normal handling for a debug exception... */ \ 285 2: mfspr r4,SPRN_DBSR; \ 286 addi r3,r1,STACK_FRAME_OVERHEAD; \ 287 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) 288 289 #define DEBUG_CRIT_EXCEPTION \ 290 START_EXCEPTION(DebugCrit); \ 291 CRITICAL_EXCEPTION_PROLOG; \ 292 \ 293 /* \ 294 * If there is a single step or branch-taken exception in an \ 295 * exception entry sequence, it was probably meant to apply to \ 296 * the code where the exception occurred (since exception entry \ 297 * doesn't turn off DE automatically). We simulate the effect \ 298 * of turning off DE on entry to an exception handler by turning \ 299 * off DE in the CSRR1 value and clearing the debug status. \ 300 */ \ 301 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 302 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 303 beq+ 2f; \ 304 \ 305 lis r10,KERNELBASE@h; /* check if exception in vectors */ \ 306 ori r10,r10,KERNELBASE@l; \ 307 cmplw r12,r10; \ 308 blt+ 2f; /* addr below exception vectors */ \ 309 \ 310 lis r10,DebugCrit@h; \ 311 ori r10,r10,DebugCrit@l; \ 312 cmplw r12,r10; \ 313 bgt+ 2f; /* addr above exception vectors */ \ 314 \ 315 /* here it looks like we got an inappropriate debug exception. */ \ 316 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ 317 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 318 mtspr SPRN_DBSR,r10; \ 319 /* restore state and get out */ \ 320 lwz r10,_CCR(r11); \ 321 lwz r0,GPR0(r11); \ 322 lwz r1,GPR1(r11); \ 323 mtcrf 0x80,r10; \ 324 mtspr SPRN_CSRR0,r12; \ 325 mtspr SPRN_CSRR1,r9; \ 326 lwz r9,GPR9(r11); \ 327 lwz r12,GPR12(r11); \ 328 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \ 329 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ 330 lwz r10,GPR10(r8); \ 331 lwz r11,GPR11(r8); \ 332 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \ 333 \ 334 rfci; \ 335 b .; \ 336 \ 337 /* continue normal handling for a critical exception... */ \ 338 2: mfspr r4,SPRN_DBSR; \ 339 addi r3,r1,STACK_FRAME_OVERHEAD; \ 340 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) 341 342 #define DATA_STORAGE_EXCEPTION \ 343 START_EXCEPTION(DataStorage) \ 344 NORMAL_EXCEPTION_PROLOG; \ 345 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 346 stw r5,_ESR(r11); \ 347 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ 348 EXC_XFER_EE_LITE(0x0300, handle_page_fault) 349 350 #define INSTRUCTION_STORAGE_EXCEPTION \ 351 START_EXCEPTION(InstructionStorage) \ 352 NORMAL_EXCEPTION_PROLOG; \ 353 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 354 stw r5,_ESR(r11); \ 355 mr r4,r12; /* Pass SRR0 as arg2 */ \ 356 li r5,0; /* Pass zero as arg3 */ \ 357 EXC_XFER_EE_LITE(0x0400, handle_page_fault) 358 359 #define ALIGNMENT_EXCEPTION \ 360 START_EXCEPTION(Alignment) \ 361 NORMAL_EXCEPTION_PROLOG; \ 362 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ 363 stw r4,_DEAR(r11); \ 364 addi r3,r1,STACK_FRAME_OVERHEAD; \ 365 EXC_XFER_EE(0x0600, alignment_exception) 366 367 #define PROGRAM_EXCEPTION \ 368 START_EXCEPTION(Program) \ 369 NORMAL_EXCEPTION_PROLOG; \ 370 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ 371 stw r4,_ESR(r11); \ 372 addi r3,r1,STACK_FRAME_OVERHEAD; \ 373 EXC_XFER_STD(0x0700, program_check_exception) 374 375 #define DECREMENTER_EXCEPTION \ 376 START_EXCEPTION(Decrementer) \ 377 NORMAL_EXCEPTION_PROLOG; \ 378 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ 379 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ 380 addi r3,r1,STACK_FRAME_OVERHEAD; \ 381 EXC_XFER_LITE(0x0900, timer_interrupt) 382 383 #define FP_UNAVAILABLE_EXCEPTION \ 384 START_EXCEPTION(FloatingPointUnavailable) \ 385 NORMAL_EXCEPTION_PROLOG; \ 386 beq 1f; \ 387 bl load_up_fpu; /* if from user, just load it up */ \ 388 b fast_exception_return; \ 389 1: addi r3,r1,STACK_FRAME_OVERHEAD; \ 390 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) 391 392 #ifndef __ASSEMBLY__ 393 struct exception_regs { 394 unsigned long mas0; 395 unsigned long mas1; 396 unsigned long mas2; 397 unsigned long mas3; 398 unsigned long mas6; 399 unsigned long mas7; 400 unsigned long srr0; 401 unsigned long srr1; 402 unsigned long csrr0; 403 unsigned long csrr1; 404 unsigned long dsrr0; 405 unsigned long dsrr1; 406 unsigned long saved_ksp_limit; 407 }; 408 409 /* ensure this structure is always sized to a multiple of the stack alignment */ 410 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16) 411 412 #endif /* __ASSEMBLY__ */ 413 #endif /* __HEAD_BOOKE_H__ */ 414