1 #ifndef __HEAD_BOOKE_H__ 2 #define __HEAD_BOOKE_H__ 3 4 /* 5 * Macros used for common Book-e exception handling 6 */ 7 8 #define SET_IVOR(vector_number, vector_label) \ 9 li r26,vector_label@l; \ 10 mtspr SPRN_IVOR##vector_number,r26; \ 11 sync 12 13 #define NORMAL_EXCEPTION_PROLOG \ 14 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ 15 mtspr SPRN_SPRG1,r11; \ 16 mtspr SPRN_SPRG4W,r1; \ 17 mfcr r10; /* save CR in r10 for now */\ 18 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ 19 andi. r11,r11,MSR_PR; \ 20 beq 1f; \ 21 mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ 22 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ 23 addi r1,r1,THREAD_SIZE; \ 24 1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ 25 mr r11,r1; \ 26 stw r10,_CCR(r11); /* save various registers */\ 27 stw r12,GPR12(r11); \ 28 stw r9,GPR9(r11); \ 29 mfspr r10,SPRN_SPRG0; \ 30 stw r10,GPR10(r11); \ 31 mfspr r12,SPRN_SPRG1; \ 32 stw r12,GPR11(r11); \ 33 mflr r10; \ 34 stw r10,_LINK(r11); \ 35 mfspr r10,SPRN_SPRG4R; \ 36 mfspr r12,SPRN_SRR0; \ 37 stw r10,GPR1(r11); \ 38 mfspr r9,SPRN_SRR1; \ 39 stw r10,0(r11); \ 40 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 41 stw r0,GPR0(r11); \ 42 SAVE_4GPRS(3, r11); \ 43 SAVE_2GPRS(7, r11) 44 45 /* To handle the additional exception priority levels on 40x and Book-E 46 * processors we allocate a stack per additional priority level. 47 * 48 * On 40x critical is the only additional level 49 * On 44x/e500 we have critical and machine check 50 * On e200 we have critical and debug (machine check occurs via critical) 51 * 52 * Additionally we reserve a SPRG for each priority level so we can free up a 53 * GPR to use as the base for indirect access to the exception stacks. This 54 * is necessary since the MMU is always on, for Book-E parts, and the stacks 55 * are offset from KERNELBASE. 56 * 57 * There is some space optimization to be had here if desired. However 58 * to allow for a common kernel with support for debug exceptions either 59 * going to critical or their own debug level we aren't currently 60 * providing configurations that micro-optimize space usage. 61 */ 62 63 /* CRIT_SPRG only used in critical exception handling */ 64 #define CRIT_SPRG SPRN_SPRG2 65 /* MCHECK_SPRG only used in machine check exception handling */ 66 #define MCHECK_SPRG SPRN_SPRG6W 67 68 #define MCHECK_STACK_BASE mcheckirq_ctx 69 #define CRIT_STACK_BASE critirq_ctx 70 71 /* only on e500mc/e200 */ 72 #define DEBUG_STACK_BASE dbgirq_ctx 73 #ifdef CONFIG_PPC_E500MC 74 #define DEBUG_SPRG SPRN_SPRG9 75 #else 76 #define DEBUG_SPRG SPRN_SPRG6W 77 #endif 78 79 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 80 81 #ifdef CONFIG_SMP 82 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 83 mfspr r8,SPRN_PIR; \ 84 slwi r8,r8,2; \ 85 addis r8,r8,level##_STACK_BASE@ha; \ 86 lwz r8,level##_STACK_BASE@l(r8); \ 87 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 88 #else 89 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 90 lis r8,level##_STACK_BASE@ha; \ 91 lwz r8,level##_STACK_BASE@l(r8); \ 92 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 93 #endif 94 95 /* 96 * Exception prolog for critical/machine check exceptions. This is a 97 * little different from the normal exception prolog above since a 98 * critical/machine check exception can potentially occur at any point 99 * during normal exception processing. Thus we cannot use the same SPRG 100 * registers as the normal prolog above. Instead we use a portion of the 101 * critical/machine check exception stack at low physical addresses. 102 */ 103 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \ 104 mtspr exc_level##_SPRG,r8; \ 105 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ 106 stw r9,GPR9(r8); /* save various registers */\ 107 mfcr r9; /* save CR in r9 for now */\ 108 stw r10,GPR10(r8); \ 109 stw r11,GPR11(r8); \ 110 stw r9,_CCR(r8); /* save CR on stack */\ 111 mfspr r10,exc_level_srr1; /* check whether user or kernel */\ 112 andi. r10,r10,MSR_PR; \ 113 mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ 114 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ 115 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ 116 beq 1f; \ 117 /* COMING FROM USER MODE */ \ 118 stw r9,_CCR(r11); /* save CR */\ 119 lwz r10,GPR10(r8); /* copy regs from exception stack */\ 120 lwz r9,GPR9(r8); \ 121 stw r10,GPR10(r11); \ 122 lwz r10,GPR11(r8); \ 123 stw r9,GPR9(r11); \ 124 stw r10,GPR11(r11); \ 125 b 2f; \ 126 /* COMING FROM PRIV MODE */ \ 127 1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \ 128 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \ 129 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \ 130 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \ 131 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \ 132 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \ 133 mr r11,r8; \ 134 2: mfspr r8,exc_level##_SPRG; \ 135 stw r12,GPR12(r11); /* save various registers */\ 136 mflr r10; \ 137 stw r10,_LINK(r11); \ 138 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 139 stw r12,_DEAR(r11); /* since they may have had stuff */\ 140 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 141 stw r9,_ESR(r11); /* exception was taken */\ 142 mfspr r12,exc_level_srr0; \ 143 stw r1,GPR1(r11); \ 144 mfspr r9,exc_level_srr1; \ 145 stw r1,0(r11); \ 146 mr r1,r11; \ 147 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 148 stw r0,GPR0(r11); \ 149 SAVE_4GPRS(3, r11); \ 150 SAVE_2GPRS(7, r11) 151 152 #define CRITICAL_EXCEPTION_PROLOG \ 153 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1) 154 #define DEBUG_EXCEPTION_PROLOG \ 155 EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1) 156 #define MCHECK_EXCEPTION_PROLOG \ 157 EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1) 158 159 /* 160 * Exception vectors. 161 */ 162 #define START_EXCEPTION(label) \ 163 .align 5; \ 164 label: 165 166 #define FINISH_EXCEPTION(func) \ 167 bl transfer_to_handler_full; \ 168 .long func; \ 169 .long ret_from_except_full 170 171 #define EXCEPTION(n, label, hdlr, xfer) \ 172 START_EXCEPTION(label); \ 173 NORMAL_EXCEPTION_PROLOG; \ 174 addi r3,r1,STACK_FRAME_OVERHEAD; \ 175 xfer(n, hdlr) 176 177 #define CRITICAL_EXCEPTION(n, label, hdlr) \ 178 START_EXCEPTION(label); \ 179 CRITICAL_EXCEPTION_PROLOG; \ 180 addi r3,r1,STACK_FRAME_OVERHEAD; \ 181 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 182 NOCOPY, crit_transfer_to_handler, \ 183 ret_from_crit_exc) 184 185 #define MCHECK_EXCEPTION(n, label, hdlr) \ 186 START_EXCEPTION(label); \ 187 MCHECK_EXCEPTION_PROLOG; \ 188 mfspr r5,SPRN_ESR; \ 189 stw r5,_ESR(r11); \ 190 addi r3,r1,STACK_FRAME_OVERHEAD; \ 191 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 192 NOCOPY, mcheck_transfer_to_handler, \ 193 ret_from_mcheck_exc) 194 195 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ 196 li r10,trap; \ 197 stw r10,_TRAP(r11); \ 198 lis r10,msr@h; \ 199 ori r10,r10,msr@l; \ 200 copyee(r10, r9); \ 201 bl tfer; \ 202 .long hdlr; \ 203 .long ret 204 205 #define COPY_EE(d, s) rlwimi d,s,0,16,16 206 #define NOCOPY(d, s) 207 208 #define EXC_XFER_STD(n, hdlr) \ 209 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ 210 ret_from_except_full) 211 212 #define EXC_XFER_LITE(n, hdlr) \ 213 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ 214 ret_from_except) 215 216 #define EXC_XFER_EE(n, hdlr) \ 217 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ 218 ret_from_except_full) 219 220 #define EXC_XFER_EE_LITE(n, hdlr) \ 221 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ 222 ret_from_except) 223 224 /* Check for a single step debug exception while in an exception 225 * handler before state has been saved. This is to catch the case 226 * where an instruction that we are trying to single step causes 227 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 228 * the exception handler generates a single step debug exception. 229 * 230 * If we get a debug trap on the first instruction of an exception handler, 231 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 232 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 233 * The exception handler was handling a non-critical interrupt, so it will 234 * save (and later restore) the MSR via SPRN_CSRR1, which will still have 235 * the MSR_DE bit set. 236 */ 237 #define DEBUG_DEBUG_EXCEPTION \ 238 START_EXCEPTION(DebugDebug); \ 239 DEBUG_EXCEPTION_PROLOG; \ 240 \ 241 /* \ 242 * If there is a single step or branch-taken exception in an \ 243 * exception entry sequence, it was probably meant to apply to \ 244 * the code where the exception occurred (since exception entry \ 245 * doesn't turn off DE automatically). We simulate the effect \ 246 * of turning off DE on entry to an exception handler by turning \ 247 * off DE in the DSRR1 value and clearing the debug status. \ 248 */ \ 249 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 250 andis. r10,r10,DBSR_IC@h; \ 251 beq+ 2f; \ 252 \ 253 lis r10,KERNELBASE@h; /* check if exception in vectors */ \ 254 ori r10,r10,KERNELBASE@l; \ 255 cmplw r12,r10; \ 256 blt+ 2f; /* addr below exception vectors */ \ 257 \ 258 lis r10,DebugDebug@h; \ 259 ori r10,r10,DebugDebug@l; \ 260 cmplw r12,r10; \ 261 bgt+ 2f; /* addr above exception vectors */ \ 262 \ 263 /* here it looks like we got an inappropriate debug exception. */ \ 264 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ 265 lis r10,DBSR_IC@h; /* clear the IC event */ \ 266 mtspr SPRN_DBSR,r10; \ 267 /* restore state and get out */ \ 268 lwz r10,_CCR(r11); \ 269 lwz r0,GPR0(r11); \ 270 lwz r1,GPR1(r11); \ 271 mtcrf 0x80,r10; \ 272 mtspr SPRN_DSRR0,r12; \ 273 mtspr SPRN_DSRR1,r9; \ 274 lwz r9,GPR9(r11); \ 275 lwz r12,GPR12(r11); \ 276 mtspr DEBUG_SPRG,r8; \ 277 BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \ 278 lwz r10,GPR10(r8); \ 279 lwz r11,GPR11(r8); \ 280 mfspr r8,DEBUG_SPRG; \ 281 \ 282 RFDI; \ 283 b .; \ 284 \ 285 /* continue normal handling for a debug exception... */ \ 286 2: mfspr r4,SPRN_DBSR; \ 287 addi r3,r1,STACK_FRAME_OVERHEAD; \ 288 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) 289 290 #define DEBUG_CRIT_EXCEPTION \ 291 START_EXCEPTION(DebugCrit); \ 292 CRITICAL_EXCEPTION_PROLOG; \ 293 \ 294 /* \ 295 * If there is a single step or branch-taken exception in an \ 296 * exception entry sequence, it was probably meant to apply to \ 297 * the code where the exception occurred (since exception entry \ 298 * doesn't turn off DE automatically). We simulate the effect \ 299 * of turning off DE on entry to an exception handler by turning \ 300 * off DE in the CSRR1 value and clearing the debug status. \ 301 */ \ 302 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 303 andis. r10,r10,DBSR_IC@h; \ 304 beq+ 2f; \ 305 \ 306 lis r10,KERNELBASE@h; /* check if exception in vectors */ \ 307 ori r10,r10,KERNELBASE@l; \ 308 cmplw r12,r10; \ 309 blt+ 2f; /* addr below exception vectors */ \ 310 \ 311 lis r10,DebugCrit@h; \ 312 ori r10,r10,DebugCrit@l; \ 313 cmplw r12,r10; \ 314 bgt+ 2f; /* addr above exception vectors */ \ 315 \ 316 /* here it looks like we got an inappropriate debug exception. */ \ 317 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ 318 lis r10,DBSR_IC@h; /* clear the IC event */ \ 319 mtspr SPRN_DBSR,r10; \ 320 /* restore state and get out */ \ 321 lwz r10,_CCR(r11); \ 322 lwz r0,GPR0(r11); \ 323 lwz r1,GPR1(r11); \ 324 mtcrf 0x80,r10; \ 325 mtspr SPRN_CSRR0,r12; \ 326 mtspr SPRN_CSRR1,r9; \ 327 lwz r9,GPR9(r11); \ 328 lwz r12,GPR12(r11); \ 329 mtspr CRIT_SPRG,r8; \ 330 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ 331 lwz r10,GPR10(r8); \ 332 lwz r11,GPR11(r8); \ 333 mfspr r8,CRIT_SPRG; \ 334 \ 335 rfci; \ 336 b .; \ 337 \ 338 /* continue normal handling for a critical exception... */ \ 339 2: mfspr r4,SPRN_DBSR; \ 340 addi r3,r1,STACK_FRAME_OVERHEAD; \ 341 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) 342 343 #define DATA_STORAGE_EXCEPTION \ 344 START_EXCEPTION(DataStorage) \ 345 NORMAL_EXCEPTION_PROLOG; \ 346 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 347 stw r5,_ESR(r11); \ 348 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ 349 EXC_XFER_EE_LITE(0x0300, handle_page_fault) 350 351 #define INSTRUCTION_STORAGE_EXCEPTION \ 352 START_EXCEPTION(InstructionStorage) \ 353 NORMAL_EXCEPTION_PROLOG; \ 354 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 355 stw r5,_ESR(r11); \ 356 mr r4,r12; /* Pass SRR0 as arg2 */ \ 357 li r5,0; /* Pass zero as arg3 */ \ 358 EXC_XFER_EE_LITE(0x0400, handle_page_fault) 359 360 #define ALIGNMENT_EXCEPTION \ 361 START_EXCEPTION(Alignment) \ 362 NORMAL_EXCEPTION_PROLOG; \ 363 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ 364 stw r4,_DEAR(r11); \ 365 addi r3,r1,STACK_FRAME_OVERHEAD; \ 366 EXC_XFER_EE(0x0600, alignment_exception) 367 368 #define PROGRAM_EXCEPTION \ 369 START_EXCEPTION(Program) \ 370 NORMAL_EXCEPTION_PROLOG; \ 371 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ 372 stw r4,_ESR(r11); \ 373 addi r3,r1,STACK_FRAME_OVERHEAD; \ 374 EXC_XFER_STD(0x0700, program_check_exception) 375 376 #define DECREMENTER_EXCEPTION \ 377 START_EXCEPTION(Decrementer) \ 378 NORMAL_EXCEPTION_PROLOG; \ 379 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ 380 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ 381 addi r3,r1,STACK_FRAME_OVERHEAD; \ 382 EXC_XFER_LITE(0x0900, timer_interrupt) 383 384 #define FP_UNAVAILABLE_EXCEPTION \ 385 START_EXCEPTION(FloatingPointUnavailable) \ 386 NORMAL_EXCEPTION_PROLOG; \ 387 beq 1f; \ 388 bl load_up_fpu; /* if from user, just load it up */ \ 389 b fast_exception_return; \ 390 1: addi r3,r1,STACK_FRAME_OVERHEAD; \ 391 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) 392 393 #ifndef __ASSEMBLY__ 394 struct exception_regs { 395 unsigned long mas0; 396 unsigned long mas1; 397 unsigned long mas2; 398 unsigned long mas3; 399 unsigned long mas6; 400 unsigned long mas7; 401 unsigned long srr0; 402 unsigned long srr1; 403 unsigned long csrr0; 404 unsigned long csrr1; 405 unsigned long dsrr0; 406 unsigned long dsrr1; 407 unsigned long saved_ksp_limit; 408 }; 409 410 /* ensure this structure is always sized to a multiple of the stack alignment */ 411 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16) 412 413 #endif /* __ASSEMBLY__ */ 414 #endif /* __HEAD_BOOKE_H__ */ 415