1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __HEAD_BOOKE_H__ 3 #define __HEAD_BOOKE_H__ 4 5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */ 6 #include <asm/kvm_asm.h> 7 #include <asm/kvm_booke_hv_asm.h> 8 9 /* 10 * Macros used for common Book-e exception handling 11 */ 12 13 #define SET_IVOR(vector_number, vector_label) \ 14 li r26,vector_label@l; \ 15 mtspr SPRN_IVOR##vector_number,r26; \ 16 sync 17 18 #if (THREAD_SHIFT < 15) 19 #define ALLOC_STACK_FRAME(reg, val) \ 20 addi reg,reg,val 21 #else 22 #define ALLOC_STACK_FRAME(reg, val) \ 23 addis reg,reg,val@ha; \ 24 addi reg,reg,val@l 25 #endif 26 27 /* 28 * Macro used to get to thread save registers. 29 * Note that entries 0-3 are used for the prolog code, and the remaining 30 * entries are available for specific exception use in the event a handler 31 * requires more than 4 scratch registers. 32 */ 33 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4)) 34 35 #ifdef CONFIG_PPC_FSL_BOOK3E 36 #define BOOKE_CLEAR_BTB(reg) \ 37 START_BTB_FLUSH_SECTION \ 38 BTB_FLUSH(reg) \ 39 END_BTB_FLUSH_SECTION 40 #else 41 #define BOOKE_CLEAR_BTB(reg) 42 #endif 43 44 45 #define NORMAL_EXCEPTION_PROLOG(intno) \ 46 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 47 mfspr r10, SPRN_SPRG_THREAD; \ 48 stw r11, THREAD_NORMSAVE(0)(r10); \ 49 stw r13, THREAD_NORMSAVE(2)(r10); \ 50 mfcr r13; /* save CR in r13 for now */\ 51 mfspr r11, SPRN_SRR1; \ 52 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ 53 andi. r11, r11, MSR_PR; /* check whether user or kernel */\ 54 mr r11, r1; \ 55 beq 1f; \ 56 BOOKE_CLEAR_BTB(r11) \ 57 /* if from user, start at top of this thread's kernel stack */ \ 58 lwz r11, THREAD_INFO-THREAD(r10); \ 59 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ 60 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \ 61 stw r13, _CCR(r11); /* save various registers */ \ 62 stw r12,GPR12(r11); \ 63 stw r9,GPR9(r11); \ 64 mfspr r13, SPRN_SPRG_RSCRATCH0; \ 65 stw r13, GPR10(r11); \ 66 lwz r12, THREAD_NORMSAVE(0)(r10); \ 67 stw r12,GPR11(r11); \ 68 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \ 69 mflr r10; \ 70 stw r10,_LINK(r11); \ 71 mfspr r12,SPRN_SRR0; \ 72 stw r1, GPR1(r11); \ 73 mfspr r9,SPRN_SRR1; \ 74 stw r1, 0(r11); \ 75 mr r1, r11; \ 76 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 77 stw r0,GPR0(r11); \ 78 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \ 79 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \ 80 stw r10, 8(r11); \ 81 SAVE_4GPRS(3, r11); \ 82 SAVE_2GPRS(7, r11) 83 84 /* To handle the additional exception priority levels on 40x and Book-E 85 * processors we allocate a stack per additional priority level. 86 * 87 * On 40x critical is the only additional level 88 * On 44x/e500 we have critical and machine check 89 * On e200 we have critical and debug (machine check occurs via critical) 90 * 91 * Additionally we reserve a SPRG for each priority level so we can free up a 92 * GPR to use as the base for indirect access to the exception stacks. This 93 * is necessary since the MMU is always on, for Book-E parts, and the stacks 94 * are offset from KERNELBASE. 95 * 96 * There is some space optimization to be had here if desired. However 97 * to allow for a common kernel with support for debug exceptions either 98 * going to critical or their own debug level we aren't currently 99 * providing configurations that micro-optimize space usage. 100 */ 101 102 #define MC_STACK_BASE mcheckirq_ctx 103 #define CRIT_STACK_BASE critirq_ctx 104 105 /* only on e500mc/e200 */ 106 #define DBG_STACK_BASE dbgirq_ctx 107 108 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 109 110 #ifdef CONFIG_SMP 111 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 112 mfspr r8,SPRN_PIR; \ 113 slwi r8,r8,2; \ 114 addis r8,r8,level##_STACK_BASE@ha; \ 115 lwz r8,level##_STACK_BASE@l(r8); \ 116 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 117 #else 118 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 119 lis r8,level##_STACK_BASE@ha; \ 120 lwz r8,level##_STACK_BASE@l(r8); \ 121 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 122 #endif 123 124 /* 125 * Exception prolog for critical/machine check exceptions. This is a 126 * little different from the normal exception prolog above since a 127 * critical/machine check exception can potentially occur at any point 128 * during normal exception processing. Thus we cannot use the same SPRG 129 * registers as the normal prolog above. Instead we use a portion of the 130 * critical/machine check exception stack at low physical addresses. 131 */ 132 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \ 133 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \ 134 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ 135 stw r9,GPR9(r8); /* save various registers */\ 136 mfcr r9; /* save CR in r9 for now */\ 137 stw r10,GPR10(r8); \ 138 stw r11,GPR11(r8); \ 139 stw r9,_CCR(r8); /* save CR on stack */\ 140 mfspr r11,exc_level_srr1; /* check whether user or kernel */\ 141 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ 142 BOOKE_CLEAR_BTB(r10) \ 143 andi. r11,r11,MSR_PR; \ 144 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 145 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ 146 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ 147 beq 1f; \ 148 /* COMING FROM USER MODE */ \ 149 stw r9,_CCR(r11); /* save CR */\ 150 lwz r10,GPR10(r8); /* copy regs from exception stack */\ 151 lwz r9,GPR9(r8); \ 152 stw r10,GPR10(r11); \ 153 lwz r10,GPR11(r8); \ 154 stw r9,GPR9(r11); \ 155 stw r10,GPR11(r11); \ 156 b 2f; \ 157 /* COMING FROM PRIV MODE */ \ 158 1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \ 159 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \ 160 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \ 161 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \ 162 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \ 163 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \ 164 mr r11,r8; \ 165 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \ 166 stw r12,GPR12(r11); /* save various registers */\ 167 mflr r10; \ 168 stw r10,_LINK(r11); \ 169 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 170 stw r12,_DEAR(r11); /* since they may have had stuff */\ 171 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 172 stw r9,_ESR(r11); /* exception was taken */\ 173 mfspr r12,exc_level_srr0; \ 174 stw r1,GPR1(r11); \ 175 mfspr r9,exc_level_srr1; \ 176 stw r1,0(r11); \ 177 mr r1,r11; \ 178 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 179 stw r0,GPR0(r11); \ 180 SAVE_4GPRS(3, r11); \ 181 SAVE_2GPRS(7, r11) 182 183 #define CRITICAL_EXCEPTION_PROLOG(intno) \ 184 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1) 185 #define DEBUG_EXCEPTION_PROLOG \ 186 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1) 187 #define MCHECK_EXCEPTION_PROLOG \ 188 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \ 189 SPRN_MCSRR0, SPRN_MCSRR1) 190 191 /* 192 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite 193 * being delivered to the host. This exception can only happen 194 * inside a KVM guest -- so we just handle up to the DO_KVM rather 195 * than try to fit this into one of the existing prolog macros. 196 */ 197 #define GUEST_DOORBELL_EXCEPTION \ 198 START_EXCEPTION(GuestDoorbell); \ 199 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 200 mfspr r10, SPRN_SPRG_THREAD; \ 201 stw r11, THREAD_NORMSAVE(0)(r10); \ 202 mfspr r11, SPRN_SRR1; \ 203 stw r13, THREAD_NORMSAVE(2)(r10); \ 204 mfcr r13; /* save CR in r13 for now */\ 205 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \ 206 trap 207 208 /* 209 * Exception vectors. 210 */ 211 #define START_EXCEPTION(label) \ 212 .align 5; \ 213 label: 214 215 #define EXCEPTION(n, intno, label, hdlr, xfer) \ 216 START_EXCEPTION(label); \ 217 NORMAL_EXCEPTION_PROLOG(intno); \ 218 addi r3,r1,STACK_FRAME_OVERHEAD; \ 219 xfer(n, hdlr) 220 221 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \ 222 START_EXCEPTION(label); \ 223 CRITICAL_EXCEPTION_PROLOG(intno); \ 224 addi r3,r1,STACK_FRAME_OVERHEAD; \ 225 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 226 NOCOPY, crit_transfer_to_handler, \ 227 ret_from_crit_exc) 228 229 #define MCHECK_EXCEPTION(n, label, hdlr) \ 230 START_EXCEPTION(label); \ 231 MCHECK_EXCEPTION_PROLOG; \ 232 mfspr r5,SPRN_ESR; \ 233 stw r5,_ESR(r11); \ 234 addi r3,r1,STACK_FRAME_OVERHEAD; \ 235 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 236 NOCOPY, mcheck_transfer_to_handler, \ 237 ret_from_mcheck_exc) 238 239 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ 240 li r10,trap; \ 241 stw r10,_TRAP(r11); \ 242 lis r10,msr@h; \ 243 ori r10,r10,msr@l; \ 244 copyee(r10, r9); \ 245 bl tfer; \ 246 .long hdlr; \ 247 .long ret 248 249 #define COPY_EE(d, s) rlwimi d,s,0,16,16 250 #define NOCOPY(d, s) 251 252 #define EXC_XFER_STD(n, hdlr) \ 253 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ 254 ret_from_except_full) 255 256 #define EXC_XFER_LITE(n, hdlr) \ 257 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ 258 ret_from_except) 259 260 #define EXC_XFER_EE(n, hdlr) \ 261 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ 262 ret_from_except_full) 263 264 #define EXC_XFER_EE_LITE(n, hdlr) \ 265 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ 266 ret_from_except) 267 268 /* Check for a single step debug exception while in an exception 269 * handler before state has been saved. This is to catch the case 270 * where an instruction that we are trying to single step causes 271 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 272 * the exception handler generates a single step debug exception. 273 * 274 * If we get a debug trap on the first instruction of an exception handler, 275 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 276 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 277 * The exception handler was handling a non-critical interrupt, so it will 278 * save (and later restore) the MSR via SPRN_CSRR1, which will still have 279 * the MSR_DE bit set. 280 */ 281 #define DEBUG_DEBUG_EXCEPTION \ 282 START_EXCEPTION(DebugDebug); \ 283 DEBUG_EXCEPTION_PROLOG; \ 284 \ 285 /* \ 286 * If there is a single step or branch-taken exception in an \ 287 * exception entry sequence, it was probably meant to apply to \ 288 * the code where the exception occurred (since exception entry \ 289 * doesn't turn off DE automatically). We simulate the effect \ 290 * of turning off DE on entry to an exception handler by turning \ 291 * off DE in the DSRR1 value and clearing the debug status. \ 292 */ \ 293 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 294 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 295 beq+ 2f; \ 296 \ 297 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 298 ori r10,r10,interrupt_base@l; \ 299 cmplw r12,r10; \ 300 blt+ 2f; /* addr below exception vectors */ \ 301 \ 302 lis r10,interrupt_end@h; \ 303 ori r10,r10,interrupt_end@l; \ 304 cmplw r12,r10; \ 305 bgt+ 2f; /* addr above exception vectors */ \ 306 \ 307 /* here it looks like we got an inappropriate debug exception. */ \ 308 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ 309 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 310 mtspr SPRN_DBSR,r10; \ 311 /* restore state and get out */ \ 312 lwz r10,_CCR(r11); \ 313 lwz r0,GPR0(r11); \ 314 lwz r1,GPR1(r11); \ 315 mtcrf 0x80,r10; \ 316 mtspr SPRN_DSRR0,r12; \ 317 mtspr SPRN_DSRR1,r9; \ 318 lwz r9,GPR9(r11); \ 319 lwz r12,GPR12(r11); \ 320 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \ 321 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \ 322 lwz r10,GPR10(r8); \ 323 lwz r11,GPR11(r8); \ 324 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \ 325 \ 326 PPC_RFDI; \ 327 b .; \ 328 \ 329 /* continue normal handling for a debug exception... */ \ 330 2: mfspr r4,SPRN_DBSR; \ 331 addi r3,r1,STACK_FRAME_OVERHEAD; \ 332 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) 333 334 #define DEBUG_CRIT_EXCEPTION \ 335 START_EXCEPTION(DebugCrit); \ 336 CRITICAL_EXCEPTION_PROLOG(DEBUG); \ 337 \ 338 /* \ 339 * If there is a single step or branch-taken exception in an \ 340 * exception entry sequence, it was probably meant to apply to \ 341 * the code where the exception occurred (since exception entry \ 342 * doesn't turn off DE automatically). We simulate the effect \ 343 * of turning off DE on entry to an exception handler by turning \ 344 * off DE in the CSRR1 value and clearing the debug status. \ 345 */ \ 346 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 347 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 348 beq+ 2f; \ 349 \ 350 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 351 ori r10,r10,interrupt_base@l; \ 352 cmplw r12,r10; \ 353 blt+ 2f; /* addr below exception vectors */ \ 354 \ 355 lis r10,interrupt_end@h; \ 356 ori r10,r10,interrupt_end@l; \ 357 cmplw r12,r10; \ 358 bgt+ 2f; /* addr above exception vectors */ \ 359 \ 360 /* here it looks like we got an inappropriate debug exception. */ \ 361 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ 362 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 363 mtspr SPRN_DBSR,r10; \ 364 /* restore state and get out */ \ 365 lwz r10,_CCR(r11); \ 366 lwz r0,GPR0(r11); \ 367 lwz r1,GPR1(r11); \ 368 mtcrf 0x80,r10; \ 369 mtspr SPRN_CSRR0,r12; \ 370 mtspr SPRN_CSRR1,r9; \ 371 lwz r9,GPR9(r11); \ 372 lwz r12,GPR12(r11); \ 373 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \ 374 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ 375 lwz r10,GPR10(r8); \ 376 lwz r11,GPR11(r8); \ 377 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \ 378 \ 379 rfci; \ 380 b .; \ 381 \ 382 /* continue normal handling for a critical exception... */ \ 383 2: mfspr r4,SPRN_DBSR; \ 384 addi r3,r1,STACK_FRAME_OVERHEAD; \ 385 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) 386 387 #define DATA_STORAGE_EXCEPTION \ 388 START_EXCEPTION(DataStorage) \ 389 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \ 390 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 391 stw r5,_ESR(r11); \ 392 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ 393 EXC_XFER_LITE(0x0300, handle_page_fault) 394 395 #define INSTRUCTION_STORAGE_EXCEPTION \ 396 START_EXCEPTION(InstructionStorage) \ 397 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \ 398 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 399 stw r5,_ESR(r11); \ 400 mr r4,r12; /* Pass SRR0 as arg2 */ \ 401 li r5,0; /* Pass zero as arg3 */ \ 402 EXC_XFER_LITE(0x0400, handle_page_fault) 403 404 #define ALIGNMENT_EXCEPTION \ 405 START_EXCEPTION(Alignment) \ 406 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \ 407 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ 408 stw r4,_DEAR(r11); \ 409 addi r3,r1,STACK_FRAME_OVERHEAD; \ 410 EXC_XFER_EE(0x0600, alignment_exception) 411 412 #define PROGRAM_EXCEPTION \ 413 START_EXCEPTION(Program) \ 414 NORMAL_EXCEPTION_PROLOG(PROGRAM); \ 415 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ 416 stw r4,_ESR(r11); \ 417 addi r3,r1,STACK_FRAME_OVERHEAD; \ 418 EXC_XFER_STD(0x0700, program_check_exception) 419 420 #define DECREMENTER_EXCEPTION \ 421 START_EXCEPTION(Decrementer) \ 422 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \ 423 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ 424 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ 425 addi r3,r1,STACK_FRAME_OVERHEAD; \ 426 EXC_XFER_LITE(0x0900, timer_interrupt) 427 428 #define FP_UNAVAILABLE_EXCEPTION \ 429 START_EXCEPTION(FloatingPointUnavailable) \ 430 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \ 431 beq 1f; \ 432 bl load_up_fpu; /* if from user, just load it up */ \ 433 b fast_exception_return; \ 434 1: addi r3,r1,STACK_FRAME_OVERHEAD; \ 435 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) 436 437 #ifndef __ASSEMBLY__ 438 struct exception_regs { 439 unsigned long mas0; 440 unsigned long mas1; 441 unsigned long mas2; 442 unsigned long mas3; 443 unsigned long mas6; 444 unsigned long mas7; 445 unsigned long srr0; 446 unsigned long srr1; 447 unsigned long csrr0; 448 unsigned long csrr1; 449 unsigned long dsrr0; 450 unsigned long dsrr1; 451 unsigned long saved_ksp_limit; 452 }; 453 454 /* ensure this structure is always sized to a multiple of the stack alignment */ 455 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16) 456 457 #endif /* __ASSEMBLY__ */ 458 #endif /* __HEAD_BOOKE_H__ */ 459