1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33#include <asm/export.h> 34 35#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 36/* By simply checking Address >= 0x80000000, we know if its a kernel address */ 37#define SIMPLE_KERNEL_ADDRESS 1 38#endif 39 40/* 41 * We need an ITLB miss handler for kernel addresses if: 42 * - Either we have modules 43 * - Or we have not pinned the first 8M 44 */ 45#if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \ 46 defined(CONFIG_DEBUG_PAGEALLOC) 47#define ITLB_MISS_KERNEL 1 48#endif 49 50/* 51 * Value for the bits that have fixed value in RPN entries. 52 * Also used for tagging DAR for DTLBerror. 53 */ 54#define RPN_PATTERN 0x00f0 55 56#define PAGE_SHIFT_512K 19 57#define PAGE_SHIFT_8M 23 58 59 __HEAD 60_ENTRY(_stext); 61_ENTRY(_start); 62 63/* MPC8xx 64 * This port was done on an MBX board with an 860. Right now I only 65 * support an ELF compressed (zImage) boot from EPPC-Bug because the 66 * code there loads up some registers before calling us: 67 * r3: ptr to board info data 68 * r4: initrd_start or if no initrd then 0 69 * r5: initrd_end - unused if r4 is 0 70 * r6: Start of command line string 71 * r7: End of command line string 72 * 73 * I decided to use conditional compilation instead of checking PVR and 74 * adding more processor specific branches around code I don't need. 75 * Since this is an embedded processor, I also appreciate any memory 76 * savings I can get. 77 * 78 * The MPC8xx does not have any BATs, but it supports large page sizes. 79 * We first initialize the MMU to support 8M byte pages, then load one 80 * entry into each of the instruction and data TLBs to map the first 81 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 82 * the "internal" processor registers before MMU_init is called. 83 * 84 * -- Dan 85 */ 86 .globl __start 87__start: 88 mr r31,r3 /* save device tree ptr */ 89 90 /* We have to turn on the MMU right away so we get cache modes 91 * set correctly. 92 */ 93 bl initial_mmu 94 95/* We now have the lower 8 Meg mapped into TLB entries, and the caches 96 * ready to work. 97 */ 98 99turn_on_mmu: 100 mfmsr r0 101 ori r0,r0,MSR_DR|MSR_IR 102 mtspr SPRN_SRR1,r0 103 lis r0,start_here@h 104 ori r0,r0,start_here@l 105 mtspr SPRN_SRR0,r0 106 rfi /* enables MMU */ 107 108/* 109 * Exception entry code. This code runs with address translation 110 * turned off, i.e. using physical addresses. 111 * We assume sprg3 has the physical address of the current 112 * task's thread_struct. 113 */ 114#define EXCEPTION_PROLOG \ 115 mtspr SPRN_SPRG_SCRATCH0, r10; \ 116 mtspr SPRN_SPRG_SCRATCH1, r11; \ 117 mfcr r10; \ 118 EXCEPTION_PROLOG_1; \ 119 EXCEPTION_PROLOG_2 120 121#define EXCEPTION_PROLOG_1 \ 122 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 123 andi. r11,r11,MSR_PR; \ 124 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 125 beq 1f; \ 126 mfspr r11,SPRN_SPRG_THREAD; \ 127 lwz r11,THREAD_INFO-THREAD(r11); \ 128 addi r11,r11,THREAD_SIZE; \ 129 tophys(r11,r11); \ 1301: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 131 132 133#define EXCEPTION_PROLOG_2 \ 134 stw r10,_CCR(r11); /* save registers */ \ 135 stw r12,GPR12(r11); \ 136 stw r9,GPR9(r11); \ 137 mfspr r10,SPRN_SPRG_SCRATCH0; \ 138 stw r10,GPR10(r11); \ 139 mfspr r12,SPRN_SPRG_SCRATCH1; \ 140 stw r12,GPR11(r11); \ 141 mflr r10; \ 142 stw r10,_LINK(r11); \ 143 mfspr r12,SPRN_SRR0; \ 144 mfspr r9,SPRN_SRR1; \ 145 stw r1,GPR1(r11); \ 146 stw r1,0(r11); \ 147 tovirt(r1,r11); /* set new kernel sp */ \ 148 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 149 mtmsr r10; \ 150 stw r0,GPR0(r11); \ 151 SAVE_4GPRS(3, r11); \ 152 SAVE_2GPRS(7, r11) 153 154/* 155 * Note: code which follows this uses cr0.eq (set if from kernel), 156 * r11, r12 (SRR0), and r9 (SRR1). 157 * 158 * Note2: once we have set r1 we are in a position to take exceptions 159 * again, and we could thus set MSR:RI at that point. 160 */ 161 162/* 163 * Exception vectors. 164 */ 165#define EXCEPTION(n, label, hdlr, xfer) \ 166 . = n; \ 167label: \ 168 EXCEPTION_PROLOG; \ 169 addi r3,r1,STACK_FRAME_OVERHEAD; \ 170 xfer(n, hdlr) 171 172#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 173 li r10,trap; \ 174 stw r10,_TRAP(r11); \ 175 li r10,MSR_KERNEL; \ 176 copyee(r10, r9); \ 177 bl tfer; \ 178i##n: \ 179 .long hdlr; \ 180 .long ret 181 182#define COPY_EE(d, s) rlwimi d,s,0,16,16 183#define NOCOPY(d, s) 184 185#define EXC_XFER_STD(n, hdlr) \ 186 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 187 ret_from_except_full) 188 189#define EXC_XFER_LITE(n, hdlr) \ 190 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 191 ret_from_except) 192 193#define EXC_XFER_EE(n, hdlr) \ 194 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 195 ret_from_except_full) 196 197#define EXC_XFER_EE_LITE(n, hdlr) \ 198 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 199 ret_from_except) 200 201/* System reset */ 202 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD) 203 204/* Machine check */ 205 . = 0x200 206MachineCheck: 207 EXCEPTION_PROLOG 208 mfspr r4,SPRN_DAR 209 stw r4,_DAR(r11) 210 li r5,RPN_PATTERN 211 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 212 mfspr r5,SPRN_DSISR 213 stw r5,_DSISR(r11) 214 addi r3,r1,STACK_FRAME_OVERHEAD 215 EXC_XFER_STD(0x200, machine_check_exception) 216 217/* Data access exception. 218 * This is "never generated" by the MPC8xx. 219 */ 220 . = 0x300 221DataAccess: 222 223/* Instruction access exception. 224 * This is "never generated" by the MPC8xx. 225 */ 226 . = 0x400 227InstructionAccess: 228 229/* External interrupt */ 230 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 231 232/* Alignment exception */ 233 . = 0x600 234Alignment: 235 EXCEPTION_PROLOG 236 mfspr r4,SPRN_DAR 237 stw r4,_DAR(r11) 238 li r5,RPN_PATTERN 239 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 240 mfspr r5,SPRN_DSISR 241 stw r5,_DSISR(r11) 242 addi r3,r1,STACK_FRAME_OVERHEAD 243 EXC_XFER_EE(0x600, alignment_exception) 244 245/* Program check exception */ 246 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 247 248/* No FPU on MPC8xx. This exception is not supposed to happen. 249*/ 250 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 251 252/* Decrementer */ 253 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 254 255 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 256 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 257 258/* System call */ 259 . = 0xc00 260SystemCall: 261 EXCEPTION_PROLOG 262 EXC_XFER_EE_LITE(0xc00, DoSyscall) 263 264/* Single step - not used on 601 */ 265 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 266 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 267 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 268 269/* On the MPC8xx, this is a software emulation interrupt. It occurs 270 * for all unimplemented and illegal instructions. 271 */ 272 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD) 273 274 . = 0x1100 275/* 276 * For the MPC8xx, this is a software tablewalk to load the instruction 277 * TLB. The task switch loads the M_TW register with the pointer to the first 278 * level table. 279 * If we discover there is no second level table (value is zero) or if there 280 * is an invalid pte, we load that into the TLB, which causes another fault 281 * into the TLB Error interrupt where we can handle such problems. 282 * We have to use the MD_xxx registers for the tablewalk because the 283 * equivalent MI_xxx registers only perform the attribute functions. 284 */ 285 286#ifdef CONFIG_8xx_CPU15 287#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 288 addi tmp, addr, PAGE_SIZE; \ 289 tlbie tmp; \ 290 addi tmp, addr, -PAGE_SIZE; \ 291 tlbie tmp 292#else 293#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 294#endif 295 296InstructionTLBMiss: 297 mtspr SPRN_SPRG_SCRATCH0, r10 298 mtspr SPRN_SPRG_SCRATCH1, r11 299#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 300 mtspr SPRN_SPRG_SCRATCH2, r12 301#endif 302 303 /* If we are faulting a kernel address, we have to use the 304 * kernel page tables. 305 */ 306 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 307 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 308 /* Only modules will cause ITLB Misses as we always 309 * pin the first 8MB of kernel memory */ 310#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 311 mfcr r12 312#endif 313#ifdef ITLB_MISS_KERNEL 314#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) 315 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ 316#else 317 rlwinm r11, r10, 16, 0xfff8 318 cmpli cr0, r11, PAGE_OFFSET@h 319#ifndef CONFIG_PIN_TLB_TEXT 320 /* It is assumed that kernel code fits into the first 8M page */ 321_ENTRY(ITLBMiss_cmp) 322 cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h 323#endif 324#endif 325#endif 326 mfspr r11, SPRN_M_TW /* Get level 1 table */ 327#ifdef ITLB_MISS_KERNEL 328#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) 329 beq+ 3f 330#else 331 blt+ 3f 332#endif 333#ifndef CONFIG_PIN_TLB_TEXT 334 blt cr7, ITLBMissLinear 335#endif 336 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3373: 338#endif 339 /* Insert level 1 index */ 340 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 341 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 342 343 /* Extract level 2 index */ 344 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 345#ifdef CONFIG_HUGETLB_PAGE 346 mtcr r11 347 bt- 28, 10f /* bit 28 = Large page (8M) */ 348 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */ 349#endif 350 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 351 lwz r10, 0(r10) /* Get the pte */ 3524: 353#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 354 mtcr r12 355#endif 356 357#ifdef CONFIG_SWAP 358 rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1 359#endif 360 /* Load the MI_TWC with the attributes for this "segment." */ 361 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 362 363 li r11, RPN_PATTERN | 0x200 364 /* The Linux PTE won't go exactly into the MMU TLB. 365 * Software indicator bits 20 and 23 must be clear. 366 * Software indicator bits 22, 24, 25, 26, and 27 must be 367 * set. All other Linux PTE bits control the behavior 368 * of the MMU. 369 */ 370 rlwimi r11, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ 371 rlwimi r10, r11, 0, 0x0ff0 /* Set 22, 24-27, clear 20,23 */ 372 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 373 374 /* Restore registers */ 375_ENTRY(itlb_miss_exit_1) 376 mfspr r10, SPRN_SPRG_SCRATCH0 377 mfspr r11, SPRN_SPRG_SCRATCH1 378#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 379 mfspr r12, SPRN_SPRG_SCRATCH2 380#endif 381 rfi 382#ifdef CONFIG_PERF_EVENTS 383_ENTRY(itlb_miss_perf) 384 lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha 385 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 386 addi r11, r11, 1 387 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 388#endif 389 mfspr r10, SPRN_SPRG_SCRATCH0 390 mfspr r11, SPRN_SPRG_SCRATCH1 391#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 392 mfspr r12, SPRN_SPRG_SCRATCH2 393#endif 394 rfi 395 396#ifdef CONFIG_HUGETLB_PAGE 39710: /* 8M pages */ 398#ifdef CONFIG_PPC_16K_PAGES 399 /* Extract level 2 index */ 400 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 401 /* Add level 2 base */ 402 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 403#else 404 /* Level 2 base */ 405 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK 406#endif 407 lwz r10, 0(r10) /* Get the pte */ 408 b 4b 409 41020: /* 512k pages */ 411 /* Extract level 2 index */ 412 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 413 /* Add level 2 base */ 414 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 415 lwz r10, 0(r10) /* Get the pte */ 416 b 4b 417#endif 418 419 . = 0x1200 420DataStoreTLBMiss: 421 mtspr SPRN_SPRG_SCRATCH0, r10 422 mtspr SPRN_SPRG_SCRATCH1, r11 423 mtspr SPRN_SPRG_SCRATCH2, r12 424 mfcr r12 425 426 /* If we are faulting a kernel address, we have to use the 427 * kernel page tables. 428 */ 429 mfspr r10, SPRN_MD_EPN 430 rlwinm r11, r10, 16, 0xfff8 431 cmpli cr0, r11, PAGE_OFFSET@h 432 mfspr r11, SPRN_M_TW /* Get level 1 table */ 433 blt+ 3f 434 rlwinm r11, r10, 16, 0xfff8 435#ifndef CONFIG_PIN_TLB_IMMR 436 cmpli cr0, r11, VIRT_IMMR_BASE@h 437#endif 438_ENTRY(DTLBMiss_cmp) 439 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 440#ifndef CONFIG_PIN_TLB_IMMR 441_ENTRY(DTLBMiss_jmp) 442 beq- DTLBMissIMMR 443#endif 444 blt cr7, DTLBMissLinear 445 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 4463: 447 448 /* Insert level 1 index */ 449 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 450 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 451 452 /* We have a pte table, so load fetch the pte from the table. 453 */ 454 /* Extract level 2 index */ 455 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 456#ifdef CONFIG_HUGETLB_PAGE 457 mtcr r11 458 bt- 28, 10f /* bit 28 = Large page (8M) */ 459 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */ 460#endif 461 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 462 lwz r10, 0(r10) /* Get the pte */ 4634: 464 mtcr r12 465 466 /* Insert the Guarded flag into the TWC from the Linux PTE. 467 * It is bit 27 of both the Linux PTE and the TWC (at least 468 * I got that right :-). It will be better when we can put 469 * this into the Linux pgd/pmd and load it in the operation 470 * above. 471 */ 472 rlwimi r11, r10, 0, _PAGE_GUARDED 473#ifdef CONFIG_SWAP 474 /* _PAGE_ACCESSED has to be set. We use second APG bit for that, 0 475 * on that bit will represent a Non Access group 476 */ 477 rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1 478#endif 479 mtspr SPRN_MD_TWC, r11 480 481 /* The Linux PTE won't go exactly into the MMU TLB. 482 * Software indicator bits 24, 25, 26, and 27 must be 483 * set. All other Linux PTE bits control the behavior 484 * of the MMU. 485 */ 486 li r11, RPN_PATTERN 487 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */ 488 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 489 490 /* Restore registers */ 491 mtspr SPRN_DAR, r11 /* Tag DAR */ 492_ENTRY(dtlb_miss_exit_1) 493 mfspr r10, SPRN_SPRG_SCRATCH0 494 mfspr r11, SPRN_SPRG_SCRATCH1 495 mfspr r12, SPRN_SPRG_SCRATCH2 496 rfi 497#ifdef CONFIG_PERF_EVENTS 498_ENTRY(dtlb_miss_perf) 499 lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha 500 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 501 addi r11, r11, 1 502 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 503#endif 504 mfspr r10, SPRN_SPRG_SCRATCH0 505 mfspr r11, SPRN_SPRG_SCRATCH1 506 mfspr r12, SPRN_SPRG_SCRATCH2 507 rfi 508 509#ifdef CONFIG_HUGETLB_PAGE 51010: /* 8M pages */ 511 /* Extract level 2 index */ 512#ifdef CONFIG_PPC_16K_PAGES 513 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 514 /* Add level 2 base */ 515 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 516#else 517 /* Level 2 base */ 518 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK 519#endif 520 lwz r10, 0(r10) /* Get the pte */ 521 b 4b 522 52320: /* 512k pages */ 524 /* Extract level 2 index */ 525 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 526 /* Add level 2 base */ 527 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 528 lwz r10, 0(r10) /* Get the pte */ 529 b 4b 530#endif 531 532/* This is an instruction TLB error on the MPC8xx. This could be due 533 * to many reasons, such as executing guarded memory or illegal instruction 534 * addresses. There is nothing to do but handle a big time error fault. 535 */ 536 . = 0x1300 537InstructionTLBError: 538 EXCEPTION_PROLOG 539 mr r4,r12 540 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ 541 andis. r10,r9,SRR1_ISI_NOPT@h 542 beq+ 1f 543 tlbie r4 544itlbie: 545 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 5461: EXC_XFER_LITE(0x400, handle_page_fault) 547 548/* This is the data TLB error on the MPC8xx. This could be due to 549 * many reasons, including a dirty update to a pte. We bail out to 550 * a higher level function that can handle it. 551 */ 552 . = 0x1400 553DataTLBError: 554 mtspr SPRN_SPRG_SCRATCH0, r10 555 mtspr SPRN_SPRG_SCRATCH1, r11 556 mfcr r10 557 558 mfspr r11, SPRN_DAR 559 cmpwi cr0, r11, RPN_PATTERN 560 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 561DARFixed:/* Return from dcbx instruction bug workaround */ 562 EXCEPTION_PROLOG_1 563 EXCEPTION_PROLOG_2 564 mfspr r5,SPRN_DSISR 565 stw r5,_DSISR(r11) 566 mfspr r4,SPRN_DAR 567 andis. r10,r5,DSISR_NOHPTE@h 568 beq+ 1f 569 tlbie r4 570dtlbie: 5711: li r10,RPN_PATTERN 572 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 573 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 574 EXC_XFER_LITE(0x300, handle_page_fault) 575 576 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 577 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 578 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 579 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 580 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 581 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 582 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 583 584/* On the MPC8xx, these next four traps are used for development 585 * support of breakpoints and such. Someday I will get around to 586 * using them. 587 */ 588 . = 0x1c00 589DataBreakpoint: 590 mtspr SPRN_SPRG_SCRATCH0, r10 591 mtspr SPRN_SPRG_SCRATCH1, r11 592 mfcr r10 593 mfspr r11, SPRN_SRR0 594 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l 595 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l 596 beq- cr0, 11f 597 beq- cr7, 11f 598 EXCEPTION_PROLOG_1 599 EXCEPTION_PROLOG_2 600 addi r3,r1,STACK_FRAME_OVERHEAD 601 mfspr r4,SPRN_BAR 602 stw r4,_DAR(r11) 603 mfspr r5,SPRN_DSISR 604 EXC_XFER_EE(0x1c00, do_break) 60511: 606 mtcr r10 607 mfspr r10, SPRN_SPRG_SCRATCH0 608 mfspr r11, SPRN_SPRG_SCRATCH1 609 rfi 610 611#ifdef CONFIG_PERF_EVENTS 612 . = 0x1d00 613InstructionBreakpoint: 614 mtspr SPRN_SPRG_SCRATCH0, r10 615 mtspr SPRN_SPRG_SCRATCH1, r11 616 lis r10, (instruction_counter - PAGE_OFFSET)@ha 617 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10) 618 addi r11, r11, -1 619 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10) 620 lis r10, 0xffff 621 ori r10, r10, 0x01 622 mtspr SPRN_COUNTA, r10 623 mfspr r10, SPRN_SPRG_SCRATCH0 624 mfspr r11, SPRN_SPRG_SCRATCH1 625 rfi 626#else 627 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 628#endif 629 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 630 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 631 632 . = 0x2000 633 634/* 635 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM. 636 * not enough space in the DataStoreTLBMiss area. 637 */ 638DTLBMissIMMR: 639 mtcr r12 640 /* Set 512k byte guarded page and mark it valid and accessed */ 641 li r10, MD_PS512K | MD_GUARDED | MD_SVALID | M_APG2 642 mtspr SPRN_MD_TWC, r10 643 mfspr r10, SPRN_IMMR /* Get current IMMR */ 644 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ 645 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \ 646 _PAGE_PRESENT | _PAGE_NO_CACHE 647 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 648 649 li r11, RPN_PATTERN 650 mtspr SPRN_DAR, r11 /* Tag DAR */ 651_ENTRY(dtlb_miss_exit_2) 652 mfspr r10, SPRN_SPRG_SCRATCH0 653 mfspr r11, SPRN_SPRG_SCRATCH1 654 mfspr r12, SPRN_SPRG_SCRATCH2 655 rfi 656 657DTLBMissLinear: 658 mtcr r12 659 /* Set 8M byte page and mark it valid and accessed */ 660 li r11, MD_PS8MEG | MD_SVALID | M_APG2 661 mtspr SPRN_MD_TWC, r11 662 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 663 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \ 664 _PAGE_PRESENT 665 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 666 667 li r11, RPN_PATTERN 668 mtspr SPRN_DAR, r11 /* Tag DAR */ 669_ENTRY(dtlb_miss_exit_3) 670 mfspr r10, SPRN_SPRG_SCRATCH0 671 mfspr r11, SPRN_SPRG_SCRATCH1 672 mfspr r12, SPRN_SPRG_SCRATCH2 673 rfi 674 675#ifndef CONFIG_PIN_TLB_TEXT 676ITLBMissLinear: 677 mtcr r12 678 /* Set 8M byte page and mark it valid,accessed */ 679 li r11, MI_PS8MEG | MI_SVALID | M_APG2 680 mtspr SPRN_MI_TWC, r11 681 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 682 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \ 683 _PAGE_PRESENT 684 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 685 686_ENTRY(itlb_miss_exit_2) 687 mfspr r10, SPRN_SPRG_SCRATCH0 688 mfspr r11, SPRN_SPRG_SCRATCH1 689 mfspr r12, SPRN_SPRG_SCRATCH2 690 rfi 691#endif 692 693/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 694 * by decoding the registers used by the dcbx instruction and adding them. 695 * DAR is set to the calculated address. 696 */ 697 /* define if you don't want to use self modifying code */ 698#define NO_SELF_MODIFYING_CODE 699FixupDAR:/* Entry point for dcbx workaround. */ 700 mtspr SPRN_SPRG_SCRATCH2, r10 701 /* fetch instruction from memory. */ 702 mfspr r10, SPRN_SRR0 703 rlwinm r11, r10, 16, 0xfff8 704 cmpli cr0, r11, PAGE_OFFSET@h 705 mfspr r11, SPRN_M_TW /* Get level 1 table */ 706 blt+ 3f 707 rlwinm r11, r10, 16, 0xfff8 708_ENTRY(FixupDAR_cmp) 709 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 710 /* create physical page address from effective address */ 711 tophys(r11, r10) 712 blt- cr7, 201f 713 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 714 /* Insert level 1 index */ 7153: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 716 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 717 mtcr r11 718 bt 28,200f /* bit 28 = Large page (8M) */ 719 bt 29,202f /* bit 29 = Large page (8M or 512K) */ 720 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 721 /* Insert level 2 index */ 722 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 723 lwz r11, 0(r11) /* Get the pte */ 724 /* concat physical page address(r11) and page offset(r10) */ 725 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 726201: lwz r11,0(r11) 727/* Check if it really is a dcbx instruction. */ 728/* dcbt and dcbtst does not generate DTLB Misses/Errors, 729 * no need to include them here */ 730 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 731 rlwinm r10, r10, 0, 21, 5 732 cmpwi cr0, r10, 2028 /* Is dcbz? */ 733 beq+ 142f 734 cmpwi cr0, r10, 940 /* Is dcbi? */ 735 beq+ 142f 736 cmpwi cr0, r10, 108 /* Is dcbst? */ 737 beq+ 144f /* Fix up store bit! */ 738 cmpwi cr0, r10, 172 /* Is dcbf? */ 739 beq+ 142f 740 cmpwi cr0, r10, 1964 /* Is icbi? */ 741 beq+ 142f 742141: mfspr r10,SPRN_SPRG_SCRATCH2 743 b DARFixed /* Nope, go back to normal TLB processing */ 744 745 /* concat physical page address(r11) and page offset(r10) */ 746200: 747#ifdef CONFIG_PPC_16K_PAGES 748 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1 749 rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29 750#else 751 rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK 752#endif 753 lwz r11, 0(r11) /* Get the pte */ 754 /* concat physical page address(r11) and page offset(r10) */ 755 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31 756 b 201b 757 758202: 759 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1 760 rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29 761 lwz r11, 0(r11) /* Get the pte */ 762 /* concat physical page address(r11) and page offset(r10) */ 763 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31 764 b 201b 765 766144: mfspr r10, SPRN_DSISR 767 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 768 mtspr SPRN_DSISR, r10 769142: /* continue, it was a dcbx, dcbi instruction. */ 770#ifndef NO_SELF_MODIFYING_CODE 771 andis. r10,r11,0x1f /* test if reg RA is r0 */ 772 li r10,modified_instr@l 773 dcbtst r0,r10 /* touch for store */ 774 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 775 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 776 ori r11,r11,532 777 stw r11,0(r10) /* store add/and instruction */ 778 dcbf 0,r10 /* flush new instr. to memory. */ 779 icbi 0,r10 /* invalidate instr. cache line */ 780 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 781 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 782 isync /* Wait until new instr is loaded from memory */ 783modified_instr: 784 .space 4 /* this is where the add instr. is stored */ 785 bne+ 143f 786 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 787143: mtdar r10 /* store faulting EA in DAR */ 788 mfspr r10,SPRN_SPRG_SCRATCH2 789 b DARFixed /* Go back to normal TLB handling */ 790#else 791 mfctr r10 792 mtdar r10 /* save ctr reg in DAR */ 793 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 794 addi r10, r10, 150f@l /* add start of table */ 795 mtctr r10 /* load ctr with jump address */ 796 xor r10, r10, r10 /* sum starts at zero */ 797 bctr /* jump into table */ 798150: 799 add r10, r10, r0 ;b 151f 800 add r10, r10, r1 ;b 151f 801 add r10, r10, r2 ;b 151f 802 add r10, r10, r3 ;b 151f 803 add r10, r10, r4 ;b 151f 804 add r10, r10, r5 ;b 151f 805 add r10, r10, r6 ;b 151f 806 add r10, r10, r7 ;b 151f 807 add r10, r10, r8 ;b 151f 808 add r10, r10, r9 ;b 151f 809 mtctr r11 ;b 154f /* r10 needs special handling */ 810 mtctr r11 ;b 153f /* r11 needs special handling */ 811 add r10, r10, r12 ;b 151f 812 add r10, r10, r13 ;b 151f 813 add r10, r10, r14 ;b 151f 814 add r10, r10, r15 ;b 151f 815 add r10, r10, r16 ;b 151f 816 add r10, r10, r17 ;b 151f 817 add r10, r10, r18 ;b 151f 818 add r10, r10, r19 ;b 151f 819 add r10, r10, r20 ;b 151f 820 add r10, r10, r21 ;b 151f 821 add r10, r10, r22 ;b 151f 822 add r10, r10, r23 ;b 151f 823 add r10, r10, r24 ;b 151f 824 add r10, r10, r25 ;b 151f 825 add r10, r10, r26 ;b 151f 826 add r10, r10, r27 ;b 151f 827 add r10, r10, r28 ;b 151f 828 add r10, r10, r29 ;b 151f 829 add r10, r10, r30 ;b 151f 830 add r10, r10, r31 831151: 832 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 833 beq 152f /* if reg RA is zero, don't add it */ 834 addi r11, r11, 150b@l /* add start of table */ 835 mtctr r11 /* load ctr with jump address */ 836 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 837 bctr /* jump into table */ 838152: 839 mfdar r11 840 mtctr r11 /* restore ctr reg from DAR */ 841 mtdar r10 /* save fault EA to DAR */ 842 mfspr r10,SPRN_SPRG_SCRATCH2 843 b DARFixed /* Go back to normal TLB handling */ 844 845 /* special handling for r10,r11 since these are modified already */ 846153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 847 add r10, r10, r11 /* add it */ 848 mfctr r11 /* restore r11 */ 849 b 151b 850154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 851 add r10, r10, r11 /* add it */ 852 mfctr r11 /* restore r11 */ 853 b 151b 854#endif 855 856/* 857 * This is where the main kernel code starts. 858 */ 859start_here: 860 /* ptr to current */ 861 lis r2,init_task@h 862 ori r2,r2,init_task@l 863 864 /* ptr to phys current thread */ 865 tophys(r4,r2) 866 addi r4,r4,THREAD /* init task's THREAD */ 867 mtspr SPRN_SPRG_THREAD,r4 868 869 /* stack */ 870 lis r1,init_thread_union@ha 871 addi r1,r1,init_thread_union@l 872 li r0,0 873 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 874 875 lis r6, swapper_pg_dir@ha 876 tophys(r6,r6) 877 mtspr SPRN_M_TW, r6 878 879 bl early_init /* We have to do this with MMU on */ 880 881/* 882 * Decide what sort of machine this is and initialize the MMU. 883 */ 884 li r3,0 885 mr r4,r31 886 bl machine_init 887 bl MMU_init 888 889/* 890 * Go back to running unmapped so we can load up new values 891 * and change to using our exception vectors. 892 * On the 8xx, all we have to do is invalidate the TLB to clear 893 * the old 8M byte TLB mappings and load the page table base register. 894 */ 895 /* The right way to do this would be to track it down through 896 * init's THREAD like the context switch code does, but this is 897 * easier......until someone changes init's static structures. 898 */ 899 lis r4,2f@h 900 ori r4,r4,2f@l 901 tophys(r4,r4) 902 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 903 mtspr SPRN_SRR0,r4 904 mtspr SPRN_SRR1,r3 905 rfi 906/* Load up the kernel context */ 9072: 908 tlbia /* Clear all TLB entries */ 909 sync /* wait for tlbia/tlbie to finish */ 910 911 /* set up the PTE pointers for the Abatron bdiGDB. 912 */ 913 tovirt(r6,r6) 914 lis r5, abatron_pteptrs@h 915 ori r5, r5, abatron_pteptrs@l 916 stw r5, 0xf0(0) /* Must match your Abatron config file */ 917 tophys(r5,r5) 918 stw r6, 0(r5) 919 920/* Now turn on the MMU for real! */ 921 li r4,MSR_KERNEL 922 lis r3,start_kernel@h 923 ori r3,r3,start_kernel@l 924 mtspr SPRN_SRR0,r3 925 mtspr SPRN_SRR1,r4 926 rfi /* enable MMU and jump to start_kernel */ 927 928/* Set up the initial MMU state so we can do the first level of 929 * kernel initialization. This maps the first 8 MBytes of memory 1:1 930 * virtual to physical. Also, set the cache mode since that is defined 931 * by TLB entries and perform any additional mapping (like of the IMMR). 932 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 933 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 934 * these mappings is mapped by page tables. 935 */ 936initial_mmu: 937 li r8, 0 938 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 939 lis r10, MD_RESETVAL@h 940#ifndef CONFIG_8xx_COPYBACK 941 oris r10, r10, MD_WTDEF@h 942#endif 943 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 944 945 tlbia /* Invalidate all TLB entries */ 946#ifdef CONFIG_PIN_TLB_TEXT 947 lis r8, MI_RSV4I@h 948 ori r8, r8, 0x1c00 949 950 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 951#endif 952 953#ifdef CONFIG_PIN_TLB_DATA 954 oris r10, r10, MD_RSV4I@h 955 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 956#endif 957 958 /* Now map the lower 8 Meg into the ITLB. */ 959 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 960 ori r8, r8, MI_EVALID /* Mark it valid */ 961 mtspr SPRN_MI_EPN, r8 962 li r8, MI_PS8MEG /* Set 8M byte page */ 963 ori r8, r8, MI_SVALID | M_APG2 /* Make it valid, APG 2 */ 964 mtspr SPRN_MI_TWC, r8 965 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 966 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 967 968 lis r8, MI_APG_INIT@h /* Set protection modes */ 969 ori r8, r8, MI_APG_INIT@l 970 mtspr SPRN_MI_AP, r8 971 lis r8, MD_APG_INIT@h 972 ori r8, r8, MD_APG_INIT@l 973 mtspr SPRN_MD_AP, r8 974 975 /* Map a 512k page for the IMMR to get the processor 976 * internal registers (among other things). 977 */ 978#ifdef CONFIG_PIN_TLB_IMMR 979 oris r10, r10, MD_RSV4I@h 980 ori r10, r10, 0x1c00 981 mtspr SPRN_MD_CTR, r10 982 983 mfspr r9, 638 /* Get current IMMR */ 984 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ 985 986 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */ 987 ori r8, r8, MD_EVALID /* Mark it valid */ 988 mtspr SPRN_MD_EPN, r8 989 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */ 990 ori r8, r8, MD_SVALID | M_APG2 /* Make it valid and accessed */ 991 mtspr SPRN_MD_TWC, r8 992 mr r8, r9 /* Create paddr for TLB */ 993 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 994 mtspr SPRN_MD_RPN, r8 995#endif 996 997 /* Since the cache is enabled according to the information we 998 * just loaded into the TLB, invalidate and enable the caches here. 999 * We should probably check/set other modes....later. 1000 */ 1001 lis r8, IDC_INVALL@h 1002 mtspr SPRN_IC_CST, r8 1003 mtspr SPRN_DC_CST, r8 1004 lis r8, IDC_ENABLE@h 1005 mtspr SPRN_IC_CST, r8 1006#ifdef CONFIG_8xx_COPYBACK 1007 mtspr SPRN_DC_CST, r8 1008#else 1009 /* For a debug option, I left this here to easily enable 1010 * the write through cache mode 1011 */ 1012 lis r8, DC_SFWT@h 1013 mtspr SPRN_DC_CST, r8 1014 lis r8, IDC_ENABLE@h 1015 mtspr SPRN_DC_CST, r8 1016#endif 1017 /* Disable debug mode entry on breakpoints */ 1018 mfspr r8, SPRN_DER 1019#ifdef CONFIG_PERF_EVENTS 1020 rlwinm r8, r8, 0, ~0xc 1021#else 1022 rlwinm r8, r8, 0, ~0x8 1023#endif 1024 mtspr SPRN_DER, r8 1025 blr 1026 1027 1028/* 1029 * We put a few things here that have to be page-aligned. 1030 * This stuff goes at the beginning of the data segment, 1031 * which is page-aligned. 1032 */ 1033 .data 1034 .globl sdata 1035sdata: 1036 .globl empty_zero_page 1037 .align PAGE_SHIFT 1038empty_zero_page: 1039 .space PAGE_SIZE 1040EXPORT_SYMBOL(empty_zero_page) 1041 1042 .globl swapper_pg_dir 1043swapper_pg_dir: 1044 .space PGD_TABLE_SIZE 1045 1046/* Room for two PTE table poiners, usually the kernel and current user 1047 * pointer to their respective root page table (pgdir). 1048 */ 1049abatron_pteptrs: 1050 .space 8 1051 1052#ifdef CONFIG_PERF_EVENTS 1053 .globl itlb_miss_counter 1054itlb_miss_counter: 1055 .space 4 1056 1057 .globl dtlb_miss_counter 1058dtlb_miss_counter: 1059 .space 4 1060 1061 .globl instruction_counter 1062instruction_counter: 1063 .space 4 1064#endif 1065