1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33 34/* Macro to make the code more readable. */ 35#ifdef CONFIG_8xx_CPU6 36#define DO_8xx_CPU6(val, reg) \ 37 li reg, val; \ 38 stw reg, 12(r0); \ 39 lwz reg, 12(r0); 40#else 41#define DO_8xx_CPU6(val, reg) 42#endif 43 __HEAD 44_ENTRY(_stext); 45_ENTRY(_start); 46 47/* MPC8xx 48 * This port was done on an MBX board with an 860. Right now I only 49 * support an ELF compressed (zImage) boot from EPPC-Bug because the 50 * code there loads up some registers before calling us: 51 * r3: ptr to board info data 52 * r4: initrd_start or if no initrd then 0 53 * r5: initrd_end - unused if r4 is 0 54 * r6: Start of command line string 55 * r7: End of command line string 56 * 57 * I decided to use conditional compilation instead of checking PVR and 58 * adding more processor specific branches around code I don't need. 59 * Since this is an embedded processor, I also appreciate any memory 60 * savings I can get. 61 * 62 * The MPC8xx does not have any BATs, but it supports large page sizes. 63 * We first initialize the MMU to support 8M byte pages, then load one 64 * entry into each of the instruction and data TLBs to map the first 65 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 66 * the "internal" processor registers before MMU_init is called. 67 * 68 * The TLB code currently contains a major hack. Since I use the condition 69 * code register, I have to save and restore it. I am out of registers, so 70 * I just store it in memory location 0 (the TLB handlers are not reentrant). 71 * To avoid making any decisions, I need to use the "segment" valid bit 72 * in the first level table, but that would require many changes to the 73 * Linux page directory/table functions that I don't want to do right now. 74 * 75 * -- Dan 76 */ 77 .globl __start 78__start: 79 mr r31,r3 /* save parameters */ 80 mr r30,r4 81 mr r29,r5 82 mr r28,r6 83 mr r27,r7 84 85 /* We have to turn on the MMU right away so we get cache modes 86 * set correctly. 87 */ 88 bl initial_mmu 89 90/* We now have the lower 8 Meg mapped into TLB entries, and the caches 91 * ready to work. 92 */ 93 94turn_on_mmu: 95 mfmsr r0 96 ori r0,r0,MSR_DR|MSR_IR 97 mtspr SPRN_SRR1,r0 98 lis r0,start_here@h 99 ori r0,r0,start_here@l 100 mtspr SPRN_SRR0,r0 101 SYNC 102 rfi /* enables MMU */ 103 104/* 105 * Exception entry code. This code runs with address translation 106 * turned off, i.e. using physical addresses. 107 * We assume sprg3 has the physical address of the current 108 * task's thread_struct. 109 */ 110#define EXCEPTION_PROLOG \ 111 mtspr SPRN_SPRG_SCRATCH0,r10; \ 112 mtspr SPRN_SPRG_SCRATCH1,r11; \ 113 mfcr r10; \ 114 EXCEPTION_PROLOG_1; \ 115 EXCEPTION_PROLOG_2 116 117#define EXCEPTION_PROLOG_1 \ 118 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 119 andi. r11,r11,MSR_PR; \ 120 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 121 beq 1f; \ 122 mfspr r11,SPRN_SPRG_THREAD; \ 123 lwz r11,THREAD_INFO-THREAD(r11); \ 124 addi r11,r11,THREAD_SIZE; \ 125 tophys(r11,r11); \ 1261: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 127 128 129#define EXCEPTION_PROLOG_2 \ 130 CLR_TOP32(r11); \ 131 stw r10,_CCR(r11); /* save registers */ \ 132 stw r12,GPR12(r11); \ 133 stw r9,GPR9(r11); \ 134 mfspr r10,SPRN_SPRG_SCRATCH0; \ 135 stw r10,GPR10(r11); \ 136 mfspr r12,SPRN_SPRG_SCRATCH1; \ 137 stw r12,GPR11(r11); \ 138 mflr r10; \ 139 stw r10,_LINK(r11); \ 140 mfspr r12,SPRN_SRR0; \ 141 mfspr r9,SPRN_SRR1; \ 142 stw r1,GPR1(r11); \ 143 stw r1,0(r11); \ 144 tovirt(r1,r11); /* set new kernel sp */ \ 145 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 146 MTMSRD(r10); /* (except for mach check in rtas) */ \ 147 stw r0,GPR0(r11); \ 148 SAVE_4GPRS(3, r11); \ 149 SAVE_2GPRS(7, r11) 150 151/* 152 * Note: code which follows this uses cr0.eq (set if from kernel), 153 * r11, r12 (SRR0), and r9 (SRR1). 154 * 155 * Note2: once we have set r1 we are in a position to take exceptions 156 * again, and we could thus set MSR:RI at that point. 157 */ 158 159/* 160 * Exception vectors. 161 */ 162#define EXCEPTION(n, label, hdlr, xfer) \ 163 . = n; \ 164label: \ 165 EXCEPTION_PROLOG; \ 166 addi r3,r1,STACK_FRAME_OVERHEAD; \ 167 xfer(n, hdlr) 168 169#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 170 li r10,trap; \ 171 stw r10,_TRAP(r11); \ 172 li r10,MSR_KERNEL; \ 173 copyee(r10, r9); \ 174 bl tfer; \ 175i##n: \ 176 .long hdlr; \ 177 .long ret 178 179#define COPY_EE(d, s) rlwimi d,s,0,16,16 180#define NOCOPY(d, s) 181 182#define EXC_XFER_STD(n, hdlr) \ 183 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 184 ret_from_except_full) 185 186#define EXC_XFER_LITE(n, hdlr) \ 187 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 188 ret_from_except) 189 190#define EXC_XFER_EE(n, hdlr) \ 191 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 192 ret_from_except_full) 193 194#define EXC_XFER_EE_LITE(n, hdlr) \ 195 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 196 ret_from_except) 197 198/* System reset */ 199 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 200 201/* Machine check */ 202 . = 0x200 203MachineCheck: 204 EXCEPTION_PROLOG 205 mfspr r4,SPRN_DAR 206 stw r4,_DAR(r11) 207 li r5,0x00f0 208 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 209 mfspr r5,SPRN_DSISR 210 stw r5,_DSISR(r11) 211 addi r3,r1,STACK_FRAME_OVERHEAD 212 EXC_XFER_STD(0x200, machine_check_exception) 213 214/* Data access exception. 215 * This is "never generated" by the MPC8xx. We jump to it for other 216 * translation errors. 217 */ 218 . = 0x300 219DataAccess: 220 EXCEPTION_PROLOG 221 mfspr r10,SPRN_DSISR 222 stw r10,_DSISR(r11) 223 mr r5,r10 224 mfspr r4,SPRN_DAR 225 li r10,0x00f0 226 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 227 EXC_XFER_EE_LITE(0x300, handle_page_fault) 228 229/* Instruction access exception. 230 * This is "never generated" by the MPC8xx. We jump to it for other 231 * translation errors. 232 */ 233 . = 0x400 234InstructionAccess: 235 EXCEPTION_PROLOG 236 mr r4,r12 237 mr r5,r9 238 EXC_XFER_EE_LITE(0x400, handle_page_fault) 239 240/* External interrupt */ 241 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 242 243/* Alignment exception */ 244 . = 0x600 245Alignment: 246 EXCEPTION_PROLOG 247 mfspr r4,SPRN_DAR 248 stw r4,_DAR(r11) 249 li r5,0x00f0 250 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 251 mfspr r5,SPRN_DSISR 252 stw r5,_DSISR(r11) 253 addi r3,r1,STACK_FRAME_OVERHEAD 254 EXC_XFER_EE(0x600, alignment_exception) 255 256/* Program check exception */ 257 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 258 259/* No FPU on MPC8xx. This exception is not supposed to happen. 260*/ 261 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 262 263/* Decrementer */ 264 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 265 266 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 267 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 268 269/* System call */ 270 . = 0xc00 271SystemCall: 272 EXCEPTION_PROLOG 273 EXC_XFER_EE_LITE(0xc00, DoSyscall) 274 275/* Single step - not used on 601 */ 276 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 277 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 278 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 279 280/* On the MPC8xx, this is a software emulation interrupt. It occurs 281 * for all unimplemented and illegal instructions. 282 */ 283 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 284 285 . = 0x1100 286/* 287 * For the MPC8xx, this is a software tablewalk to load the instruction 288 * TLB. It is modelled after the example in the Motorola manual. The task 289 * switch loads the M_TWB register with the pointer to the first level table. 290 * If we discover there is no second level table (value is zero) or if there 291 * is an invalid pte, we load that into the TLB, which causes another fault 292 * into the TLB Error interrupt where we can handle such problems. 293 * We have to use the MD_xxx registers for the tablewalk because the 294 * equivalent MI_xxx registers only perform the attribute functions. 295 */ 296InstructionTLBMiss: 297#ifdef CONFIG_8xx_CPU6 298 stw r3, 8(r0) 299#endif 300 DO_8xx_CPU6(0x3f80, r3) 301 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 302 mfcr r10 303#ifdef CONFIG_8xx_CPU6 304 stw r10, 0(r0) 305 stw r11, 4(r0) 306#else 307 mtspr SPRN_DAR, r10 308 mtspr SPRN_SPRG2, r11 309#endif 310 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 311#ifdef CONFIG_8xx_CPU15 312 addi r11, r10, 0x1000 313 tlbie r11 314 addi r11, r10, -0x1000 315 tlbie r11 316#endif 317 DO_8xx_CPU6(0x3780, r3) 318 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ 319 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 320 321 /* If we are faulting a kernel address, we have to use the 322 * kernel page tables. 323 */ 324#ifdef CONFIG_MODULES 325 /* Only modules will cause ITLB Misses as we always 326 * pin the first 8MB of kernel memory */ 327 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ 328 beq 3f 329 lis r11, swapper_pg_dir@h 330 ori r11, r11, swapper_pg_dir@l 331 rlwimi r10, r11, 0, 2, 19 3323: 333#endif 334 lwz r11, 0(r10) /* Get the level 1 entry */ 335 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 336 beq 2f /* If zero, don't try to find a pte */ 337 338 /* We have a pte table, so load the MI_TWC with the attributes 339 * for this "segment." 340 */ 341 ori r11,r11,1 /* Set valid bit */ 342 DO_8xx_CPU6(0x2b80, r3) 343 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 344 DO_8xx_CPU6(0x3b80, r3) 345 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 346 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 347 lwz r10, 0(r11) /* Get the pte */ 348 349#ifdef CONFIG_SWAP 350 andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT 351 cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT 352 bne- cr0, 2f 353#endif 354 /* The Linux PTE won't go exactly into the MMU TLB. 355 * Software indicator bits 21 and 28 must be clear. 356 * Software indicator bits 24, 25, 26, and 27 must be 357 * set. All other Linux PTE bits control the behavior 358 * of the MMU. 359 */ 360 li r11, 0x00f0 361 rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ 362 DO_8xx_CPU6(0x2d80, r3) 363 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 364 365 /* Restore registers */ 366#ifndef CONFIG_8xx_CPU6 367 mfspr r10, SPRN_DAR 368 mtcr r10 369 mtspr SPRN_DAR, r11 /* Tag DAR */ 370 mfspr r11, SPRN_SPRG2 371#else 372 lwz r11, 0(r0) 373 mtcr r11 374 lwz r11, 4(r0) 375 lwz r3, 8(r0) 376#endif 377 mfspr r10, SPRN_M_TW 378 rfi 3792: 380 mfspr r11, SPRN_SRR1 381 /* clear all error bits as TLB Miss 382 * sets a few unconditionally 383 */ 384 rlwinm r11, r11, 0, 0xffff 385 mtspr SPRN_SRR1, r11 386 387 /* Restore registers */ 388#ifndef CONFIG_8xx_CPU6 389 mfspr r10, SPRN_DAR 390 mtcr r10 391 li r11, 0x00f0 392 mtspr SPRN_DAR, r11 /* Tag DAR */ 393 mfspr r11, SPRN_SPRG2 394#else 395 lwz r11, 0(r0) 396 mtcr r11 397 lwz r11, 4(r0) 398 lwz r3, 8(r0) 399#endif 400 mfspr r10, SPRN_M_TW 401 b InstructionAccess 402 403 . = 0x1200 404DataStoreTLBMiss: 405#ifdef CONFIG_8xx_CPU6 406 stw r3, 8(r0) 407#endif 408 DO_8xx_CPU6(0x3f80, r3) 409 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 410 mfcr r10 411#ifdef CONFIG_8xx_CPU6 412 stw r10, 0(r0) 413 stw r11, 4(r0) 414#else 415 mtspr SPRN_DAR, r10 416 mtspr SPRN_SPRG2, r11 417#endif 418 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 419 420 /* If we are faulting a kernel address, we have to use the 421 * kernel page tables. 422 */ 423 andi. r11, r10, 0x0800 424 beq 3f 425 lis r11, swapper_pg_dir@h 426 ori r11, r11, swapper_pg_dir@l 427 rlwimi r10, r11, 0, 2, 19 4283: 429 lwz r11, 0(r10) /* Get the level 1 entry */ 430 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 431 beq 2f /* If zero, don't try to find a pte */ 432 433 /* We have a pte table, so load fetch the pte from the table. 434 */ 435 ori r11, r11, 1 /* Set valid bit in physical L2 page */ 436 DO_8xx_CPU6(0x3b80, r3) 437 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 438 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ 439 lwz r10, 0(r10) /* Get the pte */ 440 441 /* Insert the Guarded flag into the TWC from the Linux PTE. 442 * It is bit 27 of both the Linux PTE and the TWC (at least 443 * I got that right :-). It will be better when we can put 444 * this into the Linux pgd/pmd and load it in the operation 445 * above. 446 */ 447 rlwimi r11, r10, 0, 27, 27 448 /* Insert the WriteThru flag into the TWC from the Linux PTE. 449 * It is bit 25 in the Linux PTE and bit 30 in the TWC 450 */ 451 rlwimi r11, r10, 32-5, 30, 30 452 DO_8xx_CPU6(0x3b80, r3) 453 mtspr SPRN_MD_TWC, r11 454 455 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 456 * We also need to know if the insn is a load/store, so: 457 * Clear _PAGE_PRESENT and load that which will 458 * trap into DTLB Error with store bit set accordinly. 459 */ 460 /* PRESENT=0x1, ACCESSED=0x20 461 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 462 * r10 = (r10 & ~PRESENT) | r11; 463 */ 464#ifdef CONFIG_SWAP 465 rlwinm r11, r10, 32-5, _PAGE_PRESENT 466 and r11, r11, r10 467 rlwimi r10, r11, 0, _PAGE_PRESENT 468#endif 469 /* Honour kernel RO, User NA */ 470 /* 0x200 == Extended encoding, bit 22 */ 471 rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */ 472 /* r11 = (r10 & _PAGE_RW) >> 1 */ 473 rlwinm r11, r10, 32-1, 0x200 474 or r10, r11, r10 475 /* invert RW and 0x200 bits */ 476 xori r10, r10, _PAGE_RW | 0x200 477 478 /* The Linux PTE won't go exactly into the MMU TLB. 479 * Software indicator bits 22 and 28 must be clear. 480 * Software indicator bits 24, 25, 26, and 27 must be 481 * set. All other Linux PTE bits control the behavior 482 * of the MMU. 483 */ 4842: li r11, 0x00f0 485 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 486 DO_8xx_CPU6(0x3d80, r3) 487 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 488 489 /* Restore registers */ 490#ifndef CONFIG_8xx_CPU6 491 mfspr r10, SPRN_DAR 492 mtcr r10 493 mtspr SPRN_DAR, r11 /* Tag DAR */ 494 mfspr r11, SPRN_SPRG2 495#else 496 mtspr SPRN_DAR, r11 /* Tag DAR */ 497 lwz r11, 0(r0) 498 mtcr r11 499 lwz r11, 4(r0) 500 lwz r3, 8(r0) 501#endif 502 mfspr r10, SPRN_M_TW 503 rfi 504 505/* This is an instruction TLB error on the MPC8xx. This could be due 506 * to many reasons, such as executing guarded memory or illegal instruction 507 * addresses. There is nothing to do but handle a big time error fault. 508 */ 509 . = 0x1300 510InstructionTLBError: 511 b InstructionAccess 512 513/* This is the data TLB error on the MPC8xx. This could be due to 514 * many reasons, including a dirty update to a pte. We can catch that 515 * one here, but anything else is an error. First, we track down the 516 * Linux pte. If it is valid, write access is allowed, but the 517 * page dirty bit is not set, we will set it and reload the TLB. For 518 * any other case, we bail out to a higher level function that can 519 * handle it. 520 */ 521 . = 0x1400 522DataTLBError: 523#ifdef CONFIG_8xx_CPU6 524 stw r3, 8(r0) 525#endif 526 DO_8xx_CPU6(0x3f80, r3) 527 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 528 mfcr r10 529 stw r10, 0(r0) 530 stw r11, 4(r0) 531 532 mfspr r10, SPRN_DAR 533 cmpwi cr0, r10, 0x00f0 534 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 535DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ 536 mfspr r10, SPRN_M_TW /* Restore registers */ 537 lwz r11, 0(r0) 538 mtcr r11 539 lwz r11, 4(r0) 540#ifdef CONFIG_8xx_CPU6 541 lwz r3, 8(r0) 542#endif 543 b DataAccess 544 545 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 546 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 547 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 548 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 549 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 550 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 551 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 552 553/* On the MPC8xx, these next four traps are used for development 554 * support of breakpoints and such. Someday I will get around to 555 * using them. 556 */ 557 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 558 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 559 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 560 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 561 562 . = 0x2000 563 564/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 565 * by decoding the registers used by the dcbx instruction and adding them. 566 * DAR is set to the calculated address and r10 also holds the EA on exit. 567 */ 568 /* define if you don't want to use self modifying code */ 569#define NO_SELF_MODIFYING_CODE 570FixupDAR:/* Entry point for dcbx workaround. */ 571 /* fetch instruction from memory. */ 572 mfspr r10, SPRN_SRR0 573 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ 574 DO_8xx_CPU6(0x3780, r3) 575 mtspr SPRN_MD_EPN, r10 576 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ 577 beq- 3f /* Branch if user space */ 578 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h 579 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l 580 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ 5813: lwz r11, 0(r11) /* Get the level 1 entry */ 582 DO_8xx_CPU6(0x3b80, r3) 583 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 584 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 585 lwz r11, 0(r11) /* Get the pte */ 586 /* concat physical page address(r11) and page offset(r10) */ 587 rlwimi r11, r10, 0, 20, 31 588 lwz r11,0(r11) 589/* Check if it really is a dcbx instruction. */ 590/* dcbt and dcbtst does not generate DTLB Misses/Errors, 591 * no need to include them here */ 592 srwi r10, r11, 26 /* check if major OP code is 31 */ 593 cmpwi cr0, r10, 31 594 bne- 141f 595 rlwinm r10, r11, 0, 21, 30 596 cmpwi cr0, r10, 2028 /* Is dcbz? */ 597 beq+ 142f 598 cmpwi cr0, r10, 940 /* Is dcbi? */ 599 beq+ 142f 600 cmpwi cr0, r10, 108 /* Is dcbst? */ 601 beq+ 144f /* Fix up store bit! */ 602 cmpwi cr0, r10, 172 /* Is dcbf? */ 603 beq+ 142f 604 cmpwi cr0, r10, 1964 /* Is icbi? */ 605 beq+ 142f 606141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ 607 b DARFixed /* Nope, go back to normal TLB processing */ 608 609144: mfspr r10, SPRN_DSISR 610 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 611 mtspr SPRN_DSISR, r10 612142: /* continue, it was a dcbx, dcbi instruction. */ 613#ifdef CONFIG_8xx_CPU6 614 lwz r3, 8(r0) /* restore r3 from memory */ 615#endif 616#ifndef NO_SELF_MODIFYING_CODE 617 andis. r10,r11,0x1f /* test if reg RA is r0 */ 618 li r10,modified_instr@l 619 dcbtst r0,r10 /* touch for store */ 620 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 621 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 622 ori r11,r11,532 623 stw r11,0(r10) /* store add/and instruction */ 624 dcbf 0,r10 /* flush new instr. to memory. */ 625 icbi 0,r10 /* invalidate instr. cache line */ 626 lwz r11, 4(r0) /* restore r11 from memory */ 627 mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ 628 isync /* Wait until new instr is loaded from memory */ 629modified_instr: 630 .space 4 /* this is where the add instr. is stored */ 631 bne+ 143f 632 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 633143: mtdar r10 /* store faulting EA in DAR */ 634 b DARFixed /* Go back to normal TLB handling */ 635#else 636 mfctr r10 637 mtdar r10 /* save ctr reg in DAR */ 638 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 639 addi r10, r10, 150f@l /* add start of table */ 640 mtctr r10 /* load ctr with jump address */ 641 xor r10, r10, r10 /* sum starts at zero */ 642 bctr /* jump into table */ 643150: 644 add r10, r10, r0 ;b 151f 645 add r10, r10, r1 ;b 151f 646 add r10, r10, r2 ;b 151f 647 add r10, r10, r3 ;b 151f 648 add r10, r10, r4 ;b 151f 649 add r10, r10, r5 ;b 151f 650 add r10, r10, r6 ;b 151f 651 add r10, r10, r7 ;b 151f 652 add r10, r10, r8 ;b 151f 653 add r10, r10, r9 ;b 151f 654 mtctr r11 ;b 154f /* r10 needs special handling */ 655 mtctr r11 ;b 153f /* r11 needs special handling */ 656 add r10, r10, r12 ;b 151f 657 add r10, r10, r13 ;b 151f 658 add r10, r10, r14 ;b 151f 659 add r10, r10, r15 ;b 151f 660 add r10, r10, r16 ;b 151f 661 add r10, r10, r17 ;b 151f 662 add r10, r10, r18 ;b 151f 663 add r10, r10, r19 ;b 151f 664 add r10, r10, r20 ;b 151f 665 add r10, r10, r21 ;b 151f 666 add r10, r10, r22 ;b 151f 667 add r10, r10, r23 ;b 151f 668 add r10, r10, r24 ;b 151f 669 add r10, r10, r25 ;b 151f 670 add r10, r10, r26 ;b 151f 671 add r10, r10, r27 ;b 151f 672 add r10, r10, r28 ;b 151f 673 add r10, r10, r29 ;b 151f 674 add r10, r10, r30 ;b 151f 675 add r10, r10, r31 676151: 677 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 678 beq 152f /* if reg RA is zero, don't add it */ 679 addi r11, r11, 150b@l /* add start of table */ 680 mtctr r11 /* load ctr with jump address */ 681 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 682 bctr /* jump into table */ 683152: 684 mfdar r11 685 mtctr r11 /* restore ctr reg from DAR */ 686 mtdar r10 /* save fault EA to DAR */ 687 b DARFixed /* Go back to normal TLB handling */ 688 689 /* special handling for r10,r11 since these are modified already */ 690153: lwz r11, 4(r0) /* load r11 from memory */ 691 b 155f 692154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */ 693155: add r10, r10, r11 /* add it */ 694 mfctr r11 /* restore r11 */ 695 b 151b 696#endif 697 698 .globl giveup_fpu 699giveup_fpu: 700 blr 701 702/* 703 * This is where the main kernel code starts. 704 */ 705start_here: 706 /* ptr to current */ 707 lis r2,init_task@h 708 ori r2,r2,init_task@l 709 710 /* ptr to phys current thread */ 711 tophys(r4,r2) 712 addi r4,r4,THREAD /* init task's THREAD */ 713 mtspr SPRN_SPRG_THREAD,r4 714 715 /* stack */ 716 lis r1,init_thread_union@ha 717 addi r1,r1,init_thread_union@l 718 li r0,0 719 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 720 721 bl early_init /* We have to do this with MMU on */ 722 723/* 724 * Decide what sort of machine this is and initialize the MMU. 725 */ 726 mr r3,r31 727 mr r4,r30 728 mr r5,r29 729 mr r6,r28 730 mr r7,r27 731 bl machine_init 732 bl MMU_init 733 734/* 735 * Go back to running unmapped so we can load up new values 736 * and change to using our exception vectors. 737 * On the 8xx, all we have to do is invalidate the TLB to clear 738 * the old 8M byte TLB mappings and load the page table base register. 739 */ 740 /* The right way to do this would be to track it down through 741 * init's THREAD like the context switch code does, but this is 742 * easier......until someone changes init's static structures. 743 */ 744 lis r6, swapper_pg_dir@h 745 ori r6, r6, swapper_pg_dir@l 746 tophys(r6,r6) 747#ifdef CONFIG_8xx_CPU6 748 lis r4, cpu6_errata_word@h 749 ori r4, r4, cpu6_errata_word@l 750 li r3, 0x3980 751 stw r3, 12(r4) 752 lwz r3, 12(r4) 753#endif 754 mtspr SPRN_M_TWB, r6 755 lis r4,2f@h 756 ori r4,r4,2f@l 757 tophys(r4,r4) 758 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 759 mtspr SPRN_SRR0,r4 760 mtspr SPRN_SRR1,r3 761 rfi 762/* Load up the kernel context */ 7632: 764 SYNC /* Force all PTE updates to finish */ 765 tlbia /* Clear all TLB entries */ 766 sync /* wait for tlbia/tlbie to finish */ 767 TLBSYNC /* ... on all CPUs */ 768 769 /* set up the PTE pointers for the Abatron bdiGDB. 770 */ 771 tovirt(r6,r6) 772 lis r5, abatron_pteptrs@h 773 ori r5, r5, abatron_pteptrs@l 774 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 775 tophys(r5,r5) 776 stw r6, 0(r5) 777 778/* Now turn on the MMU for real! */ 779 li r4,MSR_KERNEL 780 lis r3,start_kernel@h 781 ori r3,r3,start_kernel@l 782 mtspr SPRN_SRR0,r3 783 mtspr SPRN_SRR1,r4 784 rfi /* enable MMU and jump to start_kernel */ 785 786/* Set up the initial MMU state so we can do the first level of 787 * kernel initialization. This maps the first 8 MBytes of memory 1:1 788 * virtual to physical. Also, set the cache mode since that is defined 789 * by TLB entries and perform any additional mapping (like of the IMMR). 790 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 791 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by 792 * these mappings is mapped by page tables. 793 */ 794initial_mmu: 795 tlbia /* Invalidate all TLB entries */ 796/* Always pin the first 8 MB ITLB to prevent ITLB 797 misses while mucking around with SRR0/SRR1 in asm 798*/ 799 lis r8, MI_RSV4I@h 800 ori r8, r8, 0x1c00 801 802 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 803 804#ifdef CONFIG_PIN_TLB 805 lis r10, (MD_RSV4I | MD_RESETVAL)@h 806 ori r10, r10, 0x1c00 807 mr r8, r10 808#else 809 lis r10, MD_RESETVAL@h 810#endif 811#ifndef CONFIG_8xx_COPYBACK 812 oris r10, r10, MD_WTDEF@h 813#endif 814 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 815 816 /* Now map the lower 8 Meg into the TLBs. For this quick hack, 817 * we can load the instruction and data TLB registers with the 818 * same values. 819 */ 820 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 821 ori r8, r8, MI_EVALID /* Mark it valid */ 822 mtspr SPRN_MI_EPN, r8 823 mtspr SPRN_MD_EPN, r8 824 li r8, MI_PS8MEG /* Set 8M byte page */ 825 ori r8, r8, MI_SVALID /* Make it valid */ 826 mtspr SPRN_MI_TWC, r8 827 mtspr SPRN_MD_TWC, r8 828 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 829 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 830 mtspr SPRN_MD_RPN, r8 831 lis r8, MI_Kp@h /* Set the protection mode */ 832 mtspr SPRN_MI_AP, r8 833 mtspr SPRN_MD_AP, r8 834 835 /* Map another 8 MByte at the IMMR to get the processor 836 * internal registers (among other things). 837 */ 838#ifdef CONFIG_PIN_TLB 839 addi r10, r10, 0x0100 840 mtspr SPRN_MD_CTR, r10 841#endif 842 mfspr r9, 638 /* Get current IMMR */ 843 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ 844 845 mr r8, r9 /* Create vaddr for TLB */ 846 ori r8, r8, MD_EVALID /* Mark it valid */ 847 mtspr SPRN_MD_EPN, r8 848 li r8, MD_PS8MEG /* Set 8M byte page */ 849 ori r8, r8, MD_SVALID /* Make it valid */ 850 mtspr SPRN_MD_TWC, r8 851 mr r8, r9 /* Create paddr for TLB */ 852 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 853 mtspr SPRN_MD_RPN, r8 854 855#ifdef CONFIG_PIN_TLB 856 /* Map two more 8M kernel data pages. 857 */ 858 addi r10, r10, 0x0100 859 mtspr SPRN_MD_CTR, r10 860 861 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 862 addis r8, r8, 0x0080 /* Add 8M */ 863 ori r8, r8, MI_EVALID /* Mark it valid */ 864 mtspr SPRN_MD_EPN, r8 865 li r9, MI_PS8MEG /* Set 8M byte page */ 866 ori r9, r9, MI_SVALID /* Make it valid */ 867 mtspr SPRN_MD_TWC, r9 868 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 869 addis r11, r11, 0x0080 /* Add 8M */ 870 mtspr SPRN_MD_RPN, r11 871 872 addis r8, r8, 0x0080 /* Add 8M */ 873 mtspr SPRN_MD_EPN, r8 874 mtspr SPRN_MD_TWC, r9 875 addis r11, r11, 0x0080 /* Add 8M */ 876 mtspr SPRN_MD_RPN, r11 877#endif 878 879 /* Since the cache is enabled according to the information we 880 * just loaded into the TLB, invalidate and enable the caches here. 881 * We should probably check/set other modes....later. 882 */ 883 lis r8, IDC_INVALL@h 884 mtspr SPRN_IC_CST, r8 885 mtspr SPRN_DC_CST, r8 886 lis r8, IDC_ENABLE@h 887 mtspr SPRN_IC_CST, r8 888#ifdef CONFIG_8xx_COPYBACK 889 mtspr SPRN_DC_CST, r8 890#else 891 /* For a debug option, I left this here to easily enable 892 * the write through cache mode 893 */ 894 lis r8, DC_SFWT@h 895 mtspr SPRN_DC_CST, r8 896 lis r8, IDC_ENABLE@h 897 mtspr SPRN_DC_CST, r8 898#endif 899 blr 900 901 902/* 903 * Set up to use a given MMU context. 904 * r3 is context number, r4 is PGD pointer. 905 * 906 * We place the physical address of the new task page directory loaded 907 * into the MMU base register, and set the ASID compare register with 908 * the new "context." 909 */ 910_GLOBAL(set_context) 911 912#ifdef CONFIG_BDI_SWITCH 913 /* Context switch the PTE pointer for the Abatron BDI2000. 914 * The PGDIR is passed as second argument. 915 */ 916 lis r5, KERNELBASE@h 917 lwz r5, 0xf0(r5) 918 stw r4, 0x4(r5) 919#endif 920 921#ifdef CONFIG_8xx_CPU6 922 lis r6, cpu6_errata_word@h 923 ori r6, r6, cpu6_errata_word@l 924 tophys (r4, r4) 925 li r7, 0x3980 926 stw r7, 12(r6) 927 lwz r7, 12(r6) 928 mtspr SPRN_M_TWB, r4 /* Update MMU base address */ 929 li r7, 0x3380 930 stw r7, 12(r6) 931 lwz r7, 12(r6) 932 mtspr SPRN_M_CASID, r3 /* Update context */ 933#else 934 mtspr SPRN_M_CASID,r3 /* Update context */ 935 tophys (r4, r4) 936 mtspr SPRN_M_TWB, r4 /* and pgd */ 937#endif 938 SYNC 939 blr 940 941#ifdef CONFIG_8xx_CPU6 942/* It's here because it is unique to the 8xx. 943 * It is important we get called with interrupts disabled. I used to 944 * do that, but it appears that all code that calls this already had 945 * interrupt disabled. 946 */ 947 .globl set_dec_cpu6 948set_dec_cpu6: 949 lis r7, cpu6_errata_word@h 950 ori r7, r7, cpu6_errata_word@l 951 li r4, 0x2c00 952 stw r4, 8(r7) 953 lwz r4, 8(r7) 954 mtspr 22, r3 /* Update Decrementer */ 955 SYNC 956 blr 957#endif 958 959/* 960 * We put a few things here that have to be page-aligned. 961 * This stuff goes at the beginning of the data segment, 962 * which is page-aligned. 963 */ 964 .data 965 .globl sdata 966sdata: 967 .globl empty_zero_page 968empty_zero_page: 969 .space 4096 970 971 .globl swapper_pg_dir 972swapper_pg_dir: 973 .space 4096 974 975/* Room for two PTE table poiners, usually the kernel and current user 976 * pointer to their respective root page table (pgdir). 977 */ 978abatron_pteptrs: 979 .space 8 980 981#ifdef CONFIG_8xx_CPU6 982 .globl cpu6_errata_word 983cpu6_errata_word: 984 .space 16 985#endif 986 987